CN1157644C - Computer system backing up different type of DRAMs - Google Patents
Computer system backing up different type of DRAMs Download PDFInfo
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- CN1157644C CN1157644C CNB001374176A CN00137417A CN1157644C CN 1157644 C CN1157644 C CN 1157644C CN B001374176 A CNB001374176 A CN B001374176A CN 00137417 A CN00137417 A CN 00137417A CN 1157644 C CN1157644 C CN 1157644C
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Abstract
The present invention relates to a computer system supporting different types of dynamic random access memories, which comprises a first slot, a second slot, a north bridge chip for respectively supporting the first kind of slot and the second kind of slot, and a control circuit for connecting the north bridge chip. The first slot is used for installed the first kind of dynamic random access memory. The first slot comprises a plurality of first slot pins, and each first slot pin is defined corresponding to a first pin. The second slot is used for installing the second kind of dynamic random access memory. The second slot comprises a plurality of second slot pins, and each second slot pin is defined corresponding to a second pin.
Description
Technical field
The present invention relates to a kind of computer system of supporting dissimilar dynamic RAM, particularly relate to a kind of computer system of supporting double Data Dynamic random access memory (DDRAM) and Synchronous Dynamic Random Access Memory (SDRAM).
Background technology
Double Data Dynamic random access memory (DDRAM) has become following main trend of dynamic RAM (DRAM) with the double linear memory assembly slot (184pin DIMM) with 184 pins.Yet, be converted to DDRAM fully and 184pin DIMM still has one period suitable market transitional period from Synchronous Dynamic Random Access Memory (SDRAM) and the double linear memory assembly slot (168pin DIMM) with 168 pins.
Because the pin definitions (pin assignment) of 184pin DIMM and 168pin DIMM is inequality, therefore, support the computer system of DDRAM and 184pin DIMM just can't support SDRAM and 168pin DIMM, and support the computer system of SDRAM and 168pin DIMM just can't support DDRAM and 184pin DIMM.Therefore, switch transition is interim in market, and the user can produce suitable puzzlement and trouble in the selection and upgrading of specification.
Summary of the invention
Therefore, fundamental purpose of the present invention is to provide a kind of computer system that can support double Data Dynamic random access memory (DDRAM) and synchronous dynamic dynamic RAM (SDRAM) simultaneously, to solve the above problems.
In order to realize purpose of the present invention, the invention provides the computer system of the dynamic RAM of a kind of dynamic RAM that is used for supporting a first kind and one second type, it comprises: a motherboard comprises one first plane and one second plane; One first slot is installed on first plane of this motherboard, is used for installing the dynamic RAM of this first kind, and this first slot comprises a plurality of first slot pins, and each first slot pin is corresponding to one first pin definitions; One second slot is installed on first plane of this motherboard, is used for installing the dynamic RAM of this second type, and this second slot comprises a plurality of second slot pins, and each second slot pin is corresponding to one second pin definitions; Many conducting paths; One north bridge chips is installed on first plane of this motherboard, and it comprises a plurality of chip pins, is connected in this first slot and this second slot via this conducting path, and each chip pin is corresponding to one first pin definitions and one second pin definitions; And a control circuit, be installed on first plane of this motherboard and be connected in this north bridge chips, be used for setting the pin definitions of this chip pin; Wherein, this control circuit is imported this north bridge chips with one first control signal, and the pin definitions of this chip pin can be made as this first pin definitions, makes this north bridge chips to carry out data transmission with this dynamic RAM of first type; This control circuit is imported this north bridge chips with one second control signal, and the pin definitions of this chip pin can be made as this second pin definitions, makes this north bridge chips to carry out data transmission with the dynamic RAM of this second type.
The present invention also provides a kind of computer system that is used for supporting an a pair of haplotype data dynamic RAM and a synchronous dynamic RAM, and it comprises: a motherboard comprises one first plane and one second plane; One first slot, be installed on first plane of this motherboard, be used for installing this double Data Dynamic random access memory, this first slot comprises a plurality of first slot pins, each first slot pin is corresponding to one first pin definitions, and this first pin definitions belongs to a plurality of pin definitions group respectively; One second slot, be installed on first plane of this motherboard, be used for installing this Synchronous Dynamic Random Access Memory, this second slot comprises a plurality of second slot pins, each second slot pin is corresponding to one second pin definitions, and this second pin definitions belongs to this a plurality of pin definitions group respectively; Many conducting paths; One north bridge chips, be installed on first plane of this motherboard, it comprises a plurality of chip pins, be connected in this first slot and this second slot via this conducting path, each chip pin is corresponding to one first pin definitions and one second pin definitions, and this first pin definitions and this second pin definitions belong to same pin definitions group; And a control circuit, be installed on first plane of this motherboard and be connected in this north bridge chips, be used for setting the pin definitions of this chip pin; Wherein, this control circuit is imported this north bridge chips with one first control signal, and the pin definitions of this chip pin can be made as this first pin definitions, makes this north bridge chips to carry out data transmission with this double Data Dynamic random access memory; And when this control circuit was imported this north bridge chips with one second control signal, the pin definitions of this chip pin can be made as this second pin definitions, made this north bridge chips to carry out data transmission with this Synchronous Dynamic Random Access Memory.
Description of drawings
Fig. 1 is the synoptic diagram of computer system of the present invention.
Fig. 2 is the synoptic diagram of first slot.
Fig. 3 is pin definitions group table.
Fig. 4 is the synoptic diagram of second slot.
Fig. 5 is the pin definitions corresponding tables of the chip pin of north bridge chips.
Fig. 6 is the synoptic diagram on first plane of the motherboard of computer system of the present invention.
Fig. 7 is the synoptic diagram on second plane of the motherboard of computer system of the present invention.
Embodiment
See also Fig. 1.Fig. 1 is the synoptic diagram of computer system 10 of the present invention.Computer system 10 can be supported two types dynamic RAM simultaneously.Wherein, first type dynamic RAM is a double Data Dynamic random access memory (DDRAM), and second type dynamic RAM is a synchronous dynamic RAM (SDRAM).Computer system 10 comprises one first slot, 12, one second slots, 14, one north bridge chips, 16, one control circuits 18, and a testing circuit 20.
Please refer to Fig. 2.Fig. 2 is the synoptic diagram of first slot 12.First slot 12 is used for installing double Data Dynamic random access memory (DDRAM) for having the double linear memory assembly slot (184pin DIMM) of 184 pins.First slot 12 comprises a plurality of pins, and each pin is corresponding to one first pin definitions.
See also Fig. 3.Fig. 3 is pin definitions group table.Pairing first pin definitions of pin that first slot 12 is used for being connected in north bridge chips 16 belongs to data pins definition group respectively, address pins definition group, and order pin definitions group.For example, pin definitions is MD[0:63] be to belong to data pins definition group.
See also Fig. 4.Fig. 4 is the synoptic diagram of second slot 14.Second slot 14 is used for installing Synchronous Dynamic Random Access Memory (SDRAM) for having the double linear memory assembly slot (168pin DIMM) of 168 pins.Second slot 14 comprises a plurality of pins, and each pin is corresponding to one second pin definitions.
As shown in Figure 3, pairing second pin definitions of pin that second slot 14 is used for being connected in north bridge chips 16 belongs to data pins definition group respectively, address pins definition group, and order pin definitions group.For example, pin definitions is MD[0:63] be to belong to data pins definition group.
As shown in Figure 1, testing circuit 20 is to be electrically connected on control circuit 18.When testing circuit 20 detects double Data Dynamic random access memory and is installed on first slot 12, testing circuit 20 can transmission one first detection signal to control circuit 18, make control circuit 18 one first control signal can be inputed to north bridge chips 16.At this moment, the pin definitions of the chip pin of north bridge chips 16 can be made as first pin definitions, makes north bridge chips 16 to carry out data transmission with double Data Dynamic random access memory.
When testing circuit 20 detects Synchronous Dynamic Random Access Memory and is installed on second slot 14, testing circuit 20 can transmission one second detection signal to control circuit 18, make control circuit 18 one second control signal can be inputed to north bridge chips 16.At this moment, the pin definitions of the chip pin of north bridge chips 16 can be made as second pin definitions, makes north bridge chips 16 to carry out data transmission with Synchronous Dynamic Random Access Memory.
For example, control circuit 18 can utilize other pins (non-chip pin) of north bridge chips 16, as the AD18 (not shown), sets the pin definitions of the chip pin (Fig. 5 is listed) of north bridge chips 16.When pin AD18 was a high position, the pin definitions of the chip pin of north bridge chips 16 can be made as first pin definitions, to support the DDR memory assembly.And when pin AD18 was electronegative potential, the pin definitions of the chip pin of north bridge chips 16 can be made as second pin definitions, to support the SDR memory assembly.
In the present invention, north bridge chips must be supported two kinds of memory assemblies, therefore, in order to implement the present invention, arranges at the arrangements of components and the pin of motherboard, must the suitable thought of cost.In known technology, the research and development slip-stick artist is definition chip functions, decision number of pins earlier, and arranges pin positions, then design circuit and make motherboard according to this.Because pin positions is fixed, therefore in the process of circuit layout (layout), usually can on motherboard, produce unnecessary perforation, change layer, and the situation that strides across different electrical power district (promptly striding Moat), thereby produce unpredictable noise and interference.In the lower epoch of previous calculation machine frequency of operation, its influence still can be accepted.Yet, entering the high frequency epoch now, these problems often cause customer requirement to stipulate pin positions again, and cause great loss on research and development of products time and cost.
Therefore, in implementation process of the present invention, the research and development slip-stick artist is after the decision number of pins, and the slot pin that can consider earlier first slot and second slot different in arrangement are to determine the configuration (placement) of first slot and second slot.When first slot is just being put second slot being put upside down, both pins have in a way similar and corresponding on arranging.Therefore, can draw up the pin definitions corresponding tables (as shown in Figure 5) of the chip pin of north bridge chips.
See also Fig. 6 and Fig. 7.Fig. 6 is the synoptic diagram on first plane 24 of the motherboard 22 of computer system 10 of the present invention.Fig. 7 is the synoptic diagram on second plane 26 of the motherboard 22 of computer system 10 of the present invention.Computer system 10 comprises a motherboard 22 in addition, and wherein first slot 12, second slot 14, north bridge chips 16, control circuit 18 and a testing circuit 20 are to be installed on first plane 24 of motherboard 22.And be used for the chip pin of control store in the north bridge chips is to be connected in first slot 12 and second slot 14 via the conducting path on the motherboard 22 28.
For in the process of circuit layout, on motherboard, use minimum perforation and the most suitable cabling, loss minimum when allowing signal on motherboard, advance, therefore the present invention divides into three groups with pin definitions, be respectively data pins definition group, address pins definition group, and order pin definitions group (as shown in Figure 3).Wherein, the signal that pin produced that belongs to same pin definitions group has similarity to a certain degree, therefore can the most suitable mode of cabling exchange.For instance, because MD[0:63] and DM[0:7] belong to same pin definitions group, so its cabling can the most suitable mode exchange.Is MD 32 as the MD 63 of DDR when the SDR, and the DM0 of SDR is MD 37 when DDR.Similarly, A[0:12], BA[0:1], SCAAJ, SRASJ and SWEAJ, on cabling, can exchange.Is A7 as the A3 of DDR when the SDR, and the SCASJ of SDR is SWEAJ when DDR.And CS[0:5] and CKE[0:5] also same.
As Fig. 6 and shown in Figure 7, be that conducting path 28 via first plane 24 that is installed on motherboard 22 is connected in first slot 12 and second slot 14 corresponding to the chip pin of data pins definition group in the north bridge chips 16.And be that conducting path 28 via second plane 26 that is installed on motherboard 22 is connected in first slot 12 and second slot 14 corresponding to the chip pin of address pins definition group and order pin definitions group in the north bridge chips 16.In addition, generally speaking, on the cabling of circuit layout, outer limit three rows' pin cabling can be walked the front at motherboard in the chip, to avoid unnecessary perforation, change layer, to stride Moat etc. and cause the uncertain factor of noise.Because, the signal of dynamic RAM is the high frequency action, therefore the present invention will belong to data pins definition group pin (MD[0:63], DM[0:7], DQS[0:7] etc. 80 pins), all be arranged in first three row, make it can be at the front of motherboard (component side) cabling, and will belong to address pins definition group and order pin definitions group pin (A[0:12], BA[0:1], SCASJ, SRASJ, SWEAJ, CS[0:5], CKE[0:5]) be arranged in back three rows, make its (solder side) cabling overleaf.
Yet, because 80 pin signals are walked the front entirely and can be caused the cabling area too big.Therefore, in the process of implementing, the research and development slip-stick artist can be divided into 8 groups with 80 pin signals.For example, with MD[0:7], DM[0], DQS[0] etc. ten pin signals be depicted as first group (group 0), with MD[8:15], DM[1], DQS[1] etc. ten signals be depicted as second group (group 1), by that analogy.Then, the research and development slip-stick artist can be with the perforation of each group, change hierachy number is made into as many, so that the characteristics of signals of each group is more consistent, that is there is noise to produce equally, situation about being disturbed is also similar, thereby reduces affected degree, and reduces the cabling area.That is to say, data pins is defined group be further divided into eight data pin definitions subgroup, make that the chip pin corresponding to each data pins definition subgroup has similar characteristics of signals in the north bridge chips 16, to reduce affected degree.
Compared to the prior art, computer system 10 of the present invention has 184pin DIMM and two kinds of slots with different pin definitions of 168pin DIMM simultaneously, and the chip pin of its north bridge chips 16 is to correspond respectively to the pin definitions of 184pin DIMM and the pin definitions of 168pin DIMM, therefore can support double Data Dynamic random access memory and Synchronous Dynamic Random Access Memory simultaneously.Therefore, the transitional period, the user need not suffer from the selection and the upgrading of specification in the market that is converted to DDRAM and 184pin DIMM fully from SDRAM and 168pin DIMM.
The above only is preferred embodiment of the present invention, and all variations of being made within the scope of the invention and modification are all within protection scope of the present invention.
Claims (14)
1. the computer system of the dynamic RAM of dynamic RAM that is used for supporting a first kind and one second type, it comprises:
One motherboard comprises one first plane and one second plane;
One first slot is installed on first plane of this motherboard, is used for installing the dynamic RAM of this first kind, and this first slot comprises a plurality of first slot pins, and each first slot pin is corresponding to one first pin definitions;
One second slot is installed on first plane of this motherboard, is used for installing the dynamic RAM of this second type, and this second slot comprises a plurality of second slot pins, and each second slot pin is corresponding to one second pin definitions;
Many conducting paths;
One north bridge chips is installed on first plane of this motherboard, and it comprises a plurality of chip pins, is connected in this first slot and this second slot via this conducting path, and each chip pin is corresponding to one first pin definitions and one second pin definitions; And
One control circuit is installed on first plane of this motherboard and is connected in this north bridge chips, is used for setting the pin definitions of this chip pin;
Wherein, this control circuit is imported this north bridge chips with one first control signal, and the pin definitions of this chip pin can be made as this first pin definitions, makes this north bridge chips to carry out data transmission with the dynamic RAM of this first kind; This control circuit is imported this north bridge chips with one second control signal, and the pin definitions of this chip pin can be made as this second pin definitions, makes this north bridge chips to carry out data transmission with the dynamic RAM of this second type.
2. computer system as claimed in claim 1, wherein the dynamic RAM of this first kind is an a pair of haplotype data dynamic RAM, and the dynamic RAM of this second type is a synchronous dynamic RAM.
3. computer system as claimed in claim 2, wherein this first slot is one to have the double linear memory assembly slot of 184 pins, and this second slot is one to have the double linear memory assembly slot of 168 pins.
4. computer system as claimed in claim 1, wherein pairing first pin definitions of this first slot pin is to belong to a plurality of pin definitions group respectively, and pairing second pin definitions of this second slot pin also belongs to this a plurality of pin definitions group respectively, and pairing first pin definitions of each chip pin and second pin definitions are to belong to same pin definitions group.
5. computer system as claimed in claim 4, wherein this pin definitions group is respectively data pins definition group, address pins definition group, and an order pin definitions group.
6. computer system as claimed in claim 5, be that conducting path via first plane that is installed on this motherboard is connected in this first slot and second slot corresponding to the chip pin of this data pins definition group in this north bridge chips wherein, and be that conducting path via second plane that is installed on this motherboard is connected in this first slot and second slot corresponding to the chip pin of this address pins definition group and this order pin definitions group in this north bridge chips.
7. computer system as claimed in claim 5, wherein this data pins definition group is divided into eight data pin definitions subgroup in addition, and the chip pin corresponding to each data pins definition subgroup in this north bridge chips has similar characteristics of signals.
8. computer system as claimed in claim 1, also comprise a testing circuit, be electrically connected on this control circuit, the dynamic RAM that this testing circuit detects this first kind is installed on this first slot, this testing circuit can transmit one first detection signal to this control circuit, make this control circuit transmit this and first control signal to this north bridge chips, be made as this first pin definitions with pin definitions with this chip pin; When the dynamic RAM that this testing circuit detects this second type is installed on this second slot, this testing circuit can transmit one second detection signal to this control circuit, make this control circuit transmit this and second control signal to this north bridge chips, be made as this second pin definitions with pin definitions with this chip pin.
9. computer system that is used for supporting an a pair of haplotype data dynamic RAM and a synchronous dynamic RAM, it comprises:
One motherboard comprises one first plane and one second plane;
One first slot, be installed on first plane of this motherboard, be used for installing this double Data Dynamic random access memory, this first slot comprises a plurality of first slot pins, each first slot pin is corresponding to one first pin definitions, and this first pin definitions belongs to a plurality of pin definitions group respectively;
One second slot, be installed on first plane of this motherboard, be used for installing this Synchronous Dynamic Random Access Memory, this second slot comprises a plurality of second slot pins, each second slot pin is corresponding to one second pin definitions, and this second pin definitions belongs to this a plurality of pin definitions group respectively;
Many conducting paths;
One north bridge chips, be installed on first plane of this motherboard, it comprises a plurality of chip pins, be connected in this first slot and this second slot via this conducting path, each chip pin is corresponding to one first pin definitions and one second pin definitions, and this first pin definitions and this second pin definitions belong to same pin definitions group; And
One control circuit is installed on first plane of this motherboard and is connected in this north bridge chips, is used for setting the pin definitions of this chip pin;
Wherein, this control circuit is imported this north bridge chips with one first control signal, and the pin definitions of this chip pin can be made as this first pin definitions, makes this north bridge chips to carry out data transmission with this double Data Dynamic random access memory; And when this control circuit was imported this north bridge chips with one second control signal, the pin definitions of this chip pin can be made as this second pin definitions, made this north bridge chips to carry out data transmission with this Synchronous Dynamic Random Access Memory.
10. computer system as claimed in claim 9, wherein this first slot is one to have the double linear memory assembly slot of 1 84 pins, and this second slot is one to have the double linear memory assembly slot of 1 68 pins.
11. computer system as claimed in claim 9, wherein this pin definitions group is respectively data pins definition group, address pins definition group, and an order pin definitions group.
12. computer system as claimed in claim 9, also comprise a testing circuit, be electrically connected on this control circuit, the dynamic RAM that this testing circuit detects this first kind is installed on this first slot, this testing circuit can transmit one first detection signal to this control circuit, make this control circuit transmit this and first control signal to this north bridge chips, be made as this first pin definitions with pin definitions with this chip pin; The dynamic RAM that this testing circuit detects this second type is installed on this second slot, this testing circuit can transmit one second detection signal to this control circuit, make this control circuit transmit this and second control signal to this north bridge chips, be made as this second pin definitions with pin definitions with this chip pin.
13. computer system as claimed in claim 11, be that conducting path via first plane that is installed on this motherboard is connected in this first slot and second slot corresponding to the chip pin of this data pins definition group in this north bridge chips wherein, and be that conducting path via second plane that is installed on this motherboard is connected in this first slot and second slot corresponding to the chip pin of this address pins definition group and this order pin definitions group in this north bridge chips.
14. computer system as claimed in claim 11, wherein this data pins definition group is divided into eight data pin definitions subgroup in addition, and the chip pin corresponding to each data pins definition subgroup in this north bridge chips has similar characteristics of signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001374176A CN1157644C (en) | 2000-12-27 | 2000-12-27 | Computer system backing up different type of DRAMs |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001374176A CN1157644C (en) | 2000-12-27 | 2000-12-27 | Computer system backing up different type of DRAMs |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1361458A CN1361458A (en) | 2002-07-31 |
| CN1157644C true CN1157644C (en) | 2004-07-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001374176A Expired - Fee Related CN1157644C (en) | 2000-12-27 | 2000-12-27 | Computer system backing up different type of DRAMs |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100351827C (en) * | 2004-04-13 | 2007-11-28 | 联发科技股份有限公司 | Pin sharing system |
| CN100346331C (en) * | 2004-11-30 | 2007-10-31 | 英业达股份有限公司 | Chip bridging device for multiple chip socket type circuit board |
| CN101398800B (en) * | 2007-09-27 | 2012-09-19 | 鸿富锦精密工业（深圳）有限公司 | Mainboard with mixed slot architecture |
| CN105843326A (en) * | 2015-01-15 | 2016-08-10 | 华硕电脑股份有限公司 | Computer main board with double-specification memory slots, and computer system |
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2000
- 2000-12-27 CN CNB001374176A patent/CN1157644C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN1361458A (en) | 2002-07-31 |
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Granted publication date: 20040714 Termination date: 20101227 |