CN115966224A

CN115966224A - Multi-die package

Info

Publication number: CN115966224A
Application number: CN202111187000.3A
Authority: CN
Inventors: 钟胜峰
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-10-12
Filing date: 2021-10-12
Publication date: 2023-04-14

Abstract

The application discloses a multi-die package, which comprises a main die, a memory die, a first group of pins and a second group of pins, wherein the main die comprises a memory controller, a first group of contacts, a second group of contacts and a third group of contacts, the memory die is coupled to the first group of contacts and the second group of contacts of the main die, the first group of pins is coupled to the third group of contacts of the main die, and the second group of pins is coupled to the second group of contacts of the main die. In addition, the memory controller accesses the memory die through the first set of contacts and the second set of contacts and accesses the memory chip outside the multi-die package through the second set of contacts and the third set of contacts.

Description

Multi-die package

Technical Field

The present application relates to a multi-die package architecture including Dynamic Random Access Memory (DRAM).

Background

Current semiconductor packaging technology can integrate multiple dies (die) into a single package to reduce the routing and area on a Printed Circuit Board (PCB). For example, the conventional DRAM and the processor are two chips/packages, and therefore, a plurality of traces and contacts are required to be designed on the printed circuit board to connect the two chips, and if the processor and the DRAM are integrated into a single package so that the processor can access the DRAM through the traces and contacts inside the package, the traces and contacts on the printed circuit board can be reduced.

However, if the processor and the DRAM are disposed in a single package, the size of the DRAM can be maintained at an initial design value because the number of dies in the package cannot be increased any more, and thus, the scalability is lacking. In other words, if the designer needs to design the processor and the DRAM for a plurality of different products, and the capacities of the DRAM required by the different products are not exactly the same, the designer needs to design the chip for the plurality of different DRAM capacities, thereby increasing the design and manufacturing costs.

Disclosure of Invention

Therefore, one of the objectives of the present invention is to provide a multi-die package architecture that allows for expansion of the DRAM capacity to solve the problems of the prior art.

In one embodiment of the present invention, a multi-die package is disclosed, which includes a main die, a memory die, a first set of pins, and a second set of pins, wherein the main die includes a memory controller, a first set of contacts, a second set of contacts, and a third set of contacts, the memory die is coupled to the first set of contacts and the second set of contacts of the main die, the first set of pins is coupled to the third set of contacts of the main die, and the second set of pins is coupled to the second set of contacts of the main die. In addition, the memory controller accesses the memory die through the first set of contacts and the second set of contacts and accesses the memory chip outside the multi-die package through the second set of contacts and the third set of contacts.

The features, practical operation and efficacy of the present invention will be described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a diagram illustrating a multi-die package according to an embodiment of the invention.

Fig. 2 is a diagram of a multi-die package and a memory chip according to an embodiment of the invention.

Description of the symbols

100: multi-die package

102: first group of pins of multi-die package

104: second group of pins of multi-die package

110: master crystal grain

112: core circuit

114: memory controller

116_1: first set of contacts of the master die

116_2: second set of contacts of the master die

116 \ u 3: third set of contacts of the master die

120: memory die

122: control circuit

124: memory array

126_1: first set of contacts for memory die

126_2: second set of contacts for memory die

200: memory chip

202: first group of pins of memory chip

204: second group pin of memory chip

210: control circuit

220: memory array

Detailed Description

Embodiments of the present invention are described in more detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be embodied in a wide variety of specific contexts. The examples are given for illustration only and do not limit the scope of the present application.

Fig. 1 is a diagram of a multi-die package 100 according to one embodiment of the invention. As shown in fig. 1, the multi-die package 100 includes a main die 110, a memory die 120, and a plurality of groups of leads (only the first group of leads 102 and the second group of leads 104 are shown in this embodiment), wherein the first group of leads 102 and the second group of leads 104 each include a plurality of leads. In the present embodiment, the main die 110 may be a processor, such as a Central Processing Unit (CPU), and the main die 110 includes a core circuit 112, a memory controller 114, and a plurality of sets of contacts (only the first, second, and third sets of contacts 116_1, 116_2, and 116_3 are shown in this embodiment), wherein each of the first, second, and third sets of contacts 116_1, 116_2, and 116 _3includes a plurality of contacts; in addition, the memory die 120 includes a control circuit 122, a memory array 124, and a plurality of sets of contacts (only the first set of contacts 126_1 and the second set of contacts 126_2 are shown in this embodiment). In addition, in the embodiment, the memory die 120 is a DRAM die, and the memory controller 114 in the master die 110 is a DRAM controller, but the invention is not limited thereto.

In the present embodiment, the first set of contacts 116_1 of the main die 110 are Data contacts used to transfer Data to the memory die 120 through the first set of contacts 126 _1of the memory die 120 and/or to receive Data from the memory die 120, i.e., the first set of contacts 116 _1of the main die 110 and the first set of contacts 126 _1of the memory die 120 are connected by a plurality of connecting lines, wherein the plurality of connecting lines are at least used to transmit a plurality of bi-directional (bi-directional) Data signals (Data, DQ), one or more bi-directional Data Strobe Signals (DQs) …, and so on. The second set of contacts 116 u 2 of the host die 110 are control signal contacts that are used to transmit clock, control and address signals to the second set of contacts 126 u 2 of the memory die 120 for use by the memory die 120, and also to transmit control and address signals to components external to the multi-die package 100 via the second set of pins 104, wherein the clock, control and address signals include read command/write command, write enable (write enable), column address (row address) signals, column address (column address) signals …, and so on. The third set of contacts 116_3 of the main die 110 are data contacts used to transmit data to and/or receive data from components external to the multi-die package 100 via the first set of pins 102, i.e., the first set of contacts 116_1 of the main die 110 and the components external to the multi-die package 100 are connected by a plurality of connections for at least transmitting a plurality of bi-directional data signals (DQ), one or more bi-directional data strobe Signals (DQs) …, and so on. In the present embodiment, the path for the memory controller 110 to access components outside the multi-die package 100 through the third set of contacts 116 \ u 3 and the first set of pins 102 does not pass through the memory die 120.

In general operation of the multi-die package 100, the memory controller 114 may receive a request from the core circuitry 112 and send a portion of the data signals, data strobe signals, command signals, and clock signals through the first set of contacts 116_1 and the second set of contacts 116_2 to access the memory die 120. Specifically, the memory controller 114 may include associated circuitry, such as address decoders, processing circuitry, write/read buffers, control logic, and arbiters, for generating data signals, data strobe signals, command signals, and clock signals to the memory die 120. In addition, in the memory die 120, the control circuit 122 may include a read/write controller, a row decoder and a column decoder, and the control circuit 124 receives data signals, data strobe signals, command signals and clock signals from the memory controller from the first set of contacts 126_1 and the second set of contacts 126_2 to access the memory array 124.

In the above embodiments, since the capacity of the memory die 120 in the multi-die package 100 is fixed, when the multi-die package 100 needs to be applied to electronic products with high memory capacity and performance requirements, the capacity of the memory die 120 is not enough to meet the requirements. Therefore, the multi-die package 100 of the present embodiment can be externally connected to another memory chip to improve the memory capacity and performance. Specifically, referring to fig. 2, it includes a multi-die package 100 and a memory chip 200, wherein the memory chip 200 includes a control circuit 210, a memory array 220 and a plurality of groups of pins (only the related first group of pins 202 and second group of pins 204 are shown in this embodiment). In addition, in the present embodiment, the memory chip 200 is a DRAM chip, the multi-die package 100 and the memory chip 200 are disposed on a printed circuit board, and the first group of leads 102 and the second group of leads 104 of the multi-die package 100 are connected to the first group of leads 202 and the second group of leads 204 of the memory chip 200 through connecting wires on the printed circuit board.

In operation of the multi-die package 100 and the memory chip 200 shown in fig. 2, the memory controller 114 may receive a request from the core circuitry 112 and send a plurality of command signals to the memory die 120 and the memory chip 200 via the second set of contacts 116 \ u 2 to access at least one of the memory die 120 and the memory chip 200. Specifically, when the applications executed by the core circuitry 112 require lower memory access speed and performance (e.g., lower bandwidth), the memory controller 114 may receive requests from the core circuitry 112 and send a portion of the data signals, data strobe signals, command signals and clock signals through the first set of contacts 116_1 and the second set of contacts 116_2 to access the memory die 120 to read data from the memory array 124 or write data to the memory array 124; at this time, since the memory controller 114 does not need to access the memory chip 200, the control circuit 210 in the memory chip 200 may ignore the command signals received from the second set of pins 204 and/or the memory chip 200 may enter the power saving mode. In another embodiment, when the application executed by the core circuit 112 only needs to use the lower memory access speed and performance, the memory controller 114 may also receive a request from the core circuit 112 and send a portion of the data signal, the data strobe signal, the command signals and the clock signal through the second set of contacts 116 _2and the third set of contacts 116 _3to access the memory chip 200 to read data from the memory array 220 or write data to the memory array 220; at this time, since the memory controller 114 does not need to access the memory die 120, the control circuit 122 in the memory die 120 may ignore the command signals received from the second set of contacts 126 and/or the memory die 120 may enter the power saving mode.

When applications executed by the core circuitry 112 require higher memory access speeds and performance (e.g., higher bandwidth) to be used, the memory controller 114 may receive requests from the core circuitry 112 and send multiple command signals through the second set of contacts 116 v 2 to access the memory die 120 and the memory chip 200 simultaneously. Specifically, the command signals sent by the memory controller 114 via the second set of contacts 116 v 2 may include a write command and the address of the memory array 124 and the address of the memory array 220, while the memory controller 114 sends the first set of data to the memory die 120 via the first set of contacts 116 v 1 to be written to the corresponding address of the memory array 124, and simultaneously, the memory controller 114 sends the second set of data to the memory chip 200 via the third set of contacts 116 v 3 to be written to the corresponding address of the memory array 220. In addition, the command signals sent by the memory controller 114 through the second set of connection points 116 v 2 may include a read command, an address of the memory array 124 and an address of the memory array 220, and the control circuit 122 in the memory die 120 reads the first set of data from the memory array 124 according to the received addresses and transmits the first set of data to the memory controller 114 through the first set of connection points 126 v 1; simultaneously, the control circuit 210 in the memory chip 200 reads a second set of data from the memory array 220 according to the received address and transmits the second set of data to the memory controller 114 via the first set of pins 202.

In one embodiment, the bandwidth of the first set of contacts 116_1 used to transmit or receive the first set of data in the master grain 110 may be the same as the bandwidth of the third set of contacts 116_3 used to transmit or receive the second set of data, e.g., the bandwidth of the first and second sets of data may be 16 bits; the multi-die package 100 may utilize 16-bit bandwidth or 32-bit bandwidth depending on whether it is linked to the memory chip 200 or whether it is necessary to access both the memory die 120 and the memory array 220. In another example, the first set of data and the second set of data may have a bandwidth of 8 bits, and the multi-die package 100 may determine whether to use 8 bits of bandwidth or 16 bits of bandwidth based on whether it is linked to the memory chip 200 or whether it is necessary to access both the memory die 120 and the memory array 220.

Briefly summarizing the present invention, in the multi-die package 100 of the present invention, through the design of the relevant contacts/pins, the memory chip 200 can be externally connected to achieve the effect of expanding the memory capacity and speed, and the multi-die package 100 can also be applied to various electronic products with different memory bandwidth requirements, so as to reduce the design cost.

The above description is only a preferred embodiment of the present invention, and all equivalent variations and modifications made in the above disclosure of the present invention should fall within the protection scope of the present invention.

Claims

1. A multi-die package, the multi-die package comprising:

a master die comprising a memory controller, a first set of contacts, a second set of contacts, and a third set of contacts, wherein the first set of contacts, the second set of contacts, and the third set of contacts each comprise a plurality of contacts;

a memory die coupled to the first set of contacts and the second set of contacts of the host die;

a first set of pins coupled to the third set of contacts of the master die; and

a second set of pins coupled to the second set of contacts of the host die;

wherein the memory controller accesses the memory die through the first set of contacts and the second set of contacts and accesses a memory chip located outside the multi-die package through the second set of contacts and the third set of contacts.

2. The multi-die package of claim 1, wherein the memory controller transmits command signals and address signals to the memory die and the memory chip through the second set of contacts; and the memory controller writes data into the memory crystal grain or reads data from the memory crystal grain through the first set of connecting points, or the memory controller writes data into the memory chip or reads data from the memory chip through the third set of connecting points.

3. The multi-die package of claim 2, wherein the memory controller determines to access one of the memory die and the memory chip or both the memory die and the memory chip based on a bandwidth required by an application executed by a core circuit in a host die.

4. The multi-die package of claim 3, wherein the address signals transmitted by the memory controller to the memory die and the memory chip comprise an address of a first memory array within the memory die and an address of a second memory array within the memory chip when the memory controller needs to access the memory die and the memory chip simultaneously; and if the command signals transmitted by the memory controller to the memory die and the memory chip include a write command, the memory controller transmits a first set of data to the memory die via the first set of pins to write the first set of data into the first memory array, and transmits a second set of data to the memory die via the third set of pins to write the second set of data into the second memory array.

5. The multi-die package of claim 3, wherein the address signals transmitted by the memory controller to the memory die and the memory chip comprise an address of a first memory array within the memory die and an address of a second memory array within the memory chip when the memory controller needs to access the memory die and the memory chip simultaneously; and if the command signal transmitted by the memory controller to the memory grain and the memory chip comprises a read command, the memory controller receives a first set of data from the memory grain through the first set of pins and receives a second set of data from the memory chip through the third set of pins.

6. The multi-die package of claim 2, wherein a bandwidth of data transmitted/received by the first set of contacts is the same as a bandwidth of data transmitted/received by the third set of contacts.

7. The multi-die package of claim 6, wherein the bandwidth of the data transmitted/received by the first set of contacts and the bandwidth of the data transmitted/received by the third set of contacts are both 16 bits or 8 bits.

8. The multi-die package of claim 2, wherein the memory controller writes data to or reads data from the memory chip through the third set of contacts and the first set of pins, and wherein a path through which the memory controller accesses the memory chip through the third set of contacts and the first set of pins does not pass through the memory die.

9. The multi-die package of claim 2, wherein the memory controller transmits the command signals and the address signals to the memory die through the second set of contacts, and the memory controller transmits the command signals and the address signals to the memory chip through the second set of contacts and the second set of pins.

10. The multi-die package of claim 1, wherein the Memory die is a Dynamic Random Access Memory (DRAM) die, the Memory chip is a DRAM chip, and the Memory controller is a DRAM controller.