CN115757229A - Interface circuit, memory chip and data access method of memory - Google Patents
Interface circuit, memory chip and data access method of memory Download PDFInfo
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- CN115757229A CN115757229A CN202211417243.6A CN202211417243A CN115757229A CN 115757229 A CN115757229 A CN 115757229A CN 202211417243 A CN202211417243 A CN 202211417243A CN 115757229 A CN115757229 A CN 115757229A
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Abstract
The application discloses an interface circuit, a memory chip and a data access method of a memory. The interface circuit comprises a control circuit, a standard interface and a protocol conversion circuit, wherein the control circuit is connected with a storage array of the memory, and a data end, an address end and an instruction end of each storage unit of the storage array are respectively connected with different ports of the control circuit; the standard interface is used for accessing external data and outputting read data; the protocol conversion circuit is respectively connected with the control circuit and the standard interface, the protocol conversion circuit performs format conversion on external data to obtain write data conforming to the interface protocol of the storage array, and the control circuit writes the write data after protocol conversion into the storage unit; and the control circuit acquires the read data from the storage unit, and the protocol conversion circuit is used for carrying out format conversion on the read data so as to enable the standard interface to output the read data which accords with the standard interface protocol. The interface circuit provided by the application can improve the access efficiency of the memory.
Description
Technical Field
The present application relates to the field of data transmission technologies, and in particular, to an interface circuit, a memory chip, and a data access method for a memory.
Background
A conventional Dynamic Random Access Memory (DRAM) accesses an internal Memory array through a JEDEC standard DRAM interface, and the internal Memory array of the DRAM can be generally divided into a plurality of Memory cells, but due to the limitations of interface bit width and interface speed, all the Memory cells multiplex an interface bus in a time-sharing manner, and a system can only Access one Memory cell of the DRAM at a time, so that the Access efficiency is low, and the performance of the DRAM cannot be fully exerted.
In the non-standard memory array chip in the market, the control line, the address line and the data line interface of each memory unit are mutually independent, so that the data bandwidth is greatly improved, but the non-standard memory array chip is incompatible with a standard protocol and has poor user integration flexibility.
Disclosure of Invention
The technical problem mainly solved by the application is to provide an interface circuit, a memory chip and a data access method of a memory, which can improve the access efficiency of the memory.
In order to solve the technical problem, the application adopts a technical scheme that: providing an interface circuit, wherein the interface circuit comprises a control circuit, a standard interface and a protocol conversion circuit, the control circuit is connected with a storage array of a memory, and a data end, an address end and an instruction end of each storage unit of the storage array are respectively connected with different ports of the control circuit; the standard interface is used for accessing external data and outputting read data; the protocol conversion circuit is respectively connected with the control circuit and the standard interface, the protocol conversion circuit performs format conversion on external data to obtain write data conforming to the interface protocol of the storage array, and the control circuit writes the write data after the protocol conversion into the storage unit; and the control circuit acquires the read data from the storage unit, and the protocol conversion circuit is used for carrying out format conversion on the read data so as to enable the standard interface to output the read data which accords with the standard interface protocol.
In order to solve the technical problem, the other technical scheme adopted by the application is as follows: the memory chip comprises the interface circuit and the memory array, wherein the interface circuit is used for accessing external data and performing read-write operation on the memory array based on the external data.
In order to solve the above technical problem, the present application adopts another technical solution: the interface circuit of the memory comprises a control circuit, a standard interface and a protocol conversion circuit, wherein the control circuit is respectively connected with the conversion circuit and a storage array of the memory, and a data end, an address end and an instruction end of each storage unit of the storage array are respectively connected with different ports of the control circuit; the data access method comprises the following steps: the standard interface is accessed to external data, and the protocol conversion circuit performs format conversion on the external data to obtain write data; the control circuit writes into the memory cell based on the write data; and the control circuit acquires the read data from the storage unit and feeds the read data back to the protocol conversion circuit, and the protocol conversion circuit is used for carrying out format conversion on the read data so as to enable the standard interface to output the read data which conforms to the standard interface protocol.
The beneficial technical effects are as follows: the interface circuit provided by the application is provided with the protocol conversion circuit, the standard interface and the control circuit, and is respectively connected with different ports of the control circuit through the data end, the address end and the instruction end of each storage unit of the storage array of the memory, and the control circuit can be used for writing data which is obtained by format conversion of external data accessed by the standard interface through the protocol conversion circuit and accords with the interface protocol of the storage array into the storage unit. Or the control circuit acquires the read data from the storage unit and transmits the read data to the protocol conversion circuit, and after the protocol conversion circuit performs format conversion on the read data, the standard interface can output the read data meeting the standard interface protocol, so that the memory is compatible with the standard protocol, and the flexibility of user integration is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic block diagram of an embodiment of an interface circuit provided herein;
FIG. 2 is a schematic diagram of an implementation of the standard interface and protocol conversion circuit of the embodiment of FIG. 1;
FIG. 3 is a schematic block diagram of an embodiment of an interface circuit and memory interconnect according to the present application;
FIG. 4 is a schematic diagram of an embodiment of the control circuit of FIG. 2;
FIG. 5 is a schematic block diagram of one embodiment of the NOC circuit of the embodiment of FIG. 4;
FIG. 6 is a schematic diagram of another embodiment of the control circuit of FIG. 2;
FIG. 7 is a schematic structural diagram of an embodiment of a memory chip of the present application;
FIG. 8 is a flow chart illustrating an embodiment of a method for accessing data of a memory provided herein;
fig. 9 is a schematic flowchart of a data access method of a memory according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work according to the embodiments of the present application are within the scope of the present application.
In the description of the embodiments of the present application, it should be noted that the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. Specific meanings of the above terms in the embodiments of the present application can be understood in specific cases by those of ordinary skill in the art.
In the embodiments of the present application, unless otherwise explicitly specified or limited, a first feature "on" or "under" a second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "above," and "over" a second feature may be directly on or obliquely above the second feature, or simply mean that the first feature is at a higher level than the second feature. A first feature "under," "beneath," and "under" a second feature may be directly under or obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of an interface circuit provided in the present application. As shown in fig. 1, the interface circuit 100 includes a protocol conversion circuit 110, a standard interface 130, and a control circuit 120, the control circuit 120 is respectively connected to the protocol conversion circuit 110 and a memory array (not shown) of the memory, and a data terminal, an address terminal, and a command terminal of each memory cell (not shown) of the memory array are respectively connected to different ports of the control circuit 120. The standard interface 130 is used for accessing external data and outputting read data. The protocol conversion circuit 110 is connected to the control circuit 120 and the standard interface 130, respectively, and is configured to perform format conversion on external data to obtain write data meeting an interface protocol of the storage array, and the control circuit 120 writes the write data after the protocol conversion into a storage unit; or the control circuit 120 obtains the read data from the memory unit, and the protocol conversion circuit 110 is used for performing format conversion on the read data so that the standard interface 130 outputs the read data conforming to the protocol of the standard interface 130. Wherein the memory may be a random access memory.
The interface circuit 100 provided by the present application is provided with the protocol conversion circuit 110, the standard interface 130, and the control circuit 120, and is connected to different ports of the control circuit 120 respectively with a data end, an address end, and an instruction end of each storage unit of the storage array of the memory, and the control circuit 120 may be configured to perform format conversion on external data accessed by the standard interface 130 by the protocol conversion circuit 110 to obtain write data conforming to an interface protocol of the storage array, and write the write data into the storage unit. Or the control circuit 120 obtains the read data from the memory cell and transmits the read data to the protocol conversion circuit 110, and after the protocol conversion circuit 110 performs format conversion on the read data, the standard interface 130 can output the read data conforming to the protocol of the standard interface 130, so that the memory is compatible with the standard protocol, and the flexibility of user integration is improved.
Alternatively, referring to fig. 2 to fig. 3, fig. 2 is a schematic structural diagram of an implementation of the standard interface and protocol conversion circuit 110 in the embodiment of fig. 1; FIG. 3 is a block diagram of an embodiment of an interface circuit and memory interconnect according to the present invention. As illustrated, the standard interface 130 may include either or both of a bus interface 131, a DDR interface 132. The protocol conversion circuit 110 is configured with a standard protocol conversion circuit 110 corresponding to the standard interface 130. When the standard interface 130 includes the bus interface 131, the protocol conversion circuit 110 includes a bus protocol conversion circuit 111, and the bus protocol conversion circuit 111 is connected to the control circuit 120 and the bus interface 131 respectively. The bus protocol conversion circuit 111 is configured to perform format conversion on external data to obtain write data, a write address, and a write command that conform to an interface protocol of the memory array. The control circuit 120 writes write data to the memory cell corresponding to the write address based on the write instruction. The bus protocol conversion circuit 111 is further configured to convert external data to obtain a read address and a read instruction that conform to the interface protocol of the memory array, the control circuit 120 reads read data from a memory cell corresponding to the read address based on the read instruction and feeds the read data back to the bus protocol conversion circuit 111, and the bus protocol conversion circuit 111 performs format conversion on the read data to enable the bus interface 131 to output the read data that conform to the protocol of the bus interface 131. The protocol of the Bus protocol conversion circuit 111 may be a mainstream SOC system Bus protocol such as an Advanced Microcontroller Bus Architecture (AMBA) protocol, a wishbone, and a core connection.
When the standard interface 130 includes the DDR interface 132, the protocol conversion circuit 110 further includes a DDR protocol conversion circuit 112. The DDR protocol conversion circuit 112 is connected to the control circuit 120 and the DDR interface 132, respectively, and is configured to perform format conversion on external data to obtain write data, a write address, and a write instruction that conform to an interface protocol of the memory array, where the control circuit 120 writes the write data into a memory cell corresponding to the write address based on the write instruction. The DDR protocol conversion circuit 112 further converts the external data to obtain a read address and a read command that conform to the interface protocol of the memory array, the control circuit 120 reads the read data from the memory cell corresponding to the read address based on the read command and feeds the read data back to the DDR protocol conversion circuit 112, and the DDR protocol conversion circuit 112 performs format conversion on the read data, so that the DDR interface 132 outputs the read data that conform to the DDR interface 132 protocol. The DDR protocol conversion circuit 112 may be a standard protocol such as DDR4, PDDR2, LPDDR3, LPDDR4, LPDDR5, GDDR3, GDDR5, GDDR6, etc.
The different types of standard interfaces 130 are independently connected to the protocol conversion circuit 110 of the corresponding setting type, and the protocol conversion circuit 110 is independent from the control circuit 120 when connected, that is, the multiplexing of the bus interface 131, the DDR interface 132 and the controller is realized.
The standard interface 130 of this embodiment includes a bus interface 131 and/or a DDR interface 132, the protocol conversion circuit 110 is provided with a bus protocol conversion circuit 111 and/or a DDR protocol conversion circuit 112 corresponding to the standard interface 130, and format conversion is performed on the external data by using different protocol conversion circuits 110, so that the control circuit 120 reads data stored in the memory array based on the external data, or stores the data in the memory array. That is, under the action of the protocol conversion circuit 110 corresponding to the standard interface 130, external data accessed by different types of standard interfaces 130 can be read and written to the memory array through the control circuit 120, so as to satisfy the data read and write of different standard interfaces 130 in the memory array, thereby improving the flexibility of user integration; further, the bus interface 131 is connected to the control circuit 120 through the bus protocol conversion circuit 111, and/or the DDR interface 132 is connected to the control circuit 120 through the DDR protocol conversion circuit 112, so that multiplexing of the bus interface 131, the DDR interface 132 and the control circuit 120 is realized.
The interface circuit 100 may be connected to the memory through a Printed Circuit Board (PCB) technology or a Multi-Chip Module (MCM) technology. Preferably, the interface circuit 100 and the memory are interconnected by a Hybrid Bonding (Hybrid Bonding) technology and a Through Silicon Via (TSV) technology in a three-dimensional integrated technology (3 DIC) process. The 3DIC process is a well established technology for multi-chip stack interconnection where fusion Bonding or direct wafer Bonding can be permanently connected through a dielectric layer on each wafer surface, and Hybrid Bonding technology extends the fusion Bonding with embedded metal pads in the Bonding interface, allowing chip-to-chip connections. The TSV technology realizes vertical electrical interconnection of the through-silicon vias by filling conductive substances such as copper, tungsten, polysilicon, and the like. The through silicon via technology can reduce the interconnection length, reduce signal delay, reduce capacitance/inductance, realize low power consumption and high-speed communication between chips, increase broadband and realize miniaturization of device integration through vertical interconnection. In this embodiment, the data terminals, the address terminals, and the instruction terminals of all the memory units of the memory array chip may be interconnected with different ports of the control circuit 120 in the interface circuit 100 in the same direction by Hybrid Bonding technology and TSV technology, and then the connected memory array chip and the control circuit 120 may be interconnected in the opposite direction by Hybrid Bonding technology. As shown in fig. 3, the interface circuit 100 and the memory are interconnected by a 3DIC process, and the connecting lines between the two are stacked on the middle layer of the 3 DIC.
The interface circuit 100 and the memory array of the memory are interconnected through a Hybrid Bonding technology and a TSV technology, and a connecting line between the interface circuit 100 and the memory array of the memory is stacked on an interlayer of the 3DIC, so that the bit width of a memory interface is not limited by packaging and system hardware any more, and therefore, signals of memory unit interfaces of the memory can be directly output, the interface circuit 100 can directly control all memory units to read and write at the same time, and the access efficiency of the memory is improved.
Optionally, referring to fig. 4 to 5, fig. 4 is a schematic structural diagram of an embodiment of the control circuit in the embodiment of fig. 2; fig. 5 is a schematic diagram of an embodiment of the NOC circuit of the embodiment of fig. 4. As shown, the control circuit 120 includes a memory controller 121 and a NOC circuit 122, the NOC circuit 122 includes a source node (not shown) and a plurality of path nodes (not shown), the memory controller 121 is connected to the bus protocol conversion circuit 111, the DDR protocol conversion circuit 112 and the source node, respectively, the source node and the plurality of path nodes are connected to the memory cells in a one-to-one correspondence, and a data terminal, an address terminal and a command terminal of each memory cell of the memory array are connected to different ports of the corresponding source node or path node, respectively. The memory controller 121 writes the write data to the source node of the NOC circuit 122 based on the write command and the write address, and the source node and the path node route the write data to the memory cell corresponding to the write address. The memory controller 121 also aggregates read data of the memory cells corresponding to the read address through the path node and the source node based on the read command and the read address. The source node is a path node selected from the path nodes as a source node, and the unselected path nodes continue to be path nodes.
In the present embodiment, the control circuit 120 is provided with a storage controller 121 and an NOC circuit 122, where the NOC circuit 122 includes a source node and multiple path nodes, the storage controller 121 is connected to the bus protocol conversion circuit 111, the DDR protocol conversion circuit 112 and the source node, the source node and the multiple path nodes are connected to the storage units in a one-to-one correspondence manner, and a data end, an address end and an instruction end of each storage unit of the storage array are connected to different ports of the corresponding source node or path node, respectively, and in this way, the storage controller 121 writes write data into the source node based on the write instruction and the write address converted by the formats of the bus protocol conversion circuit 111 and the DDR protocol conversion circuit 112, and routes the write data into the storage unit corresponding to the write address through the source node and the path node; or the memory controller 121 converges the read data of the memory cell corresponding to the read address through the path node and the source node based on the read command and the read address, so that the corresponding data can be read through different paths, and the access speed of reading and writing the data in the memory array is improved; further, the bus interface 131 and the DDR interface 132 are accessed through the bus protocol conversion circuit 111 and the DDR protocol conversion circuit 112, respectively, and both read and write data from and to the memory array through the memory controller 121, so that multiplexing of the bus interface 131, the DDR interface 132, and the memory controller 121 is realized.
Optionally, referring to fig. 6, fig. 6 is a schematic structural diagram of another embodiment of the control circuit in the embodiment of fig. 2. As shown in fig. 6, the control circuit 120 includes a bus memory controller 121b and a NOC circuit 122. The NOC circuit 122 includes a source node and a plurality of path nodes. The bus memory controller 121b is connected to source nodes of the bus protocol conversion circuit 111 and the NOC circuit 122, respectively, and a plurality of path nodes of the source nodes and the NOC circuit 122 are connected to the memory cells in a one-to-one correspondence. The data end, the address end and the instruction end of each storage unit of the storage array are respectively connected with different ports of the corresponding source node or path node. The bus memory controller 121b writes the write data into the source node based on the write command and the write address, and the source node and the path node route the write data to the memory cell corresponding to the write address. The bus memory controller 121b aggregates the read data of the memory cell corresponding to the read address through the path node and the source node based on the read command and the read address. And/or
The control circuit 120 includes a DDR memory controller 121a, the DDR memory controller 121a is connected to the DDR protocol conversion circuit 112 and the memory array, and the data terminal, the address terminal, and the command terminal of each memory cell of the memory array are connected to different ports of the DDR memory controller 121 a. Wherein the DDR memory controller 121a writes the write data into the memory cell corresponding to the write address based on the write command and the write address. The DDR memory controller 121a feeds back the read data of the memory cell corresponding to the read address to the DDR protocol conversion circuit 112 based on the read command and the read address.
Optionally, the source node and the plurality of path nodes of the NOC circuit 122 are each provided with a DMA circuit (not shown), where the DMA circuit of the source node is connected to the bus memory controller 121b and/or the DDR memory controller 121a, that is, the DMA circuit of the source node is connected to the memory controller 121, and the data terminal, the address terminal, and the instruction terminal of the memory unit are respectively connected to different ports of the corresponding DMA circuit. The DMA circuit is used for realizing data transfer of the corresponding storage unit.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of a memory chip provided in the present application. As shown in fig. 7, the memory chip 50 includes the interface circuit 100 and the memory array 500 in the above embodiment, and the interface circuit 100 is used to access external data and perform read and write operations on the memory array 500 based on the external data.
The interface circuit 100 accesses external data, which may be write data, write addresses, and write commands, or read addresses and read commands. When the external data is write data, a write address, and a write command, the interface circuit 100 performs a write operation on the memory array 500; when the external data is a read address and a read command, the interface circuit 100 performs a read operation on the memory array 500.
Alternatively, the interface circuit 100 and the memory array 500 may be integrally provided by Printed Circuit Board (PCB) technology, multi-Chip Module (MCM) technology, or three-dimensional integrated technology (3 DIC).
The present application further provides a data access method of a memory, wherein the interface circuit 100 of the memory includes a protocol conversion circuit 110, a control circuit 120 and a standard interface 130, the control circuit 120 is respectively connected to the conversion circuit and a storage array of the memory, and a data terminal, an address terminal and a command terminal of each storage unit of the storage array are respectively connected to different ports of the control circuit 120.
Referring to fig. 8, fig. 8 is a schematic flowchart illustrating a data access method of the memory according to an embodiment of the present disclosure. As shown in fig. 8, the data access method includes the steps of:
step S600: the standard interface 130 accesses external data and outputs read data, and the protocol conversion circuit 110 performs format conversion on the external data to obtain write data.
The standard interface 130 accesses external data, and the format of the external data is converted by the protocol conversion circuit 110 to obtain write data that can be recognized by the control circuit 120.
Step S700: the control circuit 120 writes to the memory cell based on the write data; and the control circuit 120 obtains the read data from the memory cell and feeds the read data back to the protocol conversion circuit 110, and the protocol conversion circuit 110 is configured to perform format conversion on the read data, so that the standard interface 130 outputs the read data conforming to the protocol of the standard interface 130.
The control circuit 120 writes write data into the memory cell when receiving the write data. And the control circuit 120 obtains the read data from the memory cell and feeds the read data back to the protocol conversion circuit 110, and the protocol conversion circuit 110 is configured to perform format conversion on the read data, so that the standard interface 130 outputs the read data conforming to the protocol of the standard interface 130.
Optionally, the standard interface 130 includes a bus interface 131, and the protocol conversion circuit 110 includes a bus protocol conversion circuit 111 respectively connected to the control circuit 120 and the bus interface 131. In step S600, the following steps may be further included:
s610: the bus interface 131 accesses external data, and the bus protocol conversion circuit 111 performs format conversion on the external data to obtain write data, a write address and a write instruction which conform to an interface protocol of the memory array; and the bus protocol conversion circuit 111 performs format conversion on the external data to obtain a read address and a read instruction which conform to the interface protocol of the memory array chip.
The bus interface 131 accesses external data, and performs format conversion on the external data through the bus protocol conversion circuit 111 to obtain write data, a write address, and a write command that conform to an interface protocol of the memory array. Or the bus protocol conversion circuit 111 performs format conversion on the external data to obtain a read address and a read instruction which conform to the interface protocol of the memory array chip.
Based on step S610, in step S700, the following steps may be further included:
s710: the control circuit 120 writes write data into the memory cell corresponding to the write address based on the write instruction; and the control circuit 120 reads the read data from the memory cell corresponding to the read address based on the read command and feeds the read data back to the bus protocol conversion circuit 111, and the bus protocol conversion circuit 111 performs format conversion on the read data so that the bus interface 131 outputs the read data conforming to the bus interface 131 protocol.
The control circuit 120 writes the received write data to the memory cell corresponding to the write address based on the write instruction. Or the control circuit 120 reads the data in the memory cell corresponding to the read address based on the read command and feeds the data back to the bus protocol conversion circuit 111, and the bus protocol conversion circuit 111 performs format conversion on the read data, so that the bus interface 131 outputs the read data conforming to the protocol of the bus interface 131.
And/or
The standard interface 130 includes a DDR interface 132, the protocol conversion circuit 110 includes a DDR protocol conversion circuit 112 connected to the control circuit 120 and the DDR interface 132, respectively, and the standard interface 130 accesses external data. Step S600 may further include the steps of:
s620: the DDR interface 132 accesses external data, and the DDR protocol conversion circuit 112 is configured to perform format conversion on the external data to obtain write data, a write address, and a write instruction that conform to an interface protocol of the memory array.
The DDR interface 132 accesses external data, and performs format conversion on the external data by using the DDR protocol conversion circuit 112 to obtain write data, a write address, and a write command that conform to the interface protocol of the memory array.
Based on step S620, step S700 may further include the steps of:
s720: the control circuit 120 writes write data into the memory cell corresponding to the write address based on the write instruction; and the control circuit 120 reads the read data from the memory cell corresponding to the read address based on the read command, and feeds back the read data to the DDR protocol conversion circuit 112, and the DDR protocol conversion circuit 112 performs format conversion on the read data, so that the DDR interface 132 outputs the read data conforming to the DDR interface 132 protocol.
The control circuit 120 writes the received write data to the memory cell corresponding to the write address based on the write instruction. Or the control circuit 120 reads the read data from the memory cell corresponding to the read address based on the read command and feeds the read data back to the DDR protocol conversion circuit 112, and the DDR protocol conversion circuit 112 performs format conversion on the read data, so that the DDR interface 132 outputs the read data conforming to the DDR interface 132 protocol.
Referring to fig. 9, fig. 9 is a schematic flowchart of another embodiment of a data access method of a memory according to the present application, as shown in fig. 9, an interface circuit 100 receives external data and sends the external data to a protocol conversion circuit 110, the conversion circuit performs format conversion on the external data, and when write data, a write address and a write command are obtained, a control circuit 120 writes the write data into a memory cell corresponding to the write address based on the write command; when the read address and the read command are obtained after the conversion, the control circuit 120 reads the read data from the memory cell corresponding to the read address based on the read command, and feeds back the read data to the protocol conversion circuit 110.
In the description of the present application, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, mechanism, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, mechanisms, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing mechanisms, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps in the process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device (such as a personal computer, server, network device, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions). For the purposes of this description, a "computer-storage medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer storage medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. An interface circuit, comprising:
the control circuit is connected with a storage array of the memory, and a data end, an address end and an instruction end of each storage unit of the storage array are respectively connected with different ports of the control circuit;
the standard interface is used for accessing external data and outputting read data;
the protocol conversion circuit is respectively connected with the control circuit and the standard interface, the protocol conversion circuit performs format conversion on the external data to obtain write data meeting the interface protocol of the storage array, and the control circuit writes the write data after protocol conversion into the storage unit; and the control circuit acquires read data from the storage unit, and the protocol conversion circuit is used for carrying out format conversion on the read data so as to enable the standard interface to output the read data which conforms to a standard interface protocol.
2. The interface circuit of claim 1, wherein the standard interface comprises a bus interface, and wherein the protocol conversion circuit comprises:
the bus protocol conversion circuit is respectively connected with the control circuit and the bus interface and is used for carrying out format conversion on the external data to obtain write data, a write address and a write command which conform to the interface protocol of the storage array, and the control circuit writes the write data into the storage unit corresponding to the write address based on the write command; the control circuit reads read data from the memory unit corresponding to the read address based on the read instruction and feeds back the read data to the bus protocol conversion circuit, and the bus protocol conversion circuit performs format conversion on the read data so that the bus interface outputs the read data conforming to a bus interface protocol; and/or
The standard interface comprises a DDR interface, and the protocol conversion circuit comprises:
the DDR protocol conversion circuit is respectively connected with the control circuit and the DDR interface and is used for carrying out format conversion on the external data to obtain write data, a write address and a write command which accord with the interface protocol of the storage array, and the control circuit writes the write data into the storage unit corresponding to the write address based on the write command; and converting the external data to obtain a read address and a read instruction which accord with an interface protocol of the memory array, reading read data from the memory unit corresponding to the read address based on the read instruction by the control circuit, and feeding back the read data to the DDR protocol conversion circuit, wherein the DDR protocol conversion circuit performs format conversion on the read data to enable the DDR interface to output the read data which accord with the DDR interface protocol.
3. The interface circuit of claim 2, wherein the control circuit comprises: the storage controller is respectively connected with the bus protocol conversion circuit, the DDR protocol conversion circuit and the source node, the source node and the plurality of path nodes are correspondingly connected with the storage units one by one, and a data end, an address end and a command end of each storage unit of the storage array are respectively connected with different ports of the corresponding source node or path node;
wherein the memory controller writes the write data into the source node based on the write command and the write address, and the source node and the path node route the write data to the memory cell corresponding to the write address;
and the storage controller converges the read data of the storage unit corresponding to the read address through the path node and the source node based on the read instruction and the read address.
4. The interface circuit of claim 2, wherein the control circuit comprises:
the NOC circuit comprises a source node and a plurality of path nodes, the bus storage controller is respectively connected with the bus protocol conversion circuit and the source node, the source node and the plurality of path nodes are connected with the storage units in a one-to-one correspondence manner, and a data end, an address end and a command end of each storage unit of the storage array are respectively connected with different ports of the corresponding source node or the path node; wherein:
the bus storage controller writes the write data into the source node based on the write command and the write address, and the source node and the path node route the write data to the storage unit corresponding to the write address;
the bus memory controller converges read data of the memory unit corresponding to the read address through the path node and the source node based on the read instruction and the read address; and/or
The control circuit includes:
the DDR memory controller is respectively connected with the DDR protocol conversion circuit and the memory array, and a data end, an address end and an instruction end of each memory unit of the memory array are respectively connected with different ports of the DDR memory controller; wherein:
the DDR memory controller writes the write data into the memory cell corresponding to the write address based on the write command and the write address;
and the DDR memory controller feeds back the read data of the memory unit corresponding to the read address to the DDR protocol conversion circuit based on the read instruction and the read address.
5. The interface circuit according to claim 3 or 4, wherein the source node and the plurality of path nodes are each provided with a DMA circuit, the DMA circuit of the source node is connected to the memory controller, and a data terminal, an address terminal and an instruction terminal of the memory unit are respectively connected to different ports of the corresponding DMA circuit;
the DMA circuit is used for realizing data transportation of the corresponding storage unit.
6. A memory chip comprising the interface circuit of claims 1-5 and a memory array, wherein the interface circuit is configured to access the external data and perform read and write operations on the memory array based on the external data.
7. The memory chip of claim 6, wherein the memory array and the interface circuit are interconnected by Hybrid Bonding technology and Through Silicon Via technology.
8. The memory chip of claim 7, wherein the interface circuit and the memory array are integrally disposed through a PCB, MCM, or 3 DIC.
9. The data access method of the memorizer is characterized in that an interface circuit of the memorizer comprises a control circuit, a standard interface and a protocol conversion circuit, wherein the control circuit is respectively connected with the conversion circuit and a storage array of the memorizer, and a data end, an address end and an instruction end of each storage unit of the storage array are respectively connected with different ports of the control circuit; the data access method comprises the following steps:
the standard interface is accessed to external data, and the protocol conversion circuit performs format conversion on the external data to obtain write data;
the control circuit writes to the memory cell based on the write data; and the control circuit acquires read data from the storage unit and feeds the read data back to the protocol conversion circuit, and the protocol conversion circuit is used for carrying out format conversion on the read data so as to enable the standard interface to output the read data which accords with a standard interface protocol.
10. The data access method of claim 9, wherein the standard interface includes a bus interface, the protocol conversion circuit includes a bus protocol conversion circuit respectively connected to the control circuit and the bus interface, the standard interface accesses external data, and the protocol conversion circuit performs format conversion on the external data to obtain write data, and further comprising:
the bus interface is accessed to the external data, and the bus protocol conversion circuit performs format conversion on the external data to obtain write data, a write address and a write instruction which accord with the interface protocol of the storage array; the bus protocol conversion circuit carries out format conversion on the external data to obtain a read address and a read instruction which accord with an interface protocol of the storage array chip;
the control circuit writes to the memory cell based on the write data; and the control circuit acquires the read data from the storage unit and feeds the read data back to the protocol conversion circuit, the protocol conversion circuit is used for carrying out format conversion on the read data so as to enable the standard interface to output the read data which conforms to the standard interface protocol, and the control circuit also comprises:
the control circuit writes the write data into the memory cell corresponding to the write address based on the write instruction; the control circuit reads read data from the memory cell corresponding to the read address based on the read instruction and feeds the read data back to the bus protocol conversion circuit, and the bus protocol conversion circuit performs format conversion on the read data so that the bus interface outputs the read data conforming to a bus interface protocol; and/or
The standard interface includes a DDR interface, the protocol conversion circuit includes a DDR protocol conversion circuit connected to the control circuit and the DDR interface, the standard interface accesses external data, and the protocol conversion circuit performs format conversion on the external data to obtain write data, and the method further includes:
the DDR interface is accessed to the external data, and the DDR protocol conversion circuit is used for carrying out format conversion on the external data to obtain write data, a write address and a write command which accord with an interface protocol of the storage array;
the control circuit writes to the memory cell based on the write data; and the control circuit acquires the read data from the storage unit and feeds the read data back to the protocol conversion circuit, the protocol conversion circuit is used for carrying out format conversion on the read data so as to enable the standard interface to output the read data which conforms to the standard interface protocol, and the control circuit also comprises:
the control circuit writes the write data into the memory cell corresponding to the write address based on the write instruction; and the control circuit reads read data from the storage unit corresponding to the read address based on the read instruction and feeds the read data back to the DDR protocol conversion circuit, and the DDR protocol conversion circuit performs format conversion on the read data so that the DDR interface outputs the read data conforming to the DDR interface protocol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211417243.6A CN115757229A (en) | 2022-11-11 | 2022-11-11 | Interface circuit, memory chip and data access method of memory |
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| CN202211417243.6A CN115757229A (en) | 2022-11-11 | 2022-11-11 | Interface circuit, memory chip and data access method of memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116662240A (en) * | 2023-05-12 | 2023-08-29 | 珠海妙存科技有限公司 | Protocol conversion circuit and method, chip, testing device and storage medium |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116662240A (en) * | 2023-05-12 | 2023-08-29 | 珠海妙存科技有限公司 | Protocol conversion circuit and method, chip, testing device and storage medium |
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