CN213934865U - System access device based on three-dimensional chip, memory and electronic equipment - Google Patents

System access device based on three-dimensional chip, memory and electronic equipment Download PDF

Info

Publication number
CN213934865U
CN213934865U CN202022579295.6U CN202022579295U CN213934865U CN 213934865 U CN213934865 U CN 213934865U CN 202022579295 U CN202022579295 U CN 202022579295U CN 213934865 U CN213934865 U CN 213934865U
Authority
CN
China
Prior art keywords
memory
data
serial
system access
access device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202022579295.6U
Other languages
Chinese (zh)
Inventor
王嵩
张晨良子
曹媛媛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Unilc Semiconductors Co Ltd
Original Assignee
Xian Unilc Semiconductors Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Unilc Semiconductors Co Ltd filed Critical Xian Unilc Semiconductors Co Ltd
Priority to CN202022579295.6U priority Critical patent/CN213934865U/en
Application granted granted Critical
Publication of CN213934865U publication Critical patent/CN213934865U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Dram (AREA)

Abstract

The embodiment of the application provides a system access device, a memory and an electronic device based on a three-dimensional chip, and solves the problems of high manufacturing cost, high difficulty and poor stability caused by the silicon through hole technology used for realizing high bandwidth. The system access device may include: the device comprises a storage unit side port, a memory controller, a serial protocol conversion circuit and a serial/parallel port, wherein the storage unit port is used for being connected with storage units in a wire bonding mode so that each storage unit can independently carry out data communication with a communication device; the memory controller is connected with the side port of the memory unit and is used for processing and accessing control of memory data; the serial protocol conversion circuit is connected with the memory controller and is used for carrying out serial protocol conversion processing on the data processed by the memory controller; the serial/parallel port includes: at least one serial data port or at least two parallel data ports, the serial/parallel ports being connected to the serial protocol conversion circuit for accessing the system.

Description

System access device based on three-dimensional chip, memory and electronic equipment
Technical Field
The embodiment of the utility model provides a relate to memory technical field, specifically speaking relates to a system access device and relevant equipment based on three-dimensional chip.
Background
With the application of ASIC chips in the fields of AI artificial intelligence, large data centers, automatic driving, etc., a large amount of data needs to be processed, the demand for computing power increases correspondingly, and the demand for bandwidth of the device also increases more and more. Compared with the prior art development of the video memory, the position of a bottleneck is reached, and the space for providing larger video memory width by frequency increase is not too large.
At present, due to the 3DS (3-Dimensional Stack) technology, three-Dimensional chips are gradually becoming widespread, so that a three-Dimensional chip can be understood as a technology for stacking common two-Dimensional chips, and a common way is to communicate each memory cell based on a TSV (Through-Silicon-Vi) technology, so that each memory layer can be stacked up Through the TSV technology, and metal layers are equally spaced between layers. The most typical examples are HBM (High Bandwidth Memory) and HMC (Hybrid Memory Cube). However, from the manufacturing point of view, it is very difficult to realize a 3D stacked structure with several tens of layers, the manufacturing difficulty is high, and the problem of high operation risk and poor stability due to the immature technology exists. Furthermore, since both HBM and HMC use silicon interposers, the cost is high and the output is very limited.
SUMMERY OF THE UTILITY MODEL
In the summary section a series of concepts in a simplified form is introduced, which will be described in further detail in the detailed description section. The summary of the embodiments of the present application is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to identify key features or essential features of the claimed subject matter.
The embodiment of the application provides a system access device, a memory and an electronic device, and solves the problems of high manufacturing cost, high difficulty, high operation risk and poor stability caused by the fact that a TSV (through silicon via) technology is used for realizing high bandwidth.
To at least partially solve the above problem, in a first aspect, an embodiment of the present application provides a system access apparatus, which may include:
a memory unit side port, a memory controller, a serial protocol conversion circuit and a serial/parallel port,
wherein,
the memory cell port is used for being connected with a memory cell in a wire bonding mode so that each memory cell can independently carry out data communication with the communication device;
the memory controller is connected with the side port of the storage unit and is used for processing and controlling access of the stored data;
the serial protocol conversion circuit is connected with the memory controller and is used for performing serial protocol conversion processing on the data processed by the memory controller;
the serial/parallel port includes: at least one serial data port or at least two parallel data ports, the serial/parallel port is connected with the serial protocol conversion circuit and used for accessing a system.
In a first possible implementation manner of the first aspect, the system access device may further include:
and the deserializing circuit is connected with the serial protocol conversion circuit and is used for deserializing the data after the serial protocol conversion processing.
In a second possible implementation form of the first aspect, the at least two parallel data ports are parallel port arrays.
In a third possible implementation manner of the first aspect, the system access device may further include:
and the multi-path data bridge is connected with the memory controller and is used for bridging the data signals transmitted by the plurality of storage units.
In a fourth possible implementation manner of the first aspect, the system access device may further include:
and the phase-locked loop is connected with the memory controller and is used for synchronizing the data signals transmitted by the plurality of storage units.
In a fifth possible implementation manner of the first aspect, the system access device may further include:
and the self-testing circuit is connected with the memory controller and is used for self-testing the device and the functional conditions of all functional units in the device.
In a second aspect, an embodiment of the present application provides a memory, which may include:
two or more than three memory units and the system access device, wherein,
each of the two or more than three memory units is connected with the system access device in a wire bonding mode, so that each memory unit can independently perform data communication with the system access device.
In a first possible implementation manner of the second aspect, the two or more than three memory cells may be stacked to form a memory cell group, and the memory includes one or more than two memory cell groups arranged in a tiled manner.
In a second possible implementation form of the second aspect, the memory unit is a double rate synchronous dynamic random access memory unit.
In a third aspect, an embodiment of the present application provides an electronic device, which may include:
a processor and the memory described above, wherein,
and the processor is connected with the memory and used for reading data from the memory through the system access device or writing data into the memory through the system access device.
Compared with the prior art, the embodiment of the utility model provides an in the system access device that provides include following beneficial effect at least:
the embodiment of the utility model provides a system access device, include: the memory unit side port, the memory controller, the serial protocol conversion circuit and the serial/parallel port make full use of the wire bonding technology, so that each memory unit can independently carry out data communication with the communication device. And the data signals independently transmitted by the plurality of storage units are processed into high-speed serial signals by combining a serial protocol conversion circuit, so that the number of channels required by the data signals transmitted in the communication device is greatly reduced, the problem of crosstalk possibly generated when multipath signals are transmitted in the communication device is solved, the implementation cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
Accordingly, the embodiment of the present invention provides a memory and an electronic device, which also have the above technical effects.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts based on these drawings:
fig. 1 is a schematic structural block diagram of a system access device according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of another system access device according to an embodiment of the present invention;
fig. 3 is a schematic block diagram of another system access device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a memory according to an embodiment of the present invention;
fig. 5 is a schematic structural block diagram of a memory according to an embodiment of the present invention;
fig. 6 is a schematic structural block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention is further described in detail below with reference to the drawings and examples so that those skilled in the art can implement the invention with reference to the description.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
In addition, it should be noted that the terms "disposed" and "connected" are to be construed broadly unless otherwise explicitly stated or limited. For example, the connection can be fixed connection or detachable connection; can be directly connected or indirectly connected through an intermediate medium; either integrally connected or communicating between the interior of the two components. Or the two elements may perform signal transmission and data communication. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Currently, to achieve higher bandwidth, 3DS technology is often used by stacking storage layers. For example, the HBM chip and the HMC chip of each memory cell are connected based on the TSV technology. The HBM chip is formed by stacking a plurality of DDR double-rate synchronous dynamic random access memory unit chips and a PLD (Programmable Logic Device), then packaging the chips together with a GPU (graphics processing unit), and realizing connection between the chips by utilizing the connection of silicon through holes and micro-bumps, thereby realizing a high-capacity and high-bit-width DDR combined array. And the HMC chip is formed by stacking a plurality of DRAM layers on a basic logic layer, and the optimal combination of logic and DRAM processes is realized in a heterogeneous package. The DRAM layer handles only data, while the logical layer handles all control functions in the HMC.
However, it is very difficult to realize a stacked structure of several tens of layers, which is difficult to realize, and the technology is not mature, and there are problems of high operational risk, poor stability, etc. Furthermore, since both HBM and HMC use silicon interposers, the cost is high and the output is very limited. In addition, the heat dissipation performance is also seriously affected due to the fact that a large number of DRAM stacks and GPUs are packaged together.
In view of the above problems, embodiments of the present application provide a system access device, a memory, and an electronic device, which solve the problems of high manufacturing cost, high difficulty, high operational risk, and poor stability caused by using the tsv technology for high bandwidth.
Fig. 1 is a schematic block diagram of a system access device according to an embodiment of the present invention, and as shown in fig. 1, the system access device 100 may include: memory unit side port 110, memory controller 120, serial protocol conversion circuit 130, and serial/parallel port 140. The system access device 100 may be used to establish an interconnection between a plurality of memory units and enable the memory units to communicate data with the processor. Accordingly, the memory unit side 110 is a side to which a connection with a memory unit is required, and the serial/parallel Port 140 is a side to which a connection with a processor is required, and the Port may be represented by a PHY (Port Physical Layer). The memory cells, which may also be referred to as memory grains or memory cells or Die semiconductor dies, are used for storing instructions or data information.
Wherein,
the memory cell side port 110 may be used for wire bonding connection with memory cells so that each of the memory cells can independently perform data communication with the communication device 100;
it should be noted that, by way of example, the wire bonding technology is a process technology for connecting a semiconductor die with an I/O lead of a microelectronic package or a metal wiring Pad on a substrate by using a metal filament, which can achieve fast interconnection between chips. The method can comprise the following steps: thermal compression bonding, ultrasonic bonding, thermosonic bonding, and the like. The lead bonding technology can enable the metal of the bonding area to generate plastic deformation, so that the lead is in close contact with a bare chip or a welded surface of a microelectronic, the range of interatomic attraction is reached, the interatomic diffusion between interfaces is caused to form a welding point, and further, the transmission of data signals is realized.
In some examples, the memory cell-side port 110 may enable data communication with each memory cell independently of the communication device 100 after wire-bonding connection with the plurality of memory cells. The problems of high cost and heat dissipation caused by the fact that the TSV is used for communicating all the storage units in data communication and the problem of signal crosstalk easily caused by the fact that the TSV communicates all the storage units are solved.
In addition, since there are a lot of DRAM (Dynamic Random Access Memory) stacks and GPU (Graphics Processing Unit) packages, the heat dissipation of the DRAM stacks and the GPU stacks can be seriously affected. And because the wire bonding technology is utilized, each storage unit can independently carry out data communication with a communication device, and compared with a storage unit stacking scheme which needs to adopt a silicon intermediate layer, the heat dissipation performance is better.
The memory controller 120 is connected to the memory unit side port 110, and is configured to process and access control data; it should be noted that the memory controller 120 is an important component for controlling the memory inside the module with computing function and exchanging data between the memory and the processor through the memory controller. Can be used for the access control of addresses, the conversion of protocols and the integration of data.
In some examples, the memory unit may be integrated by the memory controller 120 by converting the internal signal through the memory unit side port 110, and the memory controller 120 converts the protocol and the instruction into a standard protocol for subsequent data communication.
The serial protocol conversion circuit 130 is connected to the memory controller 120, and configured to perform serial protocol conversion processing on the data processed by the memory controller 120;
in some examples, the serial protocol conversion circuit 130 may be a SERializer, and may serialize data into high-speed serial data for subsequent data communication, so as to greatly reduce the number of channels required for transmitting data signals in the communication device and avoid the crosstalk problem that may occur when multiple signals are transmitted in the communication device.
The serial/parallel port 140 includes: at least one serial data port or at least two parallel data ports, and the serial/parallel port 140 is connected to the serial protocol conversion circuit 130 and can be used to access a system.
In some examples, data processed by the serial protocol conversion circuit 130 may communicate with the processor through the serial/parallel port 140 described above.
The embodiment of the utility model provides an above-mentioned system access device 100 through make full use of wire bonding technique for every memory cell can independently carry out data communication with communication device. And the data signals independently transmitted by the plurality of storage units are processed into high-speed serial signals by combining a serial protocol conversion circuit, so that the number of channels required by the data signals transmitted in the communication device is greatly reduced, the problem of crosstalk possibly generated when multipath signals are transmitted in the communication device is solved, the implementation cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
According to some embodiments, the system access device may further include: and the deserializing circuit can be connected with the serial protocol conversion circuit and is used for deserializing the data after the serial protocol conversion processing. The serial protocol conversion circuit after adding the DESerializer circuit desrializer may be referred to as a SERDES serial-to-parallel conversion circuit.
Illustratively, the memory unit side port uses a serial protocol conversion circuit to serialize low-speed parallel data to be transmitted into high-speed serial data, then transmits the serial data to a data receiving end, and then uses a deserializing circuit to deserialize the received high-speed serial data into multiple paths of low-speed parallel data at the other end to complete the whole transmission process of the data in the communication device. And the deserialized multi-path low-speed parallel data has the advantages of lower hardware implementation cost and better reliability in the subsequent transmission process.
In order to satisfy the data communication between the multi-path low-speed parallel data and the processor, the at least two parallel data ports may be parallel port arrays.
According to some embodiments, the system access device may further include:
and the multi-path data bridge can be connected with the memory controller and is used for bridging data signals transmitted by the plurality of storage units so as to carry out data serialization processing subsequently.
According to some embodiments, the system access device may further include:
and the phase-locked loop is connected with the memory controller and is used for synchronizing the data signals transmitted by the plurality of storage units. The phase-locked loop can be used for uniformly integrating clock signals, so that the aim of synchronizing internal signals is fulfilled, and the memory controller can correctly access data information.
According to some embodiments, the system access device may further include:
and the self-testing circuit is connected with the memory controller and is used for self-testing the device and the functional conditions of all functional units in the device. The self-test circuit can be used for providing a self-test function of the communication device and ensuring the reliability of the communication device.
A series of processes of reading data stored in the memory unit by the processor through the memory unit side port DRAM PHY of the system access device, converting the protocol and the instruction into a standard protocol by the memory controller, sending the read data to the multi-way data bridge, sending the data to the serial/parallel port SERDES PHY of the system access device by the multi-way data bridge through the serial protocol conversion circuit, and writing data into the memory unit by the processor through the serial/parallel port SERDES PHY of the system access device can be described in detail through a specific usage scenario shown in fig. 2 and fig. 3 below.
Fig. 2 is a schematic block diagram of another system access device according to an embodiment of the present invention, and as shown in fig. 2, the system access device may include: memory unit side port DRAM PHY, memory controller, phase locked loop, multi-way data bridge, serial protocol conversion circuit, and two serial/parallel ports SERDES PHY. The input end of the DRAM PHY is connected to the storage unit to obtain the instruction or data information transmitted by the storage unit, and the output end SERDES PHY is connected to the processor to transmit the instruction or data information of the storage unit to the processor through the communication device.
Specifically, referring to fig. 2, the instructions or data information transmitted and transmitted by the plurality of memory units may be converted into internal signals of the system access device through the memory unit side port DRAM PHY of the system access device, and integrated by the memory controller, and the memory controller converts the protocol and the instructions into a standard protocol and then bridges the standard protocol through the multi-path data bridge. The phase-locked loop is used for integrating and controlling the clock pulse signal of the internal signal of the system access device uniformly, so that the aim of synchronizing the internal signal is achieved, and the memory can access data correctly. The self-test circuit may be a built-in self-test circuit for providing a test function for the communication device itself, for example, the self-test circuit may detect the function condition of the internal interface, the memory controller, and other components, so as to ensure the reliability of the communication device or the storage unit communicating with the communication device. In the example shown in fig. 2, the self-test circuit uses the JTAG test protocol to detect the functions of the communication apparatus itself. The data processed by the multi-path data bridge is processed by the serial protocol conversion circuit to obtain high-speed serial data, and as shown in fig. 2, the serial communication protocol circuit can be converted again and then interacts with the processor through the two serial data ports SERDES PHY of the system access device.
More specifically, taking LPDDR4 storage units as an example, a single LPDDR4 storage unit has a capacity of 1GB and a bit width of 16 bits, 4 LPDDR4 storage units can be stacked together into a group and tiled into 2 groups, which have a total of 8 LPDDR4 storage units and a total of 8 LPDDR4 storage units, wherein the total bandwidth is frequency x bit width/8 4266x16x8/8 is 68GBps, and the total capacity of 8 LPDDR4 storage units in 2 groups is 8GB and the total bandwidth is 68 GBps. The 8 LPDDR4 storage units are connected to the system access device by wire bonding, and each LPDDR4 storage unit is capable of independently performing data communication with the communication device. The data of 8 LPDDR4 memory cells are integrated by the DRAM PHY and the memory controller and then bridged to the multi-channel data bridge, and then converted into high-speed serial data by the serial protocol conversion circuit and transmitted to the 2 serial data ports SERDES PHY, so as to finally realize data interaction between the memory cells and the processor. It should be noted that, because the serial protocol conversion circuit usually has a certain loss when performing protocol conversion on data, the data bit width can be 8 bits for transmission on each serial data port SERDES PHY, and the transmission rate is 40 Gbps.
Fig. 3 is a schematic block diagram of another system access device according to an embodiment of the present invention, and as shown in fig. 3, the system access device may include: the device comprises a storage unit side port DRAM PHY, a memory controller, a phase-locked loop, a multi-path data bridge, a serial-parallel conversion circuit and a low-speed interface PHY array serving as a parallel data port. The input end of the DRAM PHY is connected with the storage unit to obtain the instruction or data information sent by the storage unit, and the output end of the low-speed interface PHY array is connected with the processor and used for sending the instruction or data stored by the storage unit to the processor through the communication device.
Specifically, referring to fig. 3, the instructions or data information transmitted and transmitted by the plurality of memory units may be converted into internal signals of the system access device through the memory unit side port DRAM PHY of the system access device, and integrated by the memory controller, and the memory controller converts the protocol and the instructions into a standard protocol and then bridges the standard protocol through the multi-path data bridge. The phase-locked loop is used for integrating and controlling the clock pulse signal of the internal signal of the system access device uniformly, so that the aim of synchronizing the internal signal is achieved, and the memory can access data correctly. The self-test circuit may be a built-in self-test circuit, and may be configured to provide a test function for the communication device itself, for example, to detect a function condition of an internal interface, a memory controller, and other components, so as to ensure reliability of the communication device or a storage unit communicating with the communication device. In the example shown in fig. 3, the self-test circuit uses the JTAG test protocol to detect the function of the communication apparatus itself. The data processed by the multi-path data bridge is converted by a serial-parallel conversion circuit, the serial-parallel conversion circuit comprises a deserializing circuit besides a serial protocol conversion circuit, and the deserializing circuit can be connected with the serial protocol conversion circuit and is used for deserializing the data processed by the serial protocol conversion. The serial protocol conversion circuit after adding the DESerializer circuit desrializer may be referred to as a SERDES serial-to-parallel conversion circuit. The specific process of data signal transmission is to serialize low-speed parallel data transmitted from a plurality of memory cells to be transmitted into high-speed serial data, then transmit the serial data to the receiving end of the deserializing circuit, deserialize the received high-speed serial data into multi-path low-speed parallel data by the deserializing circuit, and transmit the multi-path low-speed parallel data to the processor through the low-speed interface PHY array serving as the parallel data port, so that the whole transmission process is completed. Correspondingly, the processor can write data into the memory unit through the low-speed interface PHY array of the system access device.
In some examples, based on the system access apparatus shown in fig. 3, a single LPDDR4 storage unit has a capacity of 1GB and a bit width of 16 bits, and 4 LPDDR4 storage units are stacked together into one group and tiled into 2 groups, resulting in 8 storage units with a bit width of 128 bits, a total bandwidth of 68GBps, and a total capacity of 8 GB. The 8 LPDDR4 storage units are connected to the system access device by wire bonding, and each LPDDR4 storage unit is capable of independently performing data communication with the communication device. The data of 8 LPDDR4 storage units are integrated by a storage unit side port DRAM PHY and a memory controller and then are bridged to a multi-path data bridge, then low-speed parallel data to be transmitted by the storage units are serialized into high-speed serial data by a serial-parallel conversion circuit, then the serial data are transmitted to a receiving end of a deserializing circuit, then the received high-speed serial data are deserialized into multi-path low-speed parallel data by the deserializing circuit, and the multi-path low-speed parallel data are transmitted to a processor by the low-speed interface PHY array serving as a parallel data port. The bit width of the transmission data on the port is 1024 bits, and the transmission rate is 533 Mbps.
Based on above-mentioned system access device, the embodiment of the utility model provides a still provide a memory, can include:
two or more than three memory units and the system access device, wherein,
each of the two or more than three memory cells is connected with the system access device by a wire bonding mode, so that each memory cell can independently perform data communication with the system access device.
Correspondingly, the embodiment of the utility model provides an above-mentioned memory through make full use of wire bonding technique for every memory cell can independently carry out data communication with the communication device in the memory. And the data signals independently transmitted by the plurality of storage units are processed into high-speed serial signals by combining a serial protocol conversion circuit, so that the number of channels required by the data signals transmitted in the communication device is greatly reduced, the problem of crosstalk possibly generated when multipath signals are transmitted in the communication device is solved, the implementation cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
In some examples, the two or more memory cells may be stacked to form a memory cell group, and the memory includes one or more memory cell groups laid out in a tile. Further, the bandwidth of the memory is further improved, and the fast interconnection between the chips is realized.
In some examples, the memory unit may be a double data rate sdram unit, such as a double data rate sdram compliant with JEDEC solid state technology association standard, and may be any one of JEDEC DDR2, JEDEC DDR3, JEDEC DDR4, JEDEC DDR5, JEDEC GDDR6, JEDEC LPDDR3, JEDEC LPDDR4, and JEDEC LPDDR 5.
The system access device according to the embodiment of the present invention is described in detail above with reference to fig. 1 to 3, and the memory according to the embodiment of the present invention is described in detail below with reference to fig. 4 and 5.
Fig. 4 is a schematic structural diagram of a memory according to an embodiment of the present invention, as shown in fig. 4, the memory includes a system access device 100 and 8 memory units 420, for example, a single memory unit has a capacity of 1GB and a bit width of 16 bits, 4 memory units are stacked together to form a memory unit group, and 2 memory unit groups are tiled on both sides of the system access device 100, and then 8 memory units are shared by 2 memory unit groups, which have a bit width of 128 bits in total, a total bandwidth of 68GBps, and a total capacity of 8 GB.
In one example, after the 8 storage units are respectively connected with the system access device through the wire bonding technology, each storage unit can independently perform data communication with the communication device. The data of 8 memory units are integrated by a memory unit side port DRAM PHY and a memory controller and then bridged to a plurality of data bridges, then low-speed parallel data to be transmitted by the memory units are serialized into high-speed serial data by a serial-parallel conversion circuit, then the serial data are transmitted to a receiving end of a deserializing circuit, then the received high-speed serial data are deserialized into a plurality of paths of low-speed parallel data by the deserializing circuit, and the multi-path low-speed parallel data are transmitted to a processor through the low-speed interface PHY array serving as a parallel data port. The bit width of the transmission data on the port is 1024 bits, and the transmission rate is 533 Mbps.
In another example, after the 8 LPDDR4 storage units are respectively connected to the system access device by wire bonding, each LPDDR4 storage unit can independently perform data communication with the communication device. The data of 8 LPDDR4 memory cells are integrated by the DRAM PHY and the memory controller and then bridged to the multi-channel data bridge, and then converted into high-speed serial data by the serial protocol conversion circuit and transmitted to the 2 serial data ports SERDES PHY, so as to finally realize data interaction between the memory cells and the processor. A data bit width of 8 bits may be transmitted on each serial data port SERDES PHY at a transmission rate of 40 Gbps.
To further expand the above memory, the embodiment of the present invention further provides a memory 500, as shown in fig. 5, including a system access device 100 and 4 memory cell groups 510. For example, a single LPDDR4 memory cell has a capacity of 1GB and a bit width of 16 bits, and 4 memory cells are stacked together into one group and tiled into 4 groups of memory cell groups, for 16 memory cells. Taking LPDDR4 as an example, memory 500 may be expanded to 256 bits wide, with a total bandwidth of 128GBps and a total capacity of 16 GB.
An electronic device according to an embodiment of the present invention will be described in detail below with reference to fig. 6. Fig. 6 is a schematic structural block diagram of an electronic device according to an embodiment of the present invention.
As shown in fig. 6, the electronic device 600 may include:
a processor 610 and the memory 500 described above, wherein,
the processor 610 is connected to the memory 500, and is configured to read data from the memory 500 through the system access device 100 or write data into the memory 500 through the system access device 100.
Correspondingly, the embodiment of the utility model provides an above-mentioned electronic equipment through make full use of lead bonding technique for every memory cell can independently carry out data communication with communication device in the electronic equipment. And the data signals independently transmitted by the plurality of storage units are processed into high-speed serial signals by combining a serial protocol conversion circuit, so that the number of channels required by the data signals transmitted in the communication device is greatly reduced, the problem of crosstalk possibly generated when multipath signals are transmitted in the communication device is solved, the implementation cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
While the embodiments of the invention have been disclosed above, it is not limited to the applications listed in the description and the embodiments, which are fully applicable in all kinds of fields of application suitable for this invention, and further modifications may be readily made by those skilled in the art, and the invention is therefore not limited to the specific details shown and described herein without departing from the general concept defined by the claims and their equivalents.

Claims (10)

1. A three-dimensional chip based system access device, comprising:
a memory unit side port, a memory controller, a serial protocol conversion circuit and a serial/parallel port,
wherein,
the memory cell port is used for being in wire bonding connection with the memory cells so as to enable each memory cell to independently carry out data communication with the communication device;
the memory controller is connected with the side port of the storage unit and is used for processing and controlling access of the stored data;
the serial protocol conversion circuit is connected with the memory controller and is used for performing serial protocol conversion processing on the data processed by the memory controller;
the serial/parallel port includes: at least one serial data port or at least two parallel data ports, the serial/parallel port is connected with the serial protocol conversion circuit and used for accessing a system.
2. The apparatus of claim 1, further comprising:
and the deserializing circuit is connected with the serial protocol conversion circuit and is used for deserializing the data after the serial protocol conversion processing.
3. The apparatus of claim 2, wherein the at least two parallel data ports are parallel port arrays.
4. The apparatus of claim 1, further comprising:
and the multi-channel data bridge is respectively connected with the memory controller and the serial protocol conversion circuit and is used for bridging the data signals transmitted by the plurality of storage units.
5. The apparatus of claim 1, further comprising:
and the phase-locked loop is connected with the memory controller and is used for synchronizing the data signals transmitted by the plurality of storage units.
6. The apparatus of claim 1, further comprising:
and the self-testing circuit is connected with the memory controller and is used for self-testing the device and the functional conditions of all functional units in the device.
7. A memory, comprising:
two or more storage units and the system access device according to any one of claims 1 to 6,
each of the two or more than three memory units is connected with the system access device in a wire bonding mode, so that each memory unit can independently perform data communication with the system access device.
8. The memory according to claim 7, wherein the two or more than three memory cells are stacked to form a memory cell group, and the memory comprises one or more than two memory cell groups arranged in a tiled manner.
9. The memory of claim 7, wherein the memory cells are double rate synchronous dynamic random access memory cells.
10. An electronic device, comprising: a processor and the memory of any one of claims 7-9,
and the processor is connected with the memory and used for reading data from the memory through the system access device or writing data into the memory through the system access device.
CN202022579295.6U 2020-11-10 2020-11-10 System access device based on three-dimensional chip, memory and electronic equipment Active CN213934865U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202022579295.6U CN213934865U (en) 2020-11-10 2020-11-10 System access device based on three-dimensional chip, memory and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202022579295.6U CN213934865U (en) 2020-11-10 2020-11-10 System access device based on three-dimensional chip, memory and electronic equipment

Publications (1)

Publication Number Publication Date
CN213934865U true CN213934865U (en) 2021-08-10

Family

ID=77167199

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202022579295.6U Active CN213934865U (en) 2020-11-10 2020-11-10 System access device based on three-dimensional chip, memory and electronic equipment

Country Status (1)

Country Link
CN (1) CN213934865U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112328517A (en) * 2020-11-10 2021-02-05 西安紫光国芯半导体有限公司 Memory data communication device and method based on three-dimensional chip and related equipment
CN114038490A (en) * 2021-10-14 2022-02-11 西安紫光国芯半导体有限公司 Three-dimensional heterogeneous integration-based consistency link memory chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112328517A (en) * 2020-11-10 2021-02-05 西安紫光国芯半导体有限公司 Memory data communication device and method based on three-dimensional chip and related equipment
CN112328517B (en) * 2020-11-10 2024-04-02 西安紫光国芯半导体有限公司 Memory data communication device and method based on three-dimensional chip and related equipment
CN114038490A (en) * 2021-10-14 2022-02-11 西安紫光国芯半导体有限公司 Three-dimensional heterogeneous integration-based consistency link memory chip
CN114038490B (en) * 2021-10-14 2023-07-04 西安紫光国芯半导体有限公司 Consistency link memory chip based on three-dimensional heterogeneous integration

Similar Documents

Publication Publication Date Title
US9182925B2 (en) Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer
US11031049B2 (en) Flexible memory system with a controller and a stack of memory
CN213934865U (en) System access device based on three-dimensional chip, memory and electronic equipment
CN110033798B (en) Integrated circuit chip
CN102024489B (en) Semiconductor memory device and multilayered chip semiconductor device
US8971108B2 (en) Semiconductor memory device and method for driving the same
CN112328517B (en) Memory data communication device and method based on three-dimensional chip and related equipment
KR20200065762A (en) Memory system
JP5650984B2 (en) Semiconductor device
CN214176036U (en) Three-dimensional stacked memory chip module
CN114036086B (en) Three-dimensional heterogeneous integration-based serial interface memory chip
CN116737617B (en) Access controller
US11216393B2 (en) Storage device and method for manufacturing the same
CN115757229A (en) Interface circuit, memory chip and data access method of memory
US11416425B2 (en) Memory
CN114823615A (en) Memory chip and 3D memory chip
CN218299383U (en) Memory chip module and 3D memory chip
CN218299384U (en) 3D memory chip module
TWI814179B (en) A multi-core chip, an integrated circuit device, a board card, and a process method thereof
WO2021146912A1 (en) Communication interface and encapsulation structure
CN114823616A (en) Three-dimensional stacked memory chip
TW202334958A (en) Memory circuit, data transmission circuit, and memory
JP2009020924A (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant