CN218299384U - 3D memory chip module - Google Patents

Abstract

The embodiment of the application provides a 3D storage chip module. The 3D memory chip module comprises a memory part and a control part which are stacked mutually, and the memory part and the control part are connected in a hybrid bonding mode. The 3D memory chip provided by the embodiment of the invention comprises a memory part and a control part which are mutually stacked, wherein the memory part is connected with the control part in a hybrid bonding mode. As a driving interface circuit or a module (PHY) is not needed between two chips of the storage part and the control part of the same storage chip, the chip density of the storage chip stacking can be very high, and the mixed bonding parasitic parameters (parasitic resistance value and parasitic capacitance value) of the storage part chip and the control part chip forming the storage chip are very small, so that the RC delay is small, the data transmission speed is not lost, and the high-bandwidth data transmission of the storage chip can be realized.

Description

3D memory chip module

Technical Field

The embodiment of the invention relates to the technical field of memories, in particular to a 3D memory chip module.

Background

Currently, memory chips, especially DRAM memory chips, are largely classified into planar DRAMs and three-Dimensional stacked DRAMs formed using 3DS (3-Dimensional Stack) technology.

For a planar DRAM, the memory array portion (Bank 1-Bank4,) and the control circuit may be on one chip, see the example of the planar DRAM shown in fig. 1. The memory array part usually includes memory cells, and the control circuit usually includes decoding and decoding circuits, data writing circuits, data reading circuits and other functional circuits.

Due to the manufacturing process limitation of the planar DRAM, especially the manufacturing process limitation of the storage capacitor, the storage chip has larger parasitic resistance and capacitance, which affects the processing performance of the functional circuit in the storage chip, so the planar DRAM has the defects of low speed, high power consumption and poor capability of processing data in parallel.

In the three-dimensional stacked DRAM, it is more common to communicate with each memory portion based on a TSV (Through-Silicon-Via) technique, and each memory layer may be stacked by the TSV technique, with metal layers being equally spaced between layers. The most typical examples are HBM (High Bandwidth Memory) and HMC (Hybrid Memory Cube). However, the HBM and the HMC both use silicon interposers, which results in high cost, and also has the problems of large RC delay, large power consumption, and poor heat dissipation.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. The summary of the embodiments of the present application is not intended to define key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

The embodiment of the application provides a 3D memory chip module, and solves the problems of high manufacturing cost, large RC delay, large power consumption and poor heat dissipation caused by large parasitic resistance and capacitance of the existing memory chip and the use of a through silicon via technology.

To at least partially solve the above problem, in a first aspect, an embodiment of the present application provides a 3D memory chip module, which may include:

the memory chip comprises a memory part and a control part which are stacked mutually, wherein the memory part is connected with the control part in a hybrid bonding mode, the hybrid bonding mode is that a connecting pad of the memory part is connected with a connecting pad of the control part through a metal conductor, the metal conductor is in a metal conductor connecting hole structure, the memory part is provided with a memory array, and a functional circuit of the memory chip is arranged on the control part.

In a first possible implementation manner of the first aspect, the functional circuit includes an SRAM repair cell circuit, and the SRAM repair cell circuit is configured to replace a failed memory cell in the memory array to repair the memory array.

In a second possible implementation form of the first aspect, the storage section is further provided with a sense amplifier;

other functional circuits of the memory chip are provided in the control section.

In a third possible implementation manner of the first aspect, the storage portion is further provided with a row-column decoding circuit;

other functional circuits of the memory chip are provided in the control section.

In a fourth possible implementation form of the first aspect, the storage section is further provided with a storage section power supply circuit;

other functional circuits of the memory chip are provided in the control section.

In a fifth possible implementation form of the first aspect, the functional circuit comprises an arithmetic functional block.

In a sixth possible implementation manner of the first aspect, the operation function module is a CPU or a GPU.

In a seventh possible implementation manner of the first aspect, the control portion comprises a control portion chip, the storage portion comprises a storage portion chip, the control portion chip and/or the storage portion chip comprises a metal layer perforation assembly disposed in a chip metal layer, and the connection pad is disposed in the metal layer perforation assembly away from the first conductor of the substrate layer.

In an eighth possible implementation of the first aspect, the first conductor is the connection pad.

In a ninth possible implementation of the first aspect, the metal layer perforation assembly further comprises a second conductor proximate to the substrate layer;

the substrate layer comprises a substrate through hole, the substrate through hole is communicated with the second conductor, and the connecting pad is arranged on the second conductor.

In a tenth possible implementation manner of the first aspect, a conductor connection hole is provided between the first conductor and the second conductor, and the second conductor is connected to the first conductor through the conductor connection hole, so that a signal can be transmitted to the first conductor through the substrate layer.

In an eleventh possible implementation of the first aspect, the second conductor is the connection pad.

In a twelfth possible implementation manner of the first aspect, the substrate via is filled with a filled conductor layer, the connection pad is disposed on a side of the filled conductor layer away from the metal layer, and the connection pad is connected to the second conductor member through the filled conductor layer.

In a thirteenth possible implementation of the first aspect, the connection pad has a shape that matches a shape of the first conductor and/or the second conductor.

In a fourteenth possible implementation manner of the first aspect, the connection pad is circular or polygonal in shape.

In a fifteenth possible implementation of the first aspect, the connection pads are also used for bonding of the memory chip package leads.

In a sixteenth possible implementation of the first aspect, the memory portion includes two or more memory portion chips; and/or the presence of a gas in the gas,

the control part comprises two or more than three control part chips.

In a seventeenth possible implementation manner of the first aspect, the hybrid bonding manner is that the connection pads of the memory portion chip and the connection pads of the control portion chip are connected through a metal conductor.

In an eighteenth possible implementation manner of the first aspect, the memory portion chips are connected with each other by hybrid bonding; and/or the presence of a gas in the gas,

the control part chips are connected in a hybrid bonding mode.

In a nineteenth possible implementation of the first aspect, the memory portion includes two or more memory portion chips having memory arrays of the same capacity; and/or the presence of a gas in the gas,

the memory part comprises two or more than three memory part chips with different capacity memory arrays.

In a twenty-first possible embodiment of the first aspect, the two or more memory portion chips are disposed on the same plane, and each of the memory portion chips is independent of the other memory portion chips.

In a twenty-first possible implementation manner of the first aspect, two or more than three of the memory portion chips are stacked in the same direction.

In a twenty-second possible implementation manner of the first aspect, two or more than three of the memory portion chips include at least one volatile memory chip and one nonvolatile memory chip.

In a twenty-third possible implementation manner of the first aspect, the volatile memory chip is a DRAM chip, and the nonvolatile memory chip is a NAND flash chip.

In a twenty-fourth possible embodiment of the first aspect, two or more than three memory portion chips are stacked, and the adjacent memory portion chips and the control portion chip are connected by hybrid bonding.

In a twenty-fifth possible implementation manner of the first aspect, two or more than three control portion chips are stacked, and adjacent storage portion chips and control portion chips are connected by hybrid bonding.

In a twenty-sixth possible implementation manner of the first aspect, at least one control portion chip is stacked and disposed between two or more than three storage portion chips at intervals, and the number of the storage portion chips on both sides of the control portion chip is the same.

In a twenty-seventh possible implementation manner of the first aspect, two or more than three of the memory portion chips are arranged in a stacked arrangement without spacing.

In a twenty-eighth possible implementation manner of the first aspect, the two or more control portion chips include at least one analog function circuit chip and at least one digital function circuit chip, wherein the analog function circuit chip is provided with only analog function circuits, and the digital function circuit chip is provided with only digital function circuits.

In a twenty-ninth possible implementation manner of the first aspect, the two or more than three memory partial chips include two adjacent memory partial chips with the same orientation.

In a thirty-first possible implementation manner of the first aspect, the two or more control sub-chips include two adjacent control sub-chips with the same orientation.

In a thirty-first possible implementation manner of the first aspect, the two or more memory partial chips include two adjacent memory partial chips disposed opposite to each other.

In a thirty-second possible implementation manner of the first aspect, the two or more control sub-chips include two adjacent control sub-chips arranged opposite to each other.

In a thirty-third possible implementation manner of the first aspect, the memory portion chip and the control portion chip that are adjacent to each other are connected by hybrid bonding.

Compared with the prior art, the 3D memory chip module provided by the embodiment of the invention at least has the following beneficial effects:

the 3D memory chip module provided by the embodiment of the invention comprises a memory part and a control part which are mutually stacked, wherein the memory part is connected with the control part in a hybrid bonding mode. The hybrid bonding method is to connect the connection pads of the memory part and the connection pads of the control part through metal conductors, the memory part is provided with a memory array, the functional circuit of the memory chip is arranged on the control part, and the metal conductors are in a metal conductor connection hole structure, so that a chip stacking structure is formed conveniently. By expanding a single memory chip into two chips of a memory part and a control part stacked on each other and providing a manufacturing process or requiring different functional circuits and memory arrays in different parts. As a driving interface circuit or a module (PHY) is not needed between two chips of the storage part and the control part of the same storage chip, the chip density of the storage chip stacking can be very high, and the mixed bonding parasitic parameters (parasitic resistance value and parasitic capacitance value) of the storage part chip and the control part chip forming the storage chip are very small, so that the RC delay is small, the data transmission speed is not lost, and the high-bandwidth data transmission of the storage chip can be realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts based on these drawings:

fig. 1 is a schematic structural diagram of a planar DRAM in some examples;

fig. 2 is a schematic structural diagram of a 3D memory chip module according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a single chip in a 3D memory chip module according to an embodiment of the present invention;

FIG. 4a is a schematic structural diagram of a single chip in another 3D memory chip module according to an embodiment of the present invention;

FIG. 4b is a schematic structural diagram of a single chip in another 3D memory chip module according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a 3D memory chip module having a plurality of memory parts according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another 3D memory chip module having a plurality of memory parts according to an embodiment of the present invention;

fig. 7 is a schematic structural view of still another 3D memory chip module having a plurality of memory parts according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a 3D memory chip module having a plurality of control parts according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another 3D memory chip module having a plurality of control parts according to an embodiment of the present invention.

Detailed Description

The present invention is further described in detail below with reference to the drawings and examples so that those skilled in the art can practice the invention with reference to the description.

It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.

In addition, it should be noted that the terms "disposed" and "connected" are to be construed broadly unless otherwise explicitly stated or limited. For example, the connection can be fixed connection or detachable connection; can be directly connected or indirectly connected through an intermediate medium; either integrally connected or communicating between the interior of the two components. Or the two elements may perform signal transmission and data communication. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

At present, in order to obtain a higher bandwidth, a conventional TSV structure is generally used to communicate the HBM chip and the HMC chip of each memory portion. The HBM chip is formed by stacking a plurality of DDR double-rate synchronous dynamic random access memory part chips and a PLD (Programmable Logic Device), then packaging the chips together with a GPU (graphics processing unit), and realizing connection between the chips by utilizing the connection of silicon through holes and micro-bumps, thereby realizing a high-capacity and high-bit-width DDR combined array. And the HMC chip is formed by stacking a plurality of DRAM layers on a basic logic layer, and the optimal combination of logic and DRAM processes is realized in a heterogeneous package. The DRAM layer handles only data, while the logical layer handles all control functions in the HMC.

However, it is very difficult to realize a stacked structure of several tens of layers, which is difficult to realize, and the technology is not mature, and there are problems of high operational risk, poor stability, etc. Furthermore, since both HBM and HMC use silicon interposers, the cost is high and the output is very limited. In addition, the heat dissipation performance is also seriously affected due to the fact that a large number of DRAM stacks and GPUs are packaged together.

In view of the above problems, an embodiment of the present application provides a 3D memory chip module, which solves the problems of high manufacturing cost, poor circuit flexibility, high operational risk, poor stability, large RC delay, and large power consumption caused by stacking memory chips through technologies such as a through silicon via technology or the like in an existing planar memory chip.

Fig. 2 is a schematic structural diagram of a 3D memory chip module according to an embodiment of the present invention, and as shown in fig. 2, the 3D memory chip module may include:

a control part 100 and a memory part 200 stacked on each other, the memory part 200 being connected to the control part 100 by a hybrid bonding method in which connection pads of the memory part 200 and connection pads of the control part 100 are connected by metal conductors. Illustratively, the metal conductor is a metal conductor connection hole structure, the memory portion is provided with a memory array, and the functional circuit of the memory chip is arranged on the control portion.

It should be noted that the 3D memory chip module may be a part of a 3D memory chip, and may also be regarded as a 3D memory chip.

In some examples, the control portion 100 and the storage portion 200 may be separate planar chips or wafers, respectively. For example, the Chip to Chip (C2C) may be stacked planar chips, that is, 3D chips stacked up and down; or stacked wafers (W2W, wafer to wafer), and after being diced, 3D chips stacked up and down are formed.

In some examples, the above-mentioned hybrid bonding method may use two ends of the metal conductor 300 to be respectively connected to connection pads (Connect pads) on the memory portion 200 and the control portion 100.

For example, the control portion may include a control portion chip, the memory portion may include a memory portion chip, and the control portion chip and/or the memory portion chip may include a metal layer via assembly disposed in a metal layer of the chip, the connection pad may be disposed on the first conductor away from the substrate layer in the metal layer via assembly, and the connection pad may also be disposed on a side of the substrate via away from the metal layer.

As shown in fig. 3, in some examples, the control portion 100 and the storage portion 200 may be planar chips or wafers. The control section 100 and the memory section 200 may include a substrate layer 20 and a metal layer 10, which may also be referred to as a device layer and a metal wiring layer, when manufactured and produced, respectively. The metal layer 10 may include a first surface and a second surface that are oppositely disposed, the second surface of the metal layer 10 is disposed on the substrate layer 20, and a metal layer perforating assembly may be disposed in the metal layer 10, and the metal layer perforating assembly may include: a first conductor 11, a second conductor 12 and a conductor connection hole, wherein the first conductor 11 may be formed on a first surface of the metal layer 10. The second conductor 12 may be formed on the second surface of the metal layer 10. For convenience of description, the surface of the chip on the side where the substrate layer is located can be referred to as the reverse side or the back side of the chip; the surface of the side where the metal layer is located is called the front side of the chip. The front or back of the memory part 200 or the control part 100 may be provided with connection pads that may be used for hybrid bonding between the control part 100 and the memory part 200 or for bonding of package leads of the memory chip.

Exemplarily, referring to fig. 3, the connection pad may be disposed on the front surface of the control part chip or the memory part chip, which may be understood as the connection pad disposed on the first conductor 11 of the metal layer perforation assembly.

For example, the shape of the connection pad and the shape of the first conductor and/or the second conductor may be matched to meet the requirement of sufficient contact between the connection pad and the metal conductor in hybrid bonding. For example, the connection pad may have a rectangular shape or a circular shape, and may also have another polygonal shape or another shape, which is not limited herein.

For example, the connection pad may also be the first conductor, and it is understood that the first conductor represented by the top metal in the metal layer may be directly used as the connection pad, and the connection pad may also be used for hybrid bonding, and the process of manufacturing the chip may be further simplified.

According to some embodiments, as shown in fig. 4a, the substrate layer 20 may include a substrate via 21, the substrate via 21 may communicate with the second conductor 12, and the connection pad may be disposed on the second conductor 12.

In an exemplary embodiment, a conductor connection hole is disposed between the first conductor and the second conductor, and the second conductor is connected to the first conductor through the conductor connection hole, so that a signal can be transmitted to the first conductor through the substrate layer.

For example, the connection pad may be disposed on a back surface of the control portion chip or the memory portion chip, and the substrate layer is dug from the back surface of the chip to form the substrate through hole to the second conductor represented by the bottom metal of the metal layer, so as to dispose the connection pad on the bottom metal. First conductor members represented by the bottommost metal of the bottom-most metal and the topmost metal of the metal layers may be connected by conductor connection holes to enable signals to be transmitted to the first conductor members through second conductor members in the substrate layer.

For example, there are two ways to provide the connection pads on the lowest layer of metal:

first, referring to fig. 4a, the lowest layer metal can be directly provided as a connection pad.

A second way can be seen in fig. 4b, after filling the substrate via 21 with a conductor, a connection pad 23 is provided with a metal on the backside of the chip, where the connection pad 23 is connected to the second conductor 12 represented by the bottom-most metal through the filled conductor layer 22 in the substrate via 21. The connection pad 23 at the bottom of the substrate via is connected to the second conductor 12 by filling the conductor layer 22, and then can be connected to the first conductor through the conductor connection hole, so that the signal can be transmitted to the topmost metal of the metal layer 10 through the substrate layer 20, thereby communicating the signal with the whole chip.

For example, the form of the connection pad provided on the second conductor in the bottom-most metal or the form of the connection pad connected to the second conductor by filling the conductor layer may be identical to the shape of the first conductor or the connection pad in the top-most metal, and also serves to satisfy sufficient contact of the connection pad with the metal conductor in hybrid bonding. For example, the connection pad may have a rectangular shape or a circular shape, and may also have another polygonal shape or another shape, which is not limited herein. For example, when the connection pad is on the front surface of the memory portion or the control portion, the connection pad is provided on the topmost metal, and when the connection pad is on the back surface of the memory portion or the control portion, the connection pad is directly or indirectly connected to the bottommost metal through a filled conductor layer, and the connection pads on both surfaces may have a circular shape of the same size.

It should be noted that the connection pads are provided to facilitate connection of the chip to the metal conductors in the hybrid bond. The connection pad is arranged on the front surface of the chip and is connected with the topmost metal of the metal layer perforating assembly in the metal layer, wherein the topmost metal can be directly arranged in the form of the connection pad; the connection pad is arranged on the back surface of the chip and is connected with the lowest metal layer of the metal layer. Since the provision of the connection pads on the back side of the chip requires the substrate to be hollowed out, it is relatively easier and more reliable to provide the connection pads on the topmost metal for hybrid bonding than when the chip is not in the middle of the stacked chips.

Illustratively, the memory part comprises two or more than three memory part chips, and the memory part chips are connected with each other by hybrid bonding; and/or, the control part can comprise two or more than three control part chips, and the control part chips are connected with each other by a mixed bonding mode. The stacking manner between the control portion chips, between the storage portion chips, and between the control portion and the storage portion chips may be various, and is not limited herein.

Specifically, the storage part and the control part of the 3D memory chip module are connected in a hybrid bonding manner, because the RC parasitic parameter of the hybrid bonding is very small, a driving interface circuit or module (PHY) is not required between the two chips of the storage part and the control part, and further, the circuit module in the original planar DRAM can be flexibly placed in the storage part or the control part as required; even the storage part can be expanded into the stack of a plurality of storage function chips, so that the chip density of the stack of the storage chips can be very high, and parasitic parameters (parasitic resistance value and parasitic capacitance value) of hybrid bonding of the storage part chip and the control part are very small, so that the RC delay is small, the data transmission speed is not lost, and the high-bandwidth data transmission of the storage chips can be realized.

In connection with the above example, referring to fig. 2, the control part 100 and the memory part 200 stacked on each other, a side surface of the memory part 200 connected to the control part 100 may be provided with a connection pad for use in hybrid bonding, i.e., a manner of growing a metal conductor of hybrid bonding on the connection pad. The corresponding side surface of the control portion 100 that is connected to the memory portion 200 is also provided with connection pads for hybrid bonding, i.e. a way of growing a metal conductor of the hybrid bonding on the connection pads. The control portion 100 and the memory portion 200 are connected and communicate data by a hybrid bonded metal conductor.

For example, the aforementioned connection pad may be disposed on the front or rear surface of the memory part 200 or the control part 100. In some examples, the control portion 100 and the storage portion 200 stacked on each other may be in a face-to-face manner, that is, a front chip surface of the control portion 100 and a front chip surface of the storage portion 200 are opposite to each other, the front chip surfaces of the two portions are connected by hybrid bonding, and a back chip surface of the control portion 100 and a back chip surface of the storage portion 200 are outside. Thus, it is only necessary to provide connection pads on the topmost metal of the control portion 100 and the memory portion 200 for hybrid bonding to connect with the metal conductors 300. As described above, hybrid bonding is easier and more reliable because the connection pads are provided on the topmost metal. Therefore, the face-to-face mixed bonding is preferably adopted, and the manufactured 3D memory chip module has higher reliability and better yield.

In some examples, since the connection pads are also used for bonding the leads of the memory chip package, after the control part 100 and the memory part 200 stacked on each other are connected by the metal conductor 300 of the hybrid bonding, the side of the memory part chip and/or the control part chip in the control part 100 and the memory part 200 stacked on each other, which faces away from the metal conductor, may be provided with connection pads, wherein the connection pads may be used for leading out package lead wires for packaging of 3D chips.

It should be noted that, the holes in the metal layer perforation assemblies on the memory portion and the control portion are non-through holes, when a chip is packaged, unlike a conventional TSV, although signals can pass through the whole chip for transmission, the holes on the chip do not need to pass through the whole chip, the connection pads can be used for leading out pin connection lines, and after the memory chip is packaged, the memory chip can be connected with an external circuit through pin leads led out from the connection pads to serve as a functional unit, and the integrated circuit connected with the functional unit is matched with the external circuit to realize the whole function of the electronic device.

The above example describes in detail a hybrid bonding method between the memory portion and the control portion and a punch structure for ensuring data transmission in a single chip after the 3D memory chip module is separated into the memory portion and the control portion which are stacked on each other. In the above 3D memory chip module, the respective function assignments of the memory portion and the control portion will be specifically described below with reference to some examples.

According to some embodiments, the 3D memory chip module may include: the memory chip comprises a memory part and a control part which are stacked with each other, wherein the memory part and the control part are connected through a hybrid bonding mode, the hybrid bonding mode can be that a connecting pad of the memory part and a connecting pad of the control part are connected through a metal conductor, the memory part is provided with a memory array, and a functional circuit of the memory chip is arranged on the control part.

In some examples, the above-described memory portion may be provided with the most basic memory cell, for example, a memory array. And the functional circuit of the 3D memory chip module may be disposed on the control part.

Illustratively, the functional circuit may include: the device comprises a row-column decoding circuit, a power circuit, a data processing circuit and an interface circuit. In the 3D memory chip module, when the data is read out from the memory part, the control part receives the command related to the read data, the row and column decoding circuit decodes the address, the data in the corresponding memory array in the memory part is selected, the data enters the control part from the memory part, and then the data is read out from the control part under the drive of the interface circuit and the clock control of the data processing circuit. In the 3D memory chip module, when data is written into the memory portion, the data is written into the memory array of the memory portion after the control portion is driven by the interface circuit and allocated by the data lines of the data processing circuit, so that the basic function of the memory chip can be completely realized.

Since the smallest Memory Cell (Memory Cell) in the Memory array of the Memory portion uses a special process capable of storing data, the manufacturing process thereof is very complicated and not well controlled. The memory array is placed in the memory part to ensure the consistency of the process, and because other circuits are already placed in the control part, the particularity of the process does not influence other circuits.

According to some embodiments, the functional circuit may further include an SRAM repair cell circuit, and the SRAM repair cell circuit is configured to replace a failed memory cell in the memory array to repair the memory array. Typically, redundant cells are provided in a memory array in order to repair failed cells in the memory array. In the present invention, the functional circuit may further include an SRAM repair cell circuit for replacing a redundant cell in the memory array. The control part can manufacture an SRAM circuit with better performance by using a logic process, and the SRAM circuit is used for repairing failed units in the storage array.

According to some embodiments, the control portion may use a dedicated logic process, and the logic process may also meet the performance requirements of a portion of the analog circuit, which may not be affected by the particular process of the memory cell. The logic process can well enable other circuits including a row-column decoding circuit, a power supply circuit, a data processing circuit, an interface circuit, an SRAM repairing unit circuit and the like to play a better role. For example, row column decoding circuits, data processing circuits, etc. are purely digital logic, and higher data frequencies and bandwidths can be achieved using logic technology, while power consumption can also be saved.

According to some embodiments, in the memory chip, the memory portion is provided with a memory array and a sense amplifier, and the other functional circuit of the memory chip is provided in the control portion. When the data is read out from the storage part, the control part receives the command related to the read data, the row-column decoding circuit decodes the address, the data in the corresponding storage array in the storage part is selected, the data is amplified by the sensitive amplifier from the storage part and then enters the control part, and then the data is read out from the control part under the driving of the interface circuit and the clock control of the data processing circuit. Because the memory cells in the memory array use a special process that can store data, the fabrication process is very complicated and poorly controlled. The arrangement of the sense amplifier and the sense amplifier in the storage part can ensure the consistency of the process, and because other circuits are already arranged in the control part, the particularity of the process of the sense amplifier does not influence other circuits. Meanwhile, the sensitive amplifier is directly connected with the storage unit in the storage array, the sensitive amplifier and the storage unit are placed in the same chip as a storage part, the matching of data reading can be guaranteed, and the data reading accuracy is higher.

According to some embodiments, the memory portion may further include a row-column decoding circuit, and the other functional circuits of the memory chip are disposed in the control portion. The row and column decoding circuit described above is added to the memory section. It is understood that, in the memory portion, the row and column decoding circuit may perform frequent operations and controls on the memory array, and the row and column decoding circuit is very closely connected to the memory array, and there are many connections between them. The row-column decoding circuit is arranged in the storage part, so that the connecting lines of hybrid bonding between the storage part and the control part can be effectively reduced, the complexity of 3D chip manufacturing is reduced, and the yield is improved. Meanwhile, the row and column decoding circuit and the memory array are arranged together, so that errors caused by process mismatch can be reduced.

Illustratively, the storage part is further provided with a storage part power supply circuit, and other functional circuits of the storage chip are arranged in the control part. Specifically, during data read-write operation and other necessary operations, the storage array and the sense amplifier need to consume a large amount of electricity, a storage part power supply circuit with a basic power supply unit circuit, which is needed by the storage array and the sense amplifier, is placed in the storage part, and the basic power supply function can well meet the requirement of a functional circuit in the storage part on electric energy during the data read-write operation. The stability and reliability of the operation of the above-mentioned storage section are improved.

It should be noted that, while the power supply circuit is provided in the storage portion, the control portion may also be provided with a basic control portion power supply circuit, and the two power supply circuits may supply power to the storage portion and the control portion, respectively. Of course, in the above-described scheme in which the power supply circuit is provided in the storage portion, the power supply circuit of the storage portion may be reused when the control portion needs to supply power, instead of providing the power supply circuit in the control portion. In the scheme, the storage part is provided with the power supply circuit for supplying power, so that the technical effects of stability and reliability of the storage part are still improved.

The control section is understood to be a control section in a normal memory chip, which can perform, for example, row and column decoding and simple data processing operations, but does not have an arithmetic function. Accordingly, in some examples, the control portion of the memory chip may not be limited to only the control function of the memory chip, but may also include other more powerful logic functions, for example, the control portion may be extended to a processor.

According to some embodiments, in the 3D memory chip module, an arithmetic function module may be further provided in the control part. The running function module may be a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU). In this way, the data in the storage section can be directly subjected to data arithmetic processing in the control section. The control part and the storage part are connected in a hybrid bonding mode, and parasitic parameters of signal transmission between the control part and the storage part are small, so that a system formed by the control part and the storage part can overcome storage obstacles, and the data processing capacity is greatly improved.

It should be noted that the memory portion and the control portion in the 3D memory chip module may still adopt a hybrid bonding manner as shown in fig. 2, and the transmission of signals in the planar chip constituting the 3D memory chip module may be implemented by the above chip punching scheme that does not penetrate through the entire chip. The through silicon via does not need to be arranged, only the substrate through hole needs to be arranged on the substrate, and the metal layer perforating assembly is arranged in the metal layer, so that the diameter and the length of the hole are greatly reduced, the etching process difficulty is further reduced, the area occupied by the metal layer is reduced, the resistance parasitic parameter and the capacitance parasitic parameter are reduced, the preparation period of a chip unit is shortened, and the production cost is reduced.

In the scheme of splitting the 3D memory chip module into the memory portion and the control portion stacked on each other, the above example describes in detail the hybrid bonding manner between the memory portion and the control portion, the puncturing structure for ensuring data transmission within a single chip, and the respective function assignments of the memory portion and the control portion, and further describes in detail the stacking manner of the memory portion and the control portion stacked on each other in the 3D chip.

As shown in fig. 2, the 3D memory chip module may include:

a control part 100 and a storage part 200 stacked on each other, the storage part 200 being connected to the control part 100 by hybrid bonding. The memory portion may include two or more than three memory portion chips, and/or the control portion may include two or more than three control portion chips. For example, the 3D memory chip module may include a memory part composed of three memory part chips and a control part composed of one control part chip, or the 3D memory chip module may include a memory part composed of one memory part chip and a control part composed of three control part chips, or the 3D memory chip module may include a memory part composed of three memory part chips and a control part composed of three control part chips. The control part chip or the storage part chip refers to a single chip (Die) or a Wafer (Wafer), the chip refers to a 2D planar chip, and the Wafer refers to a 2D planar Wafer. The storage part and the control part can be connected in a mixed bonding mode to form various combination modes.

The storage part and the control part of the 3D storage chip module are connected in a hybrid bonding mode, a driving interface circuit or a module (PHY) is not needed between the two chips of the storage part and the control part which are used as the same storage chip, further, the chip density of the storage chip stacking can be very high, the stacking of more chips can be carried out, the parasitic parameters (parasitic resistance value and parasitic capacitance value) of the hybrid bonding connected with the storage part and the control part are very small, therefore, the RC delay is small, the data transmission speed is not lost, and the high-bandwidth data transmission of the storage chip can be realized.

For example, the memory portion chip and/or the control portion chip may be connected by hybrid bonding. The hybrid bonding may be a method in which the connection pads of the memory portion and the connection pads of the control portion are connected by metal conductors. The memory part may be regarded as a chip mainly used as a memory function among a plurality of stacked chips of the 3D memory chip module, and the control part may be regarded as a chip mainly used as a control function among a plurality of stacked chips of the 3D memory chip module.

According to some embodiments, in the memory chip, in addition to the memory part chip and the control part chip, the memory part chip and the control part chip may be connected by the hybrid bonding method.

In some examples, the memory portion includes two or more than three memory portion chips having the same capacity memory array; and/or, the memory part comprises two or more than three memory part chips with memory arrays with different capacities.

According to some embodiments, two or more than three memory portion chips may be disposed on the same plane, each of the above memory portion chips being independent of each other. The memory part chip can be a memory unit with a memory array, and the memory units can be respectively connected with the control part through a metal conductor in a mixed bonding mode. The plurality of memory cells in the same plane chip may not be physically connected, i.e., not connected by pin lines or metal conductors.

Fig. 5 is a schematic structural diagram of a 3D memory chip module having a plurality of memory cells according to an embodiment of the present invention. The term "having a plurality of memory cells" as used herein means that the memory portion has a plurality of memory cells in the same planar chip. As shown in fig. 5, the memory portion may include a first memory cell, a second memory cell, through an nth memory cell, and the n memory cells may be connected to the control portion by a metal conductor through hybrid bonding, respectively. The n memory cells may not be physically connected, that is, the n memory cells are not connected by a pin wire or a metal conductor, but the n memory cells are not stacked on each other but are positionally arranged on the same plane.

Specifically, a connection pad is provided on a side surface of the n memory cells connected to the control portion for connection with a metal conductor in hybrid bonding, and then a metal conductor is grown on the connection pad (hybrid bonding), and a connection pad may be provided on a corresponding side surface of the control portion connected to the n memory cells, and then the control portion and the n memory cells are connected to each other through the metal conductor in hybrid bonding, so as to perform data communication. With this structure, the control section can control the storage section relatively easily, and the reliability is relatively high. The n memory cells may be memory arrays of the same capacity (or different capacities), independent of each other. Illustratively, the above-described memory cells independent of each other may be substituted for each other as needed. The 3D memory chip module has the advantages that if one memory cell fails to work normally, other memory cells can be replaced as redundant cells, and therefore reliability of the whole 3D memory chip module is improved.

For example, referring to fig. 5, the control portion and the plurality of memory cells formed by a planar chip are used as the planar memory portion, and as described above, since the connection pads are provided on the back surface of the chip, the substrate needs to be perforated, so that the hybrid bonding is relatively easier and more reliable when the connection pads are provided on the topmost metal. Therefore, the memory portion and the control portion preferably adopt a face-to-face hybrid bonding mode, that is, the front surface of the chip of the control portion 100 is opposite to the front surface of the chip of the memory portion 200, the front surfaces of the chips of the two portions are connected by the hybrid bonding mode, and the back surface of the chip of the control portion 100 and the back surface of the chip of the memory portion 200 are outside.

According to some embodiments, in the memory chip, two or more than three memory part chips are stacked, and two adjacent chips are connected by hybrid bonding. It is understood that not only the chips of the memory portion and the control portion may be connected by hybrid bonding, but also the chips of the memory portion and the memory portion may be connected by hybrid bonding. When two or more than three memory part chips are stacked and two adjacent chips are connected by hybrid bonding, the memory chip scheme can have a plurality of situations, and each situation has corresponding functions and characteristics.

For example, two or more than three of the above memory portion chips may be stacked without spacing. Fig. 6 is a schematic structural diagram of another 3D memory chip module having a plurality of memory portions according to an embodiment of the present invention, and as shown in fig. 6, a control portion of the memory chip may include a control portion chip 110, and the control portion chip has a data and signal processing function. The memory part of the memory chip may include a first memory part chip 210 and a second memory part chip 220. The control part chip 110, the first memory part chip 210, and the second memory part chip 220 are sequentially stacked from top to bottom. The first memory part chip 210 and the second memory part chip 220 are stacked with the control part chip 110. Specifically, a connection pad is provided on a side surface of the first memory portion chip 210 connected to the control portion chip 110 for connection with a metal conductor in hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding manner, and correspondingly, a connection pad may also be provided on a side surface of the control portion chip 110 connected to the first memory portion chip 210 for connection with a metal conductor in hybrid bonding, and then a metal conductor is grown on the metal pad to connect the control portion chip 110 and the memory portion chip 210 in a hybrid bonding manner and perform data communication.

It should be noted here that, as described above, since it is relatively easier and more reliable to provide the connection pads on the topmost metal of the chip for hybrid bonding, the control portion chip 110 is faced to the first memory portion chip 210. Accordingly, since the memory part chip 210 is further required to be connected to the memory part chip 220, the second memory part chip 220 is also disposed to face the first memory part chip 210. That is, connection pads are provided on the front surfaces of the control part chip 110 and the second memory part chip 220 for connection with metal conductors in hybrid bonding.

For the first memory part chip 210 placed between the control part chip 110 and the second memory part chip 220, its front side orientation can be placed as appropriate because its front side and back side are connected to the control part chip 110 and the second memory part chip 220 by means of hybrid bonding. However, in order to ensure the consistency between the first memory portion chip 210 and the second memory portion chip 220, it is generally preferable that the orientations of the front surfaces of the first memory portion chip 210 and the second memory portion chip 220 are consistent, so that the consistency between the first memory portion chip 210 and the second memory portion chip 220 is good, and the matching between the first memory portion chip 210 and the second memory portion chip 220 of the memory portion with respect to the entire 3D chip is good, whereby the reliability of the manufactured chip, the reliability of the operation of the chip, and the reliability of data reading and writing are good.

It is to be understood that the above memory portion may be a plurality of memory portion chip stacks. The memory chip has the advantages of convenience in expanding memory capacity and simplicity in form. When the storage part is formed by stacking a plurality of storage part chips, the storage part chips are stacked in the same direction, that is, the storage part chips are all upward or downward.

For example, the plurality of memory portion chips stacked in the memory portion may be the same chip or different chips. When the plurality of memory portion chips stacked in the memory portion are different chips, at least one volatile memory chip may be included, for example: a DRAM memory chip, and at least one non-volatile memory chip, such as: NANDflash memory chip. The advantages are that the data access speed can be guaranteed through the DRAM memory chip, and the data on the nonvolatile memory chip can not be lost when the chip is powered off through the NANDflash memory chip.

According to some embodiments, in the memory chip, at least one of the control portion chips is stacked between two or more than three of the memory portion chips, and the number of the memory portion chips on both sides of the control portion chip is the same. Specifically, fig. 7 is a schematic structural diagram of another 3D memory chip module having a plurality of memory portions according to an embodiment of the present invention, and as shown in fig. 7, a control portion of the memory chip may include a control portion chip 110, and the control portion chip has a data and signal processing function. The memory part may include a first memory part chip 210 and a second memory part chip 220. The memory chip may also be formed in other structures, for example, the control part chip 110 of the control part is disposed between the first memory part chip 210 and the second memory part chip 220.

Specifically, a connection pad is provided on a side surface of the first memory portion chip 210 connected to the control portion chip 110 for connection with a metal conductor in a hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding, and accordingly, a connection pad is also provided on a side surface of the control portion chip 110 connected to the first memory portion chip 210 for connection with a metal conductor in a hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding, so that the control portion chip 110 and the first memory portion chip 210 are connected and perform data communication. Accordingly, since the control portion chip 110 needs to be connected to the second memory portion chip 220, a connection pad needs to be disposed on a side of the control portion chip 110 away from the metal conductor for connection with the metal conductor in the hybrid bonding, and then the metal conductor is grown on the connection pad to form the hybrid bonding, and the hybrid bonding is continued to be connected to the second memory portion chip 220, so as to form a chip stack structure. The memory chip has the advantages of convenience in expanding memory capacity, simple form and good symmetry. It should be noted that the memory portion is not limited to having the first memory portion chip 210 and the second memory portion chip 220, and may have more memory portion chips and continue to form a chip stack structure.

Similarly, the memory chip has the advantages of convenience in expanding the memory capacity and simplicity in form. The plurality of memory portion chips stacked in the memory portion may be the same chip or different memory chips. When the plurality of memory portion chips stacked in the above memory portion are different chips, at least one of them may be a volatile memory chip such as a DRAM memory chip and at least one other thereof may be a nonvolatile memory chip such as a NAND flash memory chip. The method has the advantages that the data access speed can be guaranteed through the DRAM memory chip, and the data on the nonvolatile memory chip can not be lost when the chip is powered off through the NAND flash memory chip.

According to some embodiments, in the memory chip, the two or more control portion chips are stacked, and two adjacent chips are connected by a metal conductor in a hybrid bonding manner. When two or more than three control part chips are stacked and two adjacent chips are connected through a metal conductor, the memory chip scheme can have various situations, and each situation has corresponding functions and characteristics.

For example, in the memory chip, two or more than three of the control portion chips may include at least one analog function circuit chip and at least one digital function circuit chip, where the analog function circuit chip is provided with only an analog function circuit, and the digital function circuit chip is provided with only a digital function circuit. Fig. 8 is a schematic structural diagram of a 3D memory chip module having a plurality of control portions according to an embodiment of the present invention, and as shown in fig. 8, the memory portion of the memory chip may include a memory portion chip 210. The control portion of the memory chip may include a first control portion chip 110 and a second control portion chip 120, the first control portion chip 110 has a data and signal processing function, and the second control portion chip 120 has a power supply function. The first control part chip 110 and the second control part chip 120 are stacked on the memory part chip 210. The first control part chip 110, the second control part chip 120, and the memory part chip 210 are stacked in order from top to bottom.

Specifically, a connection pad is provided on a side surface of the second control portion chip 120 connected to the memory portion chip 210 for connecting with a metal conductor in a hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding; accordingly, a connection pad may be provided on a side surface of the memory part chip 210 connected to the second control part chip 120 for connection with a metal conductor in a hybrid bond, and then a metal conductor is grown on the connection pad to form the hybrid bond. The second control chip 120 and the memory chip 210 are connected and perform data communication. Accordingly, since the second control portion chip 120 needs to be connected to the first control portion chip 110, a connection pad needs to be provided on a side of the second control portion chip 120 away from the memory portion chip 210 for connection with a metal conductor in a hybrid bonding, and then a metal conductor is grown on the connection pad (hybrid bonding); and is continuously connected with the control part chip 110 by the hybrid bonding method to form a chip stack structure.

It should be noted that the memory portion is not limited to the memory portion chip 210, the control portion is not limited to the first control portion chip 110 and the second control portion chip 120, and more control portion chips may be provided and a chip stack structure may be continuously formed. The memory chip has the advantages that the control part is divided into the plurality of chips, the analog function and the digital function can be set respectively, the control part can be compatible with the analog function process and the digital function process, and the advantages and the performances of the processes can be combined.

Similarly, in addition to the way in which the first control portion chip 110, the memory portion chip 210, and the second control portion chip 220 are stacked from top to bottom as shown in fig. 8, other ways are also possible, and the stacking order thereof is not limited.

The memory portion chip 210 of the above-described memory portion may be provided with the most basic memory cells, for example, a memory array. And the functional circuits of the memory chip may be provided in the control part chip 110 and the control part chip 120. The functional circuit of the control part chip 110 may include: the device comprises a row-column decoding circuit, a data processing circuit and an interface circuit. The functional circuit of the control part chip 120 may include: a power supply circuit. In the memory chip, when the memory part is read, the control part receives the command related to the read data, the row and column decoding circuit decodes the address, the data in the corresponding memory array in the memory part is selected, the data enters the control part from the memory part, and then the control part drives the interface circuit and controls the clock of the data processing circuit to read the data. In the memory chip, when data is written into the memory part, the data is written into the memory array of the memory part after the control part passes through the drive of the interface circuit and the distribution of the data lines of the data processing circuit, so that the basic functions of the memory chip can be completely realized. Because the memory cells in the memory array use a special process that can store data, the fabrication process is very complicated and poorly controlled. The memory array is placed in the memory part to ensure the consistency of the process, and because other circuits are already placed in the control part, the particularity of the process does not influence other circuits.

Fig. 9 is a schematic structural diagram of another 3D memory chip module having a plurality of control portions according to an embodiment of the present invention, and as shown in fig. 9, the control portion of the memory chip may include a memory portion chip 210. The control part of the memory chip may include a first control part chip 110 and a second control part chip 120, the first control part chip 110 may have a function of data and signal processing, and the second control part chip 120 may have a function of power supply. The first control part chip 110 and the second control part chip 120 are stacked on the memory part chip 210. Specifically, a connection pad is provided on a side surface of the second control portion chip 120 connected to the memory portion chip 210 for connection with a metal conductor in a hybrid bond, and then a metal conductor is grown on the connection pad to form the hybrid bond. Correspondingly, a connection pad may be provided on the side of the memory portion chip 210 connected to the second control portion chip 120 for connection with a metal conductor in a hybrid bond, and then a metal conductor is grown on the connection pad to form the hybrid bond. The control second control chip 120 and the memory chip 210 are connected and perform data communication. Accordingly, since the memory portion chip 210 needs to be connected to the first control portion chip 110, a connection pad needs to be disposed on a side of the memory portion chip 210 away from the metal conductor for connection with the metal conductor in the hybrid bonding, and then the metal conductor is grown on the connection pad to form the hybrid bonding, and the hybrid bonding is connected to the first control portion chip 110 to form a chip stack structure. It should be noted that the memory portion is not limited to the memory portion chip 210, the control portion is not limited to having the control portion chips 210 and 220, and more control portion chips may be provided and the chip stack structure may be continuously formed. The control part of the memory chip is divided into a plurality of chips, and can be respectively provided with an analog functional circuit and a digital functional circuit, so that the control part can be compatible with an analog functional process and a digital functional process, and the advantages and performances of the processes can be combined to be stronger.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

While embodiments of the invention have been disclosed above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.

Claims (10)

1. A3D memory chip module, comprising:

the memory comprises a memory part and a control part which are stacked mutually, wherein the memory part and the control part are connected in a hybrid bonding mode, the hybrid bonding mode is that a connecting pad of the memory part and a connecting pad of the control part are connected through a metal conductor, the metal conductor is in a metal conductor connecting hole structure, the memory part is provided with a memory array, and a functional circuit of the memory part is arranged on the control part.

2. The memory chip module of claim 1,

the functional circuit comprises an SRAM repair unit circuit, and the SRAM repair unit circuit is used for replacing a failed storage unit in the storage array so as to repair the storage array.

3. The memory chip module of claim 1,

the memory portion is also provided with a sense amplifier.

4. The memory chip module of claim 1, wherein the functional circuit comprises an arithmetic functional module.

5. The memory chip module according to claim 1, wherein the control section comprises a control section chip, the memory section comprises a memory section chip, the control section chip and/or the memory section chip comprises a metal layer perforation assembly disposed within a chip metal layer, the connection pad being disposed in the metal layer perforation assembly away from the first conductor of the substrate layer.

6. The memory chip module of claim 1, wherein the connection pads are also used for bonding of the memory chip package leads.

7. The memory chip module according to claim 2, wherein the memory portion includes two or more memory portion chips; and/or the presence of a gas in the gas,

the control part comprises two or more than three control part chips.

8. The memory chip module of claim 7,

the hybrid bonding mode is that the connection pad of the storage part chip and the connection pad of the control part chip are connected through a metal conductor.

9. The memory chip module of claim 7,

the storage part chips are connected in a hybrid bonding mode; and/or the presence of a gas in the gas,

the control part chips are connected with each other in a mixed bonding mode.

10. The memory chip module according to claim 7, wherein the memory portion includes two or more than three memory portion chips having the same capacity memory array; and/or the presence of a gas in the gas,

the memory part comprises two or more than three memory part chips with different capacity memory arrays.

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