CN115755521A - Method and device for improving optimized convergence of mask pattern and computer equipment - Google Patents
Method and device for improving optimized convergence of mask pattern and computer equipment Download PDFInfo
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Abstract
The invention relates to the technical field of photoetching, in particular to a method and a device for improving optimized convergence of a mask pattern and computer equipment. Selecting a first preset area, wherein the first preset area comprises an initial mask layout, and defining the first preset area as an initial boundary area; dividing the initial boundary area into blocks with preset sizes according to a preset rule, optimizing all the blocks in the initial boundary area according to a preset sequence and obtaining a first optimization result; adding a second preset area outside the initial boundary area to obtain a corrected boundary area, wherein the area of the corrected boundary area, which is overlapped with the initial boundary area, is larger than that of the initial boundary area; dividing the correction boundary area into blocks with the same preset size according to the same preset rule; optimizing and correcting all the blocks in the boundary area according to a preset sequence and obtaining a second optimization result; and combining the first optimization result and the second optimization result to obtain a final optimized mask layout. The problem that the convergence of the optimization result of the mask pattern is poor is solved.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of photoetching, in particular to a method and a device for improving optimized convergence of a mask pattern and computer equipment.
[ background ] A method for producing a semiconductor device
Because the computation workload of computing the photoetching is huge, the computing power of the current ED A software and a computer server cluster is not enough to support the optimization of the whole chip layout at one time. Therefore, in the mask optimization process, the mask layout is firstly partitioned, then each partition is optimized according to the sequence, and finally the optimization results of each partition are spliced to obtain a complete optimized mask graph.
However, each block needs to be expanded outwards by a certain range during optimization to ensure the accuracy of the calculation result. When the current block optimizes the mask pattern, the optimization result of the mask pattern in the boundary of the block and the optimization result of the mask pattern in the boundary after the block is expanded are both stored. As a result, the convergence of the optimization results of the mask patterns near the boundary of adjacent blocks during optimization is poor, and thus, a chip circuit formed on a silicon wafer after the patterns near the boundary are exposed by a lithography machine is likely to be short-circuited or broken.
[ summary of the invention ]
In order to solve the problem that the convergence of the optimization result of the mask pattern near the boundary of the adjacent blocks is poor when the adjacent blocks are optimized, the invention provides a method, a device and computer equipment for improving the optimization convergence of the mask pattern.
In order to solve the technical problems, the invention provides the following technical scheme: a method for improving the optimized convergence of a mask pattern is applied to an initial mask layout and comprises the following steps:
selecting a first preset area, wherein the first preset area comprises an initial mask layout, and defining the first preset area as an initial boundary area;
dividing the initial boundary area into blocks with preset sizes according to a preset rule, optimizing all the blocks in the initial boundary area according to a preset sequence and obtaining a first optimization result;
adding a second preset area outside the initial boundary area to obtain a corrected boundary area, wherein the area of the corrected boundary area, which is overlapped with the initial boundary area, is larger than that of the initial boundary area; dividing the correction boundary area into blocks with the same preset size according to the same preset rule;
optimizing and correcting all blocks in the boundary region according to a preset sequence and obtaining a second optimization result;
and combining the first optimization result and the second optimization result to obtain a final optimized mask layout.
Preferably, the area of the first preset region is greater than or equal to the area of the initial mask layout.
Preferably, a boundary line formed between adjacent blocks in the initial boundary region does not coincide with a boundary line formed between adjacent blocks in the modified boundary region.
Preferably, the step of adding a second preset area outside the initial boundary area to obtain the modified boundary area specifically includes the following steps: and taking the second preset area as a boundary area to be moved, and moving the boundary area to be moved according to a preset rule so as to form a correction boundary area.
Preferably, moving the boundary region to be moved according to a preset rule to obtain a mask optimization correction boundary region includes:
selecting a vertex of the initial boundary area as an origin of a coordinate axis, and two edges connected with the vertex as an x axis and a y axis of the coordinate axis; and defining the side length of the block as a, the side length of the initial boundary region as N, the side length of the boundary region to be moved as a + N, and moving the boundary region to be moved by a preset distance along a straight line y = x towards the third quadrant direction of the coordinate axis to obtain a mask optimization correction boundary region.
Preferably, optimizing all hierarchical tiles within the initial bounding region comprises:
breaking the mask graph in the block to obtain a line segment;
placing initial evaluation points on the line segments, simulating a mask pattern to form an actual mask image and an ideal mask image, and correlating the projections of the initial evaluation points on the contours of the actual mask image and the ideal mask image to obtain edge placement errors of the evaluation points;
the mask pattern within the block expansion boundary is optimized based on the edge placement error of the evaluation point and a preset evaluation function.
Preferably, the preset evaluation function is:
wherein, the EPE is the edge placement error of the evaluation point; x is an evaluation point at a certain position, W x Is the weight of the location evaluation point.
Preferably, optimizing all blocks in the initial bounding region according to a preset order comprises:
optimizing the mask pattern in the boundary line of the low-level blocks and storing the optimization result;
and loading the optimization result in the boundary line of the low-level blocks, optimizing the mask pattern in the boundary line of the high-level blocks and storing the optimization result.
In order to solve the above technical problems, the present invention provides another technical solution as follows: an apparatus for applying the method for improving the convergence of mask pattern optimization described above, the apparatus comprising:
an identification module: the method is used for identifying the mask pattern in the mask layout;
an optimization module: the method is used for calculating and optimizing a mask pattern in the mask layout;
an output module: for outputting the final optimized mask layout.
In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer device applied to the method for improving the mask pattern optimization convergence comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the method for improving the mask pattern optimization convergence.
Compared with the prior art, the method, the device and the computer equipment for improving the optimized convergence of the mask pattern have the following beneficial effects:
1. the method for improving the optimized convergence of the mask graph, which is provided by the embodiment of the invention, is applied to an initial mask layout and is characterized in that: the method comprises the following steps: selecting a first preset area, wherein the first preset area comprises an initial mask layout, and defining the first preset area as an initial boundary area; dividing the initial boundary area into blocks with preset sizes according to a preset rule, optimizing all the blocks in the initial boundary area according to a preset sequence and obtaining a first optimization result; adding a second preset area outside the initial boundary area to obtain a corrected boundary area, wherein the area of the corrected boundary area, which is overlapped with the initial boundary area, is larger than that of the initial boundary area; dividing the correction boundary area into blocks with the same preset size according to the same preset rule; optimizing and correcting all blocks in the boundary region according to a preset sequence and obtaining a second optimization result; and combining the first optimization result and the second optimization result to obtain the final optimized mask layout. The mask patterns in all the blocks in the initial boundary area are optimized, a second preset area is added to the initial boundary area to obtain a boundary area to be moved, the boundary area to be moved is moved to obtain a corrected boundary area, the mask patterns near the block boundary of the initial boundary area are moved to the blocks divided by the corrected boundary area, the mask patterns near the block boundary of the initial boundary area are optimized after the blocks in the corrected boundary area are optimized, and the mask patterns with good convergence can be obtained by performing optimization twice. The situation that a chip circuit formed on a silicon chip is easy to be short-circuited or broken-circuited after a pattern near the boundary is exposed by a photoetching machine is avoided.
2. According to the embodiment of the invention, the area of the first preset region is larger than or equal to the area of the initial mask layout, so that the mask patterns in the mask layout can be ensured to be positioned in the first preset region, and the mask patterns can be ensured to be optimized.
3. The embodiment of the invention adds a second preset area outside the initial boundary area to obtain the corrected boundary area, and specifically comprises the following steps:
taking the second preset area as a boundary area to be moved, and moving the boundary area to be moved according to a preset rule to form a correction boundary area; moving the boundary area to be moved according to a preset rule to obtain a mask optimization correction boundary area comprises the following steps: selecting a vertex of the initial boundary area as an origin of a coordinate axis, and two edges connected with the vertex as an x axis and a y axis of the coordinate axis; and the side length of the defined block is a, the side length of the initial boundary region is N, the side length of the boundary region to be moved is a + N, and the boundary region to be moved moves a preset distance along the straight line y = x towards the third quadrant direction of the coordinate axis to obtain the mask optimization correction boundary region. After the boundary area to be moved moves for the preset distance, the mask patterns in the block expansion area can be ensured to be positioned in the blocks in the correction boundary area after the boundary moves, and the boundary lines of the blocks in the correction boundary area can be perfectly staggered from the boundary lines of the blocks in the initial boundary area.
4. The embodiment of the invention breaks the mask graph in the block to obtain a line segment;
placing initial evaluation points on the line segments, simulating a mask pattern to form an actual mask image and an ideal mask image, and correlating the projections of the initial evaluation points on the contours of the actual mask image and the ideal mask image to obtain edge placement errors of the evaluation points; the mask pattern within the tile boundary is optimized based on the edge placement error of the evaluation points and a preset evaluation function. Correlating the projections of the initial evaluation points on the contours of the actual mask image and the ideal mask image comprises: and projecting the initial evaluation point of the line segment along the direction vertical to the line segment, wherein the intersection point of the projection and the actual mask image outline is a first evaluation point, the intersection point of the projection and the ideal mask image outline is a second evaluation point, and the offset error of the first evaluation point and the second evaluation point is the edge placement error of the evaluation points. By breaking the mask pattern to set evaluation points on broken line segments, the actual mask image and the ideal mask image can be correlated to obtain edge placement errors for the evaluation points.
5. The embodiment of the invention presets the evaluation function as follows:
wherein, the EPE is the edge placement error of the evaluation point; x is an evaluation point at a certain position, W x Is the weight of the location evaluation point. The mask optimization convergence is evaluated by an evaluation function, and the smaller the value of the evaluation function is, the more the evaluation function is converged, that is, the difference between the actual mask image formed by imaging the mask pattern and the ideal mask image is smaller.
6. The embodiment of the invention optimizes all the grade blocks according to the preset sequence and obtains the optimization results of all the blocks in the initial boundary area, which comprises the following steps: optimizing the mask pattern in the boundary line of the low-level blocks and storing the optimization result; and loading the optimization result in the boundary line of the low-level blocks, optimizing the mask graph in the boundary line of the high-level blocks and storing the optimization result. The problem that the computing power of an optimizer is not enough to support the optimization of the whole mask layout at one time is avoided.
7. The embodiment of the present invention further provides an apparatus, which has the same beneficial effects as the above method for improving the optimized convergence of the mask pattern, and is not described herein again.
8. The embodiment of the present invention further provides a computer device, which has the same beneficial effects as the above method for improving the mask pattern optimization convergence, and is not described herein again.
[ description of the drawings ]
Fig. 1 is a first schematic diagram of a mask layout block of a method for improving mask pattern optimization convergence according to an embodiment of the present invention.
FIG. 2 is an enlarged schematic diagram of an optimized mask pattern according to a method for improving the convergence of mask pattern optimization provided by an embodiment of the present invention.
FIG. 3 is a flowchart illustrating a method for improving mask pattern optimization convergence according to an embodiment of the present invention.
Fig. 4 is a second schematic diagram of mask layout blocks of the method for improving the convergence of mask pattern optimization according to the embodiment of the present invention.
FIG. 5 is a schematic diagram of a process for obtaining a corrected boundary region by a method for improving mask pattern optimization convergence according to an embodiment of the present invention.
FIG. 6 is a flowchart illustrating all blocks in an initial boundary region of an optimization method for improving mask pattern optimization convergence according to an embodiment of the present invention.
FIG. 7 is a schematic diagram of a mask pattern imaging method for improving mask pattern optimization convergence according to an embodiment of the present invention.
FIG. 8 is an enlarged view of a mask pattern image of a method for improving the optimized convergence of the mask pattern according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.
Fig. 10 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
The attached drawings indicate the following:
1. a device; 2. a computer device;
11. an identification module; 12. an optimization module; 13. an output module; 21. a memory; 22. a processor; 23. a computer program.
[ detailed description ] A
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the embodiments provided herein, it should be understood that "B corresponding to a" means that B is associated with a from which B can be determined. It should also be understood, however, that determining B from a does not mean determining B from a alone, but may also be determined from a and/or other information.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also appreciate that the embodiments described in this specification are exemplary and alternative embodiments, and that the acts and modules illustrated are not required to practice the invention.
In various embodiments of the present invention, it should be understood that the sequence numbers of the above-mentioned processes do not imply an inevitable order of execution, and the execution order of the processes should be determined by their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
The flowchart and block diagrams in the figures of the present application illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The photolithography system irradiates the mask plate with light, images the mask pattern on the mask plate to form a mask image, and transfers the pattern on the mask plate to the photoresist coated on the silicon substrate and further to the silicon wafer through the optical imaging system. The pattern transferred onto the photoresist is called an aerial image, AI (AI); the pattern transferred to the silicon wafer is called a resist image, i.e., RI (Re s i stIm ag e). These two images will now be collectively referred to as mask images. Because of the huge computation load of computing lithography, the computing power of the current ED A software and computer server cluster is not enough to support the optimization of the whole chip layout at one time. Therefore, in the mask optimization process, the mask layout is firstly partitioned, then the partitions are optimized in sequence, and finally the optimization results of the partitions are spliced to obtain a complete optimized mask graph.
Mask optimization refers to a process of moving line segments of a mask pattern so that a mask image formed by imaging the moved mask pattern is close to an ideal mask image. However, each block needs to be extended outwards by a certain range during optimization to ensure the accuracy of the calculation result. In order to reduce the computational cost in the optimization process, generally, when each block is optimized, the optimization results in the boundary lines of the blocks are stored, and the optimization results of the mask patterns in the boundaries after the boundary lines of the blocks are expanded are also stored. The optimization sequence of the adjacent blocks is inconsistent, so that the convergence of the optimized result of the mask patterns near the boundary of the adjacent blocks is poor when the adjacent blocks are optimized, namely the difference between the actual mask pattern formed by the optimized mask pattern and the ideal mask pattern is large, and the optimization effect is poor, so that the situation that a chip circuit formed on a silicon wafer after the pattern near the boundary is exposed by a photoetching machine is easy to generate short circuit or open circuit is caused.
Exemplarily, referring to fig. 1 and fig. 2, fig. 1 shows a mask layout block diagram, where L0, L1, L2, and L3 represent different levels of blocks of the mask layout, where original boundary lines are defined between adjacent blocks. It should be understood that, in the vicinity of the original boundary line of the adjacent segment, there is a mask pattern P1, and when the L0 segment is optimized, the original boundary line of L0 expands outward of the segment to form an expanded boundary line (see also the dashed boundary line shown in fig. 1). The area between the L0 block original boundary line and the extended boundary line is defined as an extended area, so that the mask pattern in the L0 block boundary line is optimized, the extended area is also optimized, and the optimization result is stored. However, the expansion area of the L0 block is a part of the original boundary line of the L1 block, the optimization of the L0 block results in that the mask pattern in the expansion area of the L0 block has moved and the movement result is stored, when the L1 block is optimized, the optimization result of the L0 block in the expansion area will have a serious influence on the optimization result of the L1 block, fig. 2 shows an optimization result of the mask patterns near the L1 block and the L0 block, it can be seen that the optimization of the mask patterns of the two mask patterns is not in place after the optimization, which causes poor convergence of the mask patterns, resulting in that the mask image portions imaged by different mask patterns are overlapped, thereby causing a situation that the chip circuit formed on the silicon wafer after the patterns near the boundary of the block are exposed by the lithography machine is easily short-circuited.
Referring to fig. 3, an embodiment of the present invention provides a method for improving optimized convergence of a mask pattern, which is applied to an initial mask layout, and includes the following steps:
s1, selecting a first preset area, wherein the first preset area comprises an initial mask layout, and defining the first preset area as an initial boundary area;
s2, dividing the initial boundary area into blocks with preset sizes according to a preset rule, optimizing all the blocks in the initial boundary area according to a preset sequence and obtaining a first optimization result;
s3, adding a second preset area outside the initial boundary area to obtain a corrected boundary area, wherein the overlapped area of the corrected boundary area and the initial boundary area is larger than that of the initial boundary area; dividing the correction boundary area into blocks with the same preset size according to the same preset rule;
s4, optimizing and correcting all blocks in the boundary area according to a preset sequence and obtaining a second optimization result;
and S5, combining the first optimization result and the second optimization result to obtain a final optimized mask layout.
It can be understood that, in the method for improving the convergence of mask pattern optimization provided by this embodiment, an area overlapping with an initial reticle pattern is selected to be defined as an initial boundary area, the initial boundary area is blocked, and all blocks in the initial boundary area are optimized for the first time, so as to obtain a first optimization result. In the first optimization result, the optimization result near the boundary line of the adjacent blocks has a problem of poor convergence. The corrected boundary area is obtained by adding a second preset area outside the initial boundary area and moving it. It should be understood that during the boundary moving process, the mask patterns are not moved all the time, so that a certain mask pattern is in the area near the original boundary line of the adjacent blocks before moving; after the movement, the mask pattern is positioned in the blocks of the corrected boundary area, and then all the blocks in the corrected boundary area are optimized for the second time to obtain a second optimization result. It should be noted that, after the first optimization result performed in the initial boundary area is obtained, the first optimization result is separately stored, that is, when the mask pattern in the corrected boundary area is optimized, the mask pattern in the corrected boundary area is a mask pattern that does not move, so that the influence of the first optimization result on the second optimization is avoided. Specifically, the mask pattern in the first optimization result near the block boundary has poor convergence, and the mask pattern is located in the block inside the modified boundary area in the second optimization process, so that the mask pattern with poor convergence in the first optimization process is well optimized in the second optimization process, and the convergence is improved. And finally, combining the first optimization result with the second optimization result to obtain the final optimized mask layout.
In the step S1, the area of the first preset region is larger than the area of the initial mask layout, and it should be understood that a preset program is usually adopted for simulation in the optimization process of the mask layout, wherein the preset program is not limited to electronic circuit design and simulation tools such as sp I C E, P S PI C E, EWB, M atl ab, S y stmvi ew or MMI C S AD. The mask layout is arranged in a plane, a region overlapped with the mask layout is selected as a first preset region, and the area of the first preset region is larger than that of the initial mask layout, so that the mask pattern in the mask layout can be optimized.
It should be noted that, in step S3, adding the second preset area outside the initial boundary area to obtain the corrected boundary area specifically includes the following steps: and taking the second preset area as a boundary area to be moved, and moving the boundary area to be moved according to a preset rule so as to form a correction boundary area.
Further, in step S2, dividing the initial mask layout to obtain blocks of a preset size includes: obtaining blocks with preset sizes of array distribution based on a preset proportion, and further optimizing all blocks in the initial boundary area according to a preset sequence comprises the following steps: obtaining blocks of a preset grade according to a preset rule; and optimizing the blocks of the preset grade according to the preset sequence.
The preset rule is as follows:
L＝2×(ro w_i d÷2)+(c o l_id÷2)；
wherein, L is the grade of the block, ro w _ i d is the row number of the block, and c o L _ i d is the column number of the block. Referring to fig. 4, the mask layout is partitioned based on a predetermined ratio, it should be noted that the value of the predetermined ratio is not specifically limited, and is determined according to the actual requirement of the user, that is, the side length of the partition is not specifically limited. Obtaining the blocks distributed in the array after dividing the mask layout, exemplarily naming the number of rows and columns of the blocks distributed in the array from 0 th row to 0 th row, and then obtaining the blocks in the preset level based on the rule. For example, the number of stages of the block of the 0 th row and the 0 th column is L =2 × (0 ÷ 2) + (0 ÷ 2) = L0; the number of stages of the 1 st row and 0 th column block is L =2 × (1 ÷ 2) + (0 ÷ 2) = L2; the number of stages of the 1 st row and 1 st column block is L =2 × (1 ÷ 2) + (1 ÷ 2) = L3. It should be understood that the grade of the blocks is defined based on a preset rule, so that the blocks with low grade are optimized firstly and then the blocks with high grade are optimized in the optimization process of the mask layout, and the problem that the calculation capacity of an optimizer is insufficient to support the optimization of the whole mask layout at one time is solved.
In step S2, the area where the corrected boundary region overlaps the initial boundary region is equal to or larger than the area of the initial boundary region. It should be understood that, in order to enable the area after the boundary is moved to still cover the initial mask layout, the area of the boundary area to be moved formed by the first preset area and the second preset area should be greater than or equal to the area of the initial boundary area. Further, the area of the modified border region, which coincides with the initial border region, should be larger than the area of the initial border region.
Further, a boundary line formed between adjacent blocks in the initial boundary region does not coincide with a boundary line formed between adjacent blocks in the corrected boundary region. It should be understood that, in order to enable the mask pattern in the first optimization result, which is located near the boundary of the adjacent blocks in the initial boundary area, to be located inside the blocks of the modified boundary area after the boundary is moved, the boundary area to be moved is moved according to a preset rule to obtain a mask optimization modified boundary area. The boundary lines formed between the adjacent blocks in the initial boundary region and the boundary lines formed between the adjacent blocks in the corrected boundary region are not coincident, so that the problem that the mask pattern with poor convergence of the first optimization result is still in the vicinity of the boundary lines of the adjacent blocks in the corrected boundary region after the boundary moves is solved. Specifically, referring to fig. 5, the distance difference H between the shifted modified border area line and the original border line is greater than 700nm, and it should be understood that the distance between the original border line and the extended border line is usually 0-700nm when the block is extended, and therefore, in the process of shifting the border, the distance difference H between the outer border line of the shifted modified border area and the outer border line of the original border area is greater than 700nm, which ensures that the mask pattern in the block extension area can be located inside the block in the modified border area after the border is shifted.
Preferably, referring to fig. 5, moving the boundary area to be moved according to the preset rule to obtain the mask optimized modified boundary area includes:
selecting a vertex of an initial boundary region (a solid line region shown in fig. 5) as an origin of a coordinate axis, and two edges connected with the vertex as an x axis and a y axis of the coordinate axis; the side length of the defined block is a, the side length of the initial boundary region is N, the side length of the boundary region to be moved is a + N, and the boundary region to be moved (the long dashed line region shown in fig. 5) is moved by a preset distance in the direction of the third quadrant of the coordinate axis along the straight line y = x to obtain a mask optimization correction boundary region (the short dashed line region shown in fig. 5). It should be understood that the vertex of the initial bounding region is defined in the default procedure as the origin O of the coordinate axis, and the two edges connecting the vertex are the x-axis and the y-axis of the coordinate axis. When the L0 segment is extended, the original boundary line is not extended to the outside of the original boundary region, and therefore, when the L0 segment is moved, the convergence of the optimization result of the segment in the vicinity of the original boundary line is excellent. Therefore, when the boundary is moved, the boundary area to be moved is preferably moved along the straight line y = x in the direction of the third quadrant of the coordinate axis, so that the boundary line between the adjacent blocks in the corrected boundary area after the movement can be perfectly deviated from the boundary line between the adjacent blocks in the initial boundary area.Specifically, the preset distance K satisfies
It should be understood that after the boundary area to be moved is moved by the preset distance, it is ensured that the mask patterns in the block expansion area can be positioned inside the blocks in the correction boundary area after the boundary is moved, and the boundary lines of the blocks in the correction boundary area can be perfectly staggered from the boundary lines of the blocks in the initial boundary area. It should be noted that the preset distance is only one possible implementation, and when the modified boundary area is large enough, the distance that the boundary area to be moved can move along the straight line y = x is much larger than the distance that the boundary area to be moved can move along the straight line y = x
At this time, the preset distance K refers to a distance from a vertex of the correction boundary region, which is closest to the coordinate axis origin O in the third quadrant of the coordinate axis, to the coordinate axis origin O, to the vertex of the intersection of the straight line y = x.
Further, referring to fig. 3 and fig. 6, in the step S2, optimizing all the hierarchical blocks in the initial boundary area includes:
s21, breaking the mask graph in the block to obtain a line segment;
s22, placing initial evaluation points on the line segments, simulating a mask pattern to form an actual mask image and an ideal mask image, and associating the projections of the initial evaluation points on the contours of the actual mask image and the ideal mask image to obtain edge placement errors of the evaluation points;
and S23, optimizing the mask pattern in the block expansion boundary based on the edge placement error of the evaluation point and a preset evaluation function.
Referring to FIG. 7, a mask pattern P1 is shown broken into line segments. By breaking the edge of the mask pattern into line segments, when the mask pattern is optimized, the edge placement error between the actual mask image and the ideal mask image is obtained through calculation, so that the deviation value of the line segments is obtained and the line segments are corrected, and the optimization accuracy of the mask pattern is improved. It should be noted that the specific break points of the mask pattern P1 are set according to the complexity of the mask pattern P1, which is only one possible implementation manner provided in this embodiment, and the specific break positions of the mask pattern are not limited.
In the above step S22, the associating the projection of the initial evaluation point on the outline of the actual mask image and the outline of the ideal mask image includes: and projecting the initial evaluation point of the line segment along the direction vertical to the line segment, wherein the intersection point of the projection and the outline of the ideal mask image is a first evaluation point, the intersection point of the projection and the outline of the actual mask image is a second evaluation point, and the offset error of the first evaluation point and the second evaluation point is the edge placement error of the evaluation point.
It is understood that the initial evaluation points of the line segments are projected in a direction perpendicular to the line segments, and if the projection does not have an intersection with the ideal mask image contour and the actual mask image contour or an intersection with only one of them, the initial evaluation points are discarded. If the projection has an intersection with both the ideal mask image contour and the actual mask image contour, the first evaluation point and the second evaluation point are correlated. Referring to fig. 8, the initial evaluation point D1 in fig. 8 is projected in a direction perpendicular to the line segment, the intersection point with the ideal mask pattern profile P2 is the first evaluation point D2, the intersection point with the actual mask pattern profile P3 is the second evaluation point D3, and the offset error between the first evaluation point D2 and the second evaluation point D3 is the edge placement error (EP E) of the evaluation points. In this embodiment, the edge placement error (EP E) of the initial evaluation point can be obtained by associating the offset error between the first evaluation point D2 and the second evaluation point D3, which is simple and convenient. It should be appreciated that the smaller the edge placement error (EP E), the closer the ideal mask pattern profile P2 is expressed to the actual mask image profile P3.
In the step S4, the optimizing the mask pattern within the block expansion boundary includes: and optimizing the mask pattern in the original boundary of the block based on the edge placement error of the evaluation point and a preset evaluation function.
Specifically, the preset evaluation function is:
wherein, the EPE is the edge placement error of the evaluation point; x is an evaluation point at a position within the boundary, W x Is the weight of the location evaluation point. It should be understood that when an edge placement error (EP E) is incorporated, the smaller the value of its merit function, the more convergent the merit function is, i.e., the less different the actual mask image formed by imaging the mask pattern from the ideal mask image.
Illustratively, when optimizing the L0 patch, the original boundary line of the L0 patch expands to form an expanded boundary line. The value of the evaluation function can be calculated and obtained by obtaining the edge placement error of the line segment formed by the mask graph in the region of the L0 block expanded boundary line, the value of the evaluation function is converged by continuous iteration, namely the value of the evaluation function tends to 0, the offset of the line segment can be obtained, and the line segment in the original boundary line is optimized based on the offset. It will be appreciated that the optimization results have good convergence by evaluating the mask pattern inside the functional block, while the convergence of the function at the boundary of adjacent blocks is poor. Further, after the optimization is finished, all the grade blocks in the initial boundary area are stored to obtain a first optimization result.
Further, optimizing all blocks in the initial boundary region according to a preset order comprises:
optimizing a mask pattern in a boundary line of the low-level block and storing an optimization result;
and loading the optimization result in the boundary line of the low-level blocks, optimizing the mask pattern in the boundary line of the high-level blocks and storing the optimization result.
It should be appreciated that with continued reference to FIG. 1, in optimizing the partitions of the initial bounding region, the lower level partitions are optimized prior to the higher level partitions in the sequential order of L0, L1, L2, and L3 partitions. Illustratively, in the optimization, in order to reduce the computational cost, the mask patterns in the boundary of the L0 segment are optimized and stored, because the first optimization result obtained by optimizing the mask patterns near the boundary of the adjacent segment by the original boundary has no influence on the second optimization result of the modified boundary region, when the L0 segment is optimized, only the optimization result in the original boundary is stored, and the region between the expanded boundary and the original boundary is not considered. And then, when the L1 block is optimized, only the optimization result in the original boundary line of the L0 block needs to be loaded, and then the mask graph in the original boundary line of the L1 block is optimized and the optimization result is stored. And then optimizing the L2 blocks, only loading the optimization result of the L0 blocks, optimizing the mask graph in the original boundary line of the L2 blocks and storing the optimization result. And finally, optimizing the L3 block, and optimizing the mask pattern in the L3 only by loading the optimization results of the L0, the L1 and the L2. When the high-level block boundary is optimized, only the optimization result stored by the low-level boundary needs to be loaded, and then the unloaded area in the preset range near the high-level boundary is optimized and stored, so that the calculation cost is greatly reduced.
It should be noted that, in the step S3, the second preset area is divided into blocks with preset sizes by the same method as that in the step S2, so as to obtain blocks with preset sizes distributed in an array, where the block size of the second preset area is the same as that of the first preset area. The method for dividing the second preset area further comprises the following steps: combining the blocks of the first preset area and the blocks of the second preset area, and obtaining the blocks of the preset level according to the preset rules for the combined blocks, illustratively, the blocks in the 0 th row and the 0 th column in the initial boundary area are in L0 level, and in the modified boundary area, some positions of the blocks are changed into the 0 th row and the 0 th column in the 1 st row, and the levels of the blocks should be named as L2 level according to the preset rules, so after the modified boundary area is formed, the blocks in the modified boundary area need to be subjected to level calibration again, and then all the blocks in the modified boundary area need to be optimized by adopting the same optimization method. It should be understood that the function convergence of the first optimization result obtained in step S2 at the boundary of the adjacent blocks is poor, after the movement, the mask pattern at the boundary of the adjacent blocks in the original boundary is located inside the blocks in the modified boundary region, after the second optimization, the result optimized by the mask pattern has good convergence, and finally, the first optimization result and the second optimization result are combined to obtain the optimization result of the final mask layout, so as to complete the optimization of the mask layout.
Illustratively, to facilitate understanding of the above-described method for improving the convergence of mask pattern optimization, the following specific embodiments are provided:
step 1: an initial mask layout is provided, the layout including at least one more polygon, which refers to a pattern having square edges.
And 2, step: selecting a 4000um x 4000um area overlapped with the initial mask plate image as a mask optimization initial boundary area, taking the vertex of the initial boundary area as a coordinate axis origin point, and taking two edges of the initial boundary area passing through the origin point as a coordinate axis x axis and a coordinate axis y axis, and setting the coordinate boundary range of the initial boundary area as [0, 4000, 4000].
And step 3: the side length of each square block is set to be 20um, and the original boundary is divided into 200 rows and 200 columns of square block combinations.
And 4, step 4: and calculating the corresponding grade of each square block according to a preset rule.
And 5: and optimizing all the blocks from the low level to the high level according to the result of the level calibration to obtain a first optimization result.
Step 6: adding an area on the range of the original boundary to define the boundary area to be moved, wherein the coordinate boundary range of the boundary area to be moved is [0, 4020]Moving in the direction of the third quadrant of the coordinate axis y = x
The coordinate boundary range of the correction boundary area is [ -10,4010]。
And 7: the side length of each square block is set to be 20um, and the correction boundary area is divided into 201 rows and x 201 columns of square block combinations. And repeating the processes of the step 4 and the step 5, and optimizing all the blocks in the corrected boundary area to obtain a second optimization result.
And 8: and outputting the first optimization result and the second optimization result, and combining the first optimization result and the second optimization result to obtain the final optimization result of the mask layout to complete the optimization of the mask layout.
The embodiment of the present invention further provides an apparatus 1, which is applied to the method for improving mask pattern optimization convergence, and is characterized in that: the device 1 comprises:
the identification module 11: the method is used for identifying the mask pattern in the mask layout;
the optimization module 12: the method is used for calculating and optimizing the mask pattern in the mask layout;
an output module 13: for outputting the final optimized mask layout.
The apparatus 1 provided in the embodiment of the present invention has the same beneficial effects as the above method for improving the optimized convergence of the mask pattern, and is not described herein again.
The embodiment of the present invention further provides a computer device 2, which is applied to the method for improving the mask pattern optimization convergence, and is characterized in that: comprising a memory 21, a processor 22 and a computer program 23 stored on the memory 21, wherein the processor 22 executes the computer program 23 to realize the method for improving the convergence of mask pattern optimization.
The computer device 2 provided in the embodiment of the present invention has the same beneficial effects as the above method for improving the optimized convergence of the mask pattern, and details are not described herein.
Compared with the prior art, the method, the device and the computer equipment for improving the optimized convergence of the mask pattern have the following beneficial effects:
1. the method for improving the optimized convergence of the mask graph, which is provided by the embodiment of the invention, is applied to an initial mask layout and is characterized in that: the method comprises the following steps: selecting a first preset area, wherein the first preset area comprises an initial mask layout, and defining the first preset area as an initial boundary area; dividing the initial boundary area into blocks with preset sizes according to a preset rule, optimizing all the blocks in the initial boundary area according to a preset sequence and obtaining a first optimization result; adding a second preset area outside the initial boundary area to obtain a corrected boundary area, wherein the area of the corrected boundary area, which is overlapped with the initial boundary area, is larger than that of the initial boundary area; dividing the correction boundary area into blocks with the same preset size according to the same preset rule; optimizing and correcting all the blocks in the boundary area according to a preset sequence and obtaining a second optimization result; and combining the first optimization result and the second optimization result to obtain a final optimized mask layout. The mask patterns in all the blocks in the initial boundary area are optimized, a second preset area is added to the initial boundary area to obtain a boundary area to be moved, the boundary area to be moved is moved to obtain a corrected boundary area, the mask patterns near the block boundary of the initial boundary area are moved to the blocks divided by the corrected boundary area, after the blocks in the corrected boundary area are optimized, the mask patterns near the block boundary of the initial boundary area are optimized, and the mask patterns with good convergence can be obtained by performing optimization twice. The situation that a chip circuit formed on a silicon chip is easy to be short-circuited or broken-circuited after a pattern near the boundary is exposed by a photoetching machine is avoided.
2. According to the embodiment of the invention, the area of the first preset region is larger than or equal to the area of the initial mask layout, so that the mask patterns in the mask layout can be ensured to be positioned in the first preset region, and the mask patterns can be ensured to be optimized.
3. The embodiment of the invention adds a second preset area outside the initial boundary area to obtain the corrected boundary area, and specifically comprises the following steps: taking the second preset area as a boundary area to be moved, and moving the boundary area to be moved according to a preset rule to form a correction boundary area; moving the boundary area to be moved according to a preset rule to obtain a mask optimization correction boundary area comprises the following steps: selecting a vertex of the initial boundary area as an origin of a coordinate axis, and two edges connected with the vertex as an x axis and a y axis of the coordinate axis; and the side length of the defined block is a, the side length of the initial boundary region is N, the side length of the boundary region to be moved is a + N, and the boundary region to be moved moves towards the third quadrant direction of the coordinate axis by a preset distance along the straight line y = x to obtain the mask optimization correction boundary region. After the boundary area to be moved moves for the preset distance, the mask patterns in the block expansion area can be ensured to be positioned in the blocks in the correction boundary area after the boundary moves, and the boundary lines of the blocks in the correction boundary area can be perfectly staggered from the boundary lines of the blocks in the initial boundary area.
4. The embodiment of the invention breaks the mask graph in the block to obtain a line segment;
placing initial evaluation points on the line segments, simulating a mask pattern to form an actual mask image and an ideal mask image, and correlating the projections of the initial evaluation points on the contours of the actual mask image and the ideal mask image to obtain edge placement errors of the evaluation points; the mask pattern within the tile boundary is optimized based on the edge placement error of the evaluation points and a preset evaluation function. Correlating the projections of the initial evaluation points on the contours of the actual mask image and the ideal mask image comprises: and projecting the initial evaluation point of the line segment along the direction vertical to the line segment, wherein the intersection point of the projection and the actual mask image outline is a first evaluation point, the intersection point of the projection and the ideal mask image outline is a second evaluation point, and the offset error of the first evaluation point and the second evaluation point is the edge placement error of the evaluation points. By breaking the mask pattern to set evaluation points on broken line segments, the actual mask image and the ideal mask image can be correlated to obtain edge placement errors for the evaluation points.
5. The embodiment of the invention presets the evaluation function as follows:
wherein, the EPE is the edge placement error of the evaluation point; x is an evaluation point at a certain position, W x Is the weight of the location evaluation point. The mask optimization convergence is evaluated through an evaluation function, and the smaller the value of the evaluation function is, the more the evaluation function converges, namely, the difference between the actual mask image formed by the mask pattern imaging and the ideal mask image is smaller.
6. The embodiment of the invention optimizes all the grade blocks according to the preset sequence and obtains the optimization results of all the blocks in the initial boundary area, which comprises the following steps: optimizing a mask pattern in a boundary line of the low-level block and storing an optimization result; and loading the optimization result in the boundary line of the low-level block, optimizing the mask graph in the boundary line of the high-level block and storing the optimization result. The problem that the computing power of an optimizer is not enough to support the optimization of the whole mask layout at one time is avoided.
7. The embodiment of the present invention further provides an apparatus, which has the same beneficial effects as the above method for improving the optimized convergence of the mask pattern, and is not described herein again.
8. The embodiment of the present invention further provides a computer device, which has the same beneficial effects as the above method for improving the mask pattern optimization convergence, and details are not repeated herein.
The method, the apparatus and the computer device for improving the convergence of mask pattern optimization disclosed in the embodiments of the present invention are described in detail above, and specific embodiments are applied in the present disclosure to explain the principles and embodiments of the present invention, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for the person skilled in the art, based on the idea of the present invention, there may be variations in the embodiments and applications, and in view of the above, the content of the present description should not be construed as a limitation to the present invention, and any modifications, equivalent substitutions and improvements made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for improving the optimized convergence of a mask pattern is applied to an initial mask layout and is characterized in that: the method comprises the following steps:
selecting a first preset area, wherein the first preset area comprises an initial mask layout, and defining the first preset area as an initial boundary area;
dividing the initial boundary area into blocks with preset sizes according to a preset rule, optimizing all the blocks in the initial boundary area according to a preset sequence and obtaining a first optimization result;
adding a second preset area outside the initial boundary area to obtain a corrected boundary area, wherein the area of the corrected boundary area, which is overlapped with the initial boundary area, is larger than that of the initial boundary area; dividing the correction boundary area into blocks with the same preset size according to the same preset rule;
optimizing and correcting all the blocks in the boundary area according to a preset sequence and obtaining a second optimization result;
and combining the first optimization result and the second optimization result to obtain a final optimized mask layout.
2. The method of claim 1, wherein the step of optimizing the mask pattern comprises: and the area of the first preset area is larger than or equal to the area of the initial mask layout.
3. The method of claim 1, wherein the step of optimizing the mask pattern comprises: the boundary lines formed between adjacent blocks in the initial boundary region do not coincide with the boundary lines formed between adjacent blocks in the corrected boundary region.
4. The method of claim 1, wherein the step of optimizing the mask pattern comprises: the step of adding a second preset area outside the initial boundary area to obtain a corrected boundary area specifically comprises the following steps: and taking the second preset area as a boundary area to be moved, and moving the boundary area to be moved according to a preset rule so as to form a correction boundary area.
5. The method of claim 4, wherein the step of optimizing the mask pattern comprises: moving the boundary area to be moved according to a preset rule to obtain a corrected boundary area comprises the following steps:
selecting a vertex of the initial boundary area as an origin of a coordinate axis, and two edges connected with the vertex as an x axis and a y axis of the coordinate axis; and defining the side length of the block as a, defining the side length of the initial boundary region as N, defining the side length of the boundary region to be moved as a + N, and moving the boundary region to be moved by a preset distance towards the third quadrant direction of the coordinate axis along the straight line y = x to obtain a corrected boundary region.
6. The method for improving mask pattern optimization convergence according to claim 1, wherein: optimizing all hierarchical tiles within the initial bounding region includes:
breaking the mask graph in the blocks to obtain line segments;
placing initial evaluation points on the line segments, simulating a mask pattern to form an actual mask image and an ideal mask image, and correlating the projections of the initial evaluation points on the contours of the actual mask image and the ideal mask image to obtain edge placement errors of the evaluation points;
the mask pattern within the tile boundaries is optimized based on the edge placement error of the evaluation points and a preset evaluation function.
7. The method of claim 6, wherein the step of optimizing the mask pattern comprises: the preset evaluation function is as follows:
wherein, the EPE is the edge placement error of the evaluation point; x is an evaluation point at a certain position, W x Is the weight of the location evaluation point.
8. The method for improving mask pattern optimization convergence according to claim 1, wherein: optimizing all blocks in the initial boundary region according to a preset sequence comprises the following steps:
optimizing a mask pattern in a boundary line of the low-level block and storing an optimization result;
and loading the optimization result in the boundary line of the low-level block, optimizing the mask graph in the boundary line of the high-level block and storing the optimization result.
9. An apparatus for use in a method for improving the convergence of mask pattern optimization according to any one of claims 1-8, wherein: the device comprises:
an identification module: the method is used for identifying the mask pattern in the mask layout;
an optimization module: the method is used for calculating and optimizing the mask pattern in the mask layout;
an output module: for outputting the final optimized mask layout.
10. A computer apparatus for use in a method for improving mask pattern optimization convergence according to any one of claims 1 to 8, wherein: comprising a memory, a processor and a computer program stored on the memory, the processor executing the computer program to implement the method for improving the optimized convergence of the mask pattern.
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