CN115754682B - Radio frequency chip test system and high-power and low-power path test method - Google Patents
Radio frequency chip test system and high-power and low-power path test method Download PDFInfo
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- CN115754682B CN115754682B CN202211548716.6A CN202211548716A CN115754682B CN 115754682 B CN115754682 B CN 115754682B CN 202211548716 A CN202211548716 A CN 202211548716A CN 115754682 B CN115754682 B CN 115754682B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application discloses a radio frequency chip test system and a high-power and low-power path test method. The system comprises: the signal synthesis module comprises a low-power output path and a high-power output path and is used for synthesizing and outputting low-power signals and high-power signals; the transmitting change-over switch is connected with the signal synthesis module and used for connecting and switching different paths of the tested chip; the receiving change-over switch is connected with different paths of the chip to be tested and is used for switching the paths connected with the receiving analysis module; the receiving and analyzing module comprises a low-power analyzing passage and a high-power analyzing passage, a high-pass filter is arranged on the high-power analyzing passage, and the receiving and analyzing module is used for receiving and analyzing and displaying the data of the tested chip. The application is compatible with low power path test and high power path test, eliminates nonlinear components generated by the electronic switch by adopting a vector synthesis mode through solid state switch switching, and reduces the number of channels so as to reduce the cost and the complexity of the system.
Description
Technical Field
The application relates to the field of chip testing, in particular to a radio frequency chip testing system and a high-power and low-power path testing method.
Background
Testing of radio frequency chips typically includes insertion loss, gain, isolation, harmonics, output power, modulation quality, and the like. The harmonic test of the radio frequency switch requires high-power input signals, the rest requires low-power high-precision signals, and a proper switch array is selected to switch the test channel. Harmonic testing typically employs a signal source, PA, triplexer or filter combination to provide a high purity single tone signal. If the high-purity single-tone signal passes through the electronic switch, nonlinear harmonic wave is generated again, and the test result is affected. The linearity of the mechanical switch is high but the switching speed is slow, the test of the mass production chip switches millions of times every day, and the service life of the mechanical switch cannot be tested in such high intensity. Testing time is wasted if the high and low power is tested separately, increasing the cost of testing. If the public channel is multiplexed without using a switch network, the multichannel tester is high in price and huge in volume.
Therefore, it is necessary to develop a system for testing a radio frequency chip and a method for testing high and low power paths based on vector synthesis.
The information disclosed in the background section of the application is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The application provides a radio frequency chip test system and a high-power and low-power path test method. The application integrates high-power harmonic test and broadband low-power insertion loss, gain, isolation, modulation quality and other tests, and is compatible with low-power access test and high-power access test, thereby meeting most of test requirements. Aiming at multi-channel test, electronic switch switching is adopted, nonlinear components generated by the electronic switch are eliminated by adopting a vector synthesis mode, the number of channels is reduced, the cost and the system complexity are reduced, and the problem that a solid-state switch cannot be used is effectively solved. The device can be matched with a solid-state switch switching module and a solid-state switch channel to meet various testing requirements, and has higher flexibility.
In a first aspect, an embodiment of the present disclosure provides a radio frequency chip testing system, including:
the signal synthesis module comprises a low-power output channel and a high-power output channel, a high-power adjusting unit is arranged on the high-power output channel, and the signal synthesis module is used for synthesizing and outputting low-power signals and high-power signals;
the transmitting change-over switch is connected with the signal synthesis module and used for connecting and switching different paths of the tested chip;
a receiving change-over switch is connected with different paths of the tested chip and is used for switching the paths connected with the receiving analysis module;
the receiving and analyzing module comprises a low-power analyzing passage and a high-power analyzing passage, a high-pass filter is arranged on the high-power analyzing passage, and the receiving and analyzing module is used for receiving the data of the tested chip for analysis and display.
Preferably, the signal synthesis module includes:
the signal source is connected to the input end of the first switch and is used for outputting signals;
the first output end of the first switch is connected with the first input end of the second switch to form the low-power output path;
the second output end of the first switch is connected with the second input end of the second switch through the high-power adjusting unit to form the high-power output path;
and the output end of the second switch is connected with the emission change-over switch.
Preferably, the high power conditioning unit comprises a high power amplifier and a triplexer, wherein,
one end of the high-power amplifier is connected with the second output end of the first switch, the other end of the high-power amplifier is connected with the LOW port of the triplexer, and the output port of the triplexer is connected with the second input end of the second switch;
the device comprises a triplexer, a harmonic generation unit, a DAC and a local oscillator source, wherein the midport and the HIGH port of the triplexer are respectively connected with the harmonic generation unit, the harmonic generation unit comprises an I/Q modulator, the DAC and the local oscillator source, the local oscillator source is connected with the midport or the HIGH port through the I/Q modulator, and the DAC is connected with the I/Q modulator.
Preferably, each input terminal of the receiving switch is connected to an attenuator, and the attenuator is used for attenuating the high-power signal, so as to reduce the harmonic level generated by the receiving switch.
Preferably, the reception analysis module includes:
the input end of the third switch is connected with the output end of the receiving change-over switch, and the first output end of the third switch is connected with the first input end of the fourth switch to form the low-power analysis path;
the second output end of the third switch is connected with the second input end of the fourth switch through the high-pass filter to form the high-power analysis path;
the output end of the fourth switch is connected with a frequency spectrograph, and the frequency spectrograph is used for receiving the data of the tested chip for analysis and display.
Preferably, the receive analysis module further comprises a directional coupler,
the directional coupler is arranged between the transmitting change-over switch and the tested chip and comprises a plurality of groups of forward ports and reflecting ports,
the multiple forward ports are connected with multiple input ends of a fifth switch, the output end of the fifth switch is connected with the third input end of the fourth switch, the multiple reflection ports are connected with multiple input ends of a sixth switch, and the output end of the sixth switch is connected with the fourth input end of the fourth switch.
Preferably, the switches are all solid state switches.
In a second aspect, an embodiment of the present disclosure further provides a high-power path testing method, including:
outputting a high power signal through the high power output path;
and the high-power signal passes through the tested chip and carries out high-power channel test on the tested chip through the high-power analysis channel.
Preferably, before the high-power path test is performed on the tested chip through the high-power analysis path, the method further comprises:
signal synthesis calibration is carried out through a high-power adjusting unit;
performing transmit power calibration based on a difference between a reflective port and a forward port of the directional coupler;
and recording the insertion loss of the harmonic receiving path, and calibrating the receiving path.
Preferably, the high power path test is performed on the tested chip through the high power analysis path, including:
measuring signals of a forward port and a reflection port of the directional coupler on harmonic frequency to obtain directional data of the directional coupler;
according to the difference data obtained by the transmitting power calibration, the signal output power is adjusted to enable the transmitting signal to reach the expected power;
detecting vector signals of a forward port and a reflecting port of the directional coupler;
calculating harmonic power of the forward port according to the calibrated directivity data, obtaining a DAC code value through interpolation calculation, eliminating harmonic signals and obtaining single-tone signals;
recording the harmonic power of the receiving path, and compensating the insertion loss of the receiving path to obtain the actual value of the harmonic.
Preferably, the signal synthesis calibration by the high power conditioning unit comprises:
respectively adjusting intermediate frequency voltage DAC of the I/Q modulator, and combining each group of code values of the DAC to synthesize a vector signal;
detecting the vector signal through a forward port of the directional coupler to obtain vector signal data of the I/Q modulator;
the combination of code values is traversed in steps of DAC code values and the resulting vector signal data is recorded.
In a third aspect, embodiments of the present disclosure further provide a low power path testing method, including:
outputting a low power signal through the low power output path;
and the low-power signal passes through the chip to be tested, and the low-power analysis path is used for carrying out low-power path test on the chip to be tested.
Preferably, the transmitting power calibration is performed by recording the difference between the output port and the forward port of the directional coupler;
recording insertion loss of each low-power receiving path, and calibrating the low-power receiving path;
and performing low-power path test of the tested chip through a radio frequency chip test system.
The beneficial effects are that:
1. the application realizes high-power harmonic test, low-power insertion loss, harmonic, isolation, gain, EVM, ACPR and other tests, covers most of the radio frequency chip test functions, solves the problem that high-power and low-power access tests cannot be compatible, and improves the test efficiency and the tester utilization rate.
2. The source end adopts a directional coupler to detect the transmitting power in real time, thereby ensuring the accuracy of the transmitting power and eliminating mismatch errors caused by mismatch of source end impedance and DUT impedance. The receiving end adopts an attenuator to improve the impedance, provides the input impedance of 50 ohms of broadband, and improves the power precision. The real-time dynamic synthesis of system harmonics provides adequate signal-to-noise ratio for DUT harmonic testing.
3. The multi-path test system generally adopts a switch to switch the test channel, has low mechanical switch speed and short service life, and is not suitable for mass production test of chips. Solid state switches also cannot be used in harmonic testing systems for switches because of the characteristic that their high power inputs excite harmonics. Aiming at the multi-path test requirement of the chip, the application adopts a vector synthesis mode, effectively solves the harmonic problem of the solid-state switch, faces various test requirements, can flexibly match the solid-state switch to switch modules and paths, multiplexes radio frequency paths, thereby saving the cost, and is compatible with high power and low power, thereby improving the test efficiency.
The method and apparatus of the present application have other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the present application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 illustrates a block diagram of a radio frequency chip testing system according to one embodiment of the application.
FIG. 2 shows a flow chart of the steps of a high power path test method according to one embodiment of the application.
FIG. 3 shows a flow chart of the steps of a low power path test method according to one embodiment of the application.
Reference numerals illustrate:
100. a signal synthesis module; 101. a signal source; 102. a first switch; 103. a second switch; 104. a high power amplifier; 105. a DAC; 106. a DAC; 107. the vibration source; 108. the vibration source; 109. an I/Q modulator; 110. an I/Q modulator; 111. a triplexer; 200. a transmitting change-over switch; 300. receiving a change-over switch; 301. an attenuator; 302. an attenuator; 303. an attenuator; 304. an attenuator; 400. a receiving and analyzing module; 401. a third switch; 402. a high pass filter; 403. a fourth switch; 404. a fifth switch; 405. a sixth switch; 406. a spectrometer; 407. a directional coupler.
Detailed Description
Preferred embodiments of the present application will be described in more detail below. While the preferred embodiments of the present application are described below, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein.
In order to facilitate understanding of the solution and the effects of the embodiments of the present application, three specific application examples are given below. It will be understood by those of ordinary skill in the art that the examples are for ease of understanding only and that any particular details thereof are not intended to limit the present application in any way.
Example 1
A radio frequency chip testing system, comprising:
the signal synthesis module comprises a low-power output channel and a high-power output channel, a high-power adjusting unit is arranged on the high-power output channel, and the signal synthesis module is used for synthesizing and outputting low-power signals and high-power signals;
the transmitting change-over switch is connected with the signal synthesis module and used for connecting and switching different paths of the tested chip;
the receiving change-over switch is connected with different paths of the chip to be tested and is used for switching the paths connected with the receiving analysis module;
the receiving and analyzing module comprises a low-power analyzing passage and a high-power analyzing passage, a high-pass filter is arranged on the high-power analyzing passage, and the receiving and analyzing module is used for receiving and analyzing and displaying the data of the tested chip.
In one example, the signal synthesis module includes:
the signal source is connected to the input end of the first switch and is used for outputting signals;
the first output end of the first switch is connected with the first input end of the second switch to form a low-power output path;
the second output end of the first switch is connected with the second input end of the second switch through the high-power adjusting unit to form a high-power output path;
the output end of the second switch is connected with the emission change-over switch.
In one example, the high power conditioning unit includes a high power amplifier and a triplexer, wherein,
one end of the high-power amplifier is connected with the second output end of the first switch, the other end of the high-power amplifier is connected with the LOW port of the triplexer, and the output port of the triplexer is connected with the second input end of the second switch;
the MID port and the HIGH port of the triplexer are respectively connected with a harmonic generation unit, wherein the harmonic generation unit comprises an I/Q modulator, a DAC and a local oscillator source, the local oscillator source is connected with the MID port or the HIGH port through the I/Q modulator, and the DAC is connected with the I/Q modulator.
In one example, each input of the receive switch is coupled to an attenuator that attenuates the high power signal to reduce the level of harmonics produced by the receive switch.
In one example, the receive analysis module includes:
the input end of the third switch is connected with the output end of the receiving change-over switch, and the first output end of the third switch is connected with the first input end of the fourth switch to form a low-power analysis path;
the second output end of the third switch is connected with the second input end of the fourth switch through a high-pass filter to form a high-power analysis path;
the output end of the fourth switch is connected with a spectrometer, and the spectrometer is used for receiving the data of the tested chip for analysis and display.
In one example, the receive analysis module further includes a directional coupler,
the directional coupler is arranged between the transmitting change-over switch and the chip to be tested and comprises a plurality of groups of forward ports and reflecting ports,
the multiple forward ports are connected with multiple input ends of a fifth switch, the output end of the fifth switch is connected with the third input end of a fourth switch, the multiple reflection ports are connected with multiple input ends of a sixth switch, and the output end of the sixth switch is connected with the fourth input end of the fourth switch.
In one example, the switches are all solid state switches.
Fig. 1 illustrates a block diagram of a radio frequency chip testing system according to one embodiment of the application.
Specifically, as shown in fig. 1, the radio frequency chip test system includes:
the signal synthesis module 100, configured to synthesize and output low power and high power signals, includes:
the signal source 101 is connected to an input end of the first switch 102 and is used for outputting a signal; a first output terminal of the first switch 102 is connected to a first input terminal of the second switch 103, forming a low-power output path, and providing a source signal for testing such as insertion loss, isolation, gain, output power, ACPR, EVM, etc.; the second output end of the first switch 102 is connected to the second input end of the second switch 103 through a high-power adjusting unit to form a high-power output path, which is mainly used for harmonic testing; the output of the second switch 103 is connected to the transmit switch 200.
The HIGH-power adjusting unit comprises a HIGH-power amplifier 104 and a triplexer 111, the triplexer 111 can filter nonlinear harmonic waves generated by the PA while playing a role of combining, and meanwhile, MID and HIGH ports of the triplexer 111 can absorb harmonic waves generated by a DUT (chip) to be measured, so that measurement accuracy is ensured. One end of the high-power amplifier 104 is connected to the second output end of the first switch 102, the other end is connected to the LOW port of the triplexer 111, and the output port of the triplexer 111 is connected to the second input end of the second switch 103; the MID port and the HIGH port of the triplexer 111 are respectively connected with a harmonic generation unit, wherein the harmonic generation unit comprises I/Q modulators 109-110, DACs 105-106 and local oscillation sources 107-108, the local oscillation sources 107-108 are connected with the MID port or the HIGH port through the I/Q modulators 109-110, and the DACs 105-106 are connected with the I/Q modulators 109-110. The vibration sources 107-108 adopt 10MHz reference frequency signals of the signal source 101 to generate second and third harmonic waves which are phase-locked with SG for synthesis. The triplexer 111 is not a broadband device, other modules can be compatible with all test frequency bands, and a solid-state switch can be used for switching different triplexer to realize test requirements of different frequency bands.
Because the transmitting path is multiplexed, the broadband high-power PA and the triplexer 111 are multiplexed, the cost can be greatly reduced, and the volume can be reduced. Is flexibly configurable for different requirements. The solid state switch can also be used to switch different triplexers 111 to meet the test requirements of each frequency band.
The transmitting change-over switch 200 is connected with the signal synthesis module 100 and is used for connecting and switching different test paths of the tested chip; the SP4T, SP8T, SP T switch can be flexibly selected, 4, 8 and 16 channel output is realized, and various test requirements are met. The mechanical switch is limited in switching speed and service life, is not suitable for a mass production chip test system, and can achieve standing waves and isolation comparable to those of the mechanical switch in a mode of combining a broadband solid-state switch.
The receiving change-over switch 300 is connected with different paths of the chip to be tested and is switched to be connected with the path of the receiving analysis module 400; the SP4T, SP8T, SP T switch can be flexibly selected, and 4, 8 and 16 path input is realized. Unlike the transmit switch, attenuators 301-304 are added to each input port in order to reduce the rf power into the switch 300, thereby reducing the harmonic level generated by the switch 300 and ensuring the test accuracy.
The reception analysis module 400 includes:
the input end of the third switch 401 is connected with the output end of the receiving switch 300, and the first output end of the third switch 401 is connected with the first input end of the fourth switch 403 to form a low-power analysis path; a second output end of the third switch 401 is connected to a second input end of the fourth switch 403 through a high-pass filter 402, so as to form a high-power analysis path; the output end of the fourth switch 403 is connected to a spectrometer 406, and the spectrometer 406 is used for receiving the data of the tested chip for analysis and display.
The receiving analysis module 400 further includes a directional coupler 407, where the directional coupler 407 is disposed between the transmitting switch 200 and the chip to be tested and includes multiple sets of forward ports and reflective ports, and the multiple forward ports are connected to multiple input ends of the fifth switch 404, and the output ends of the fifth switch 404 are connected to
The third input terminal of the fourth switch 403, the plurality of reflection ports are connected to the plurality of input terminals of the sixth switch 405, and the output terminal of the sixth switch 405 is connected to the fourth input terminal of the fourth switch 403.
All the switches are solid-state switches, and nonlinear harmonic waves can be generated when the solid-state switches pass through high-power signals. The mechanical switch has short service life and low speed, and has great limitation in being incapable of adopting a switch to switch a passage according to test requirements with different requirements; the application adopts a vector synthesis mode to generate high-purity single-tone signals, and generates synthesized signals aiming at different chips in real time, thereby improving the test precision.
The receive analysis module 400 gates the receive signal via switch 401 as a low power, high power path signal and vector composite signal detected by directional coupler 407, respectively. The low power path receives signals such as insertion loss, isolation, gain, EVM, etc., which are input to the spectrometer 406 through the third switch 401 to the fourth switch 403. The high power path signal receives the harmonic signal gated by the third switch 401, the main frequency signal of which is filtered by the high pass filter 402, and the reflected main frequency signal is attenuated again by the attenuators 301-304, so as to avoid affecting the standing wave state of the DUT (chip under test). The directional coupler 407 adopts a bidirectional directional coupler or a cascade of two unidirectional directional couplers to respectively take out the forward transmission signals (PF 11-PF 14) and the reverse reflection signals (PR 11-PR 14) of each path. The forward transmit signal into the DUT is a high power signal output by the transmit path while introducing harmonic signals due to solid state switching nonlinearities. After the DUT inputs the high power signal, it will generate a harmonic reflected signal reflected back to the source and a harmonic forward signal transmitted forward to the receiving path, the two harmonic signals generated by the DUT are close in power. During harmonic testing, forward emission signals need to be synthesized, and harmonic signals introduced by the solid-state switch are eliminated, so that the forward emission harmonic signals entering the DUT are at least 20dB lower than the harmonic signals generated by the DUT, and the testing accuracy is ensured.
Example 2
FIG. 2 shows a flow chart of the steps of a high power path test method according to one embodiment of the application.
As shown in fig. 2, the high power path test method includes:
outputting a high power signal through a high power output path;
the high-power signal passes through the chip to be tested, and the high-power analysis path is used for testing the high-power path of the chip to be tested.
In one example, before the high power path test is performed on the chip under test through the high power analysis path, the method further comprises:
signal synthesis calibration is carried out through a high-power adjusting unit;
performing transmit power calibration based on a difference between a reflective port and a forward port of the directional coupler;
and recording the insertion loss of the harmonic receiving path, and calibrating the receiving path.
In one example, performing high power path testing on a chip under test through a high power analysis path includes:
measuring signals of a forward port and a reflection port of the directional coupler on harmonic frequency to obtain directional data of the directional coupler;
according to the difference data obtained by the transmitting power calibration, the signal output power is adjusted to enable the transmitting signal to reach the expected power;
detecting vector signals of a forward port and a reflecting port of the directional coupler;
calculating harmonic power of a forward port according to the calibrated directivity data, obtaining a DAC code value through interpolation calculation, eliminating harmonic signals, and obtaining a single-tone signal;
recording the harmonic power of the receiving path, and compensating the insertion loss of the receiving path to obtain the actual value of the harmonic.
In one example, signal synthesis calibration by a high power conditioning unit includes:
respectively adjusting intermediate frequency voltage DAC of the I/Q modulator, and combining each group of code values of the DAC to synthesize a vector signal;
detecting the vector signal through a forward port of the directional coupler to obtain vector signal data of the I/Q modulator;
the combination of code values is traversed in steps of DAC code values and the resulting vector signal data is recorded.
Specifically, the signal synthesis module generates a signal with the same amplitude and opposite phase as the system harmonic signal, and in order to reduce the calibration time during the test, pre-calibration is required. The intermediate frequency voltage DAC of the I/Q modulator is adjusted respectively, and each group of code value combinations of the DAC synthesizes a vector signal. The vector signal is detected by adopting a PF1X port of the directional coupler, and enters a spectrometer through a fifth switch to a fourth switch, and finally the vector signal data of the I/Q is obtained. The combinations are stepped through with a certain DAC code value and the resulting vector signal data is recorded.
The high-power transmitting power detection is completed by the PF1X port of the directional coupler, and the difference value between the output port of the directional coupler and the PF1X port is calibrated and recorded.
The calibration harmonic receives the insertion loss of each path and records.
The high power path test is mainly a harmonic test. Firstly, PF1X and PR1X signals of a directional coupler are measured on harmonic frequency to obtain directional data of the directional coupler, and then the output power of a signal source is adjusted according to difference data obtained by transmitting power calibration to enable the transmitting signal to reach expected power. The vector signals of PF1X and PR1X of the directional coupler are then detected. According to the calibrated directivity data, the harmonic power of the system in the PF1X can be accurately calculated. In order to generate signals with the same amplitude and opposite phases with the harmonic power of the system, the signals are required to be synthesized and calibrated, and DAC code values meeting the requirements are obtained through interpolation calculation. And then eliminating harmonic signals by searching and detecting the vicinity of the code value to obtain high-purity single-tone signals. At this time, the harmonic power of the receiving path is recorded, and the insertion loss of the receiving path is compensated to obtain the actual value of the harmonic.
Example 3
FIG. 3 shows a flow chart of the steps of a low power path test method according to one embodiment of the application.
As shown in fig. 3, the low power path test method includes:
outputting a low power signal through a low power output path;
the low-power signal passes through the chip to be tested, and the low-power path test is carried out on the chip to be tested through the low-power analysis path.
In one example, transmit power calibration is performed by recording the difference between the directional coupler output port and the forward port;
recording insertion loss of each low-power receiving path, and calibrating the low-power receiving path;
and performing low-power path test on the tested chip through the radio frequency chip test system.
Specifically, a low power transmit path is output by a signal source via a first switch to a second switch, through a transmit switch and a directional coupler into the DUT, and transmit power detection is provided by the PF1X port of the directional coupler. The difference between the output port of the directional coupler and the port of PF1X is calibrated and recorded.
The low-power receiving path enters the frequency spectrograph through the receiving change-over switch, the third switch and the fourth switch, and the insertion loss of the receiving path is calibrated and recorded.
The low-power path test can realize the functions of insertion loss, gain, isolation, output power, ACPR, OBW, EVM and the like. The output power of the transmitting path is detected by the PF1X port of the directional coupler in real time, the directional coupler can detect the actual power of power transmission, the power mismatch caused by the mismatching of DUT standing waves and source end impedance is eliminated, and the transmitting power precision is improved. The attenuator at the front end of the low-power receiving path improves matching, testing precision is improved, and the power detected by the spectrometer is compensated for the insertion loss of the receiving path to obtain actual power. The remaining ACPR, OBW, EVM etc. tests were analyzed by a spectrometer.
It will be appreciated by persons skilled in the art that the above description of embodiments of the application has been given for the purpose of illustrating the benefits of embodiments of the application only and is not intended to limit embodiments of the application to any examples given.
The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described.
Claims (9)
1. A radio frequency chip test system, comprising:
the signal synthesis module comprises a low-power output channel and a high-power output channel, a high-power adjusting unit is arranged on the high-power output channel, and the signal synthesis module is used for synthesizing and outputting low-power signals and high-power signals;
the transmitting change-over switch is connected with the signal synthesis module and used for connecting and switching different paths of the tested chip;
a receiving change-over switch is connected with different paths of the tested chip and is used for switching the paths connected with the receiving analysis module;
the receiving analysis module comprises a low-power analysis path and a high-power analysis path, a high-pass filter is arranged on the high-power analysis path, and the receiving analysis module is used for receiving the data of the tested chip for analysis and display;
wherein, the signal synthesis module includes:
the signal source is connected to the input end of the first switch and is used for outputting signals;
the first output end of the first switch is connected with the first input end of the second switch to form the low-power output path;
the second output end of the first switch is connected with the second input end of the second switch through the high-power adjusting unit to form the high-power output path;
and the output end of the second switch is connected with the emission change-over switch.
2. The radio frequency chip test system according to claim 1, wherein the high power conditioning unit comprises a high power amplifier and triplexer, wherein,
one end of the high-power amplifier is connected with the second output end of the first switch, the other end of the high-power amplifier is connected with the LOW port of the triplexer, and the output port of the triplexer is connected with the second input end of the second switch;
the device comprises a triplexer, a harmonic generation unit, a DAC and a local oscillator source, wherein the midport and the HIGH port of the triplexer are respectively connected with the harmonic generation unit, the harmonic generation unit comprises an I/Q modulator, the DAC and the local oscillator source, the local oscillator source is connected with the midport or the HIGH port through the I/Q modulator, and the DAC is connected with the I/Q modulator.
3. The rf chip testing system of claim 1 wherein each input of the receive switch is connected to an attenuator for attenuating high power signals to reduce harmonic levels generated by the receive switch.
4. The radio frequency chip test system of claim 1, wherein the receive analysis module comprises:
the input end of the third switch is connected with the output end of the receiving change-over switch, and the first output end of the third switch is connected with the first input end of the fourth switch to form the low-power analysis path;
the second output end of the third switch is connected with the second input end of the fourth switch through the high-pass filter to form the high-power analysis path;
the output end of the fourth switch is connected with a frequency spectrograph, and the frequency spectrograph is used for receiving the data of the tested chip for analysis and display.
5. The radio frequency chip test system of claim 4, wherein the receive analysis module further comprises a directional coupler,
the directional coupler is arranged between the transmitting change-over switch and the tested chip and comprises a plurality of groups of forward ports and reflecting ports,
the multiple forward ports are connected with multiple input ends of a fifth switch, the output end of the fifth switch is connected with the third input end of the fourth switch, the multiple reflection ports are connected with multiple input ends of a sixth switch, and the output end of the sixth switch is connected with the fourth input end of the fourth switch.
6. The radio frequency chip testing system of any of claims 1-5, wherein the switches are all solid state switches.
7. A high power path testing method based on the radio frequency chip testing system of any of claims 1-6, comprising:
outputting a high power signal through the high power output path;
and the high-power signal passes through the tested chip and carries out high-power channel test on the tested chip through the high-power analysis channel.
8. The high power path testing method of claim 7, wherein the receive analysis module further comprises a directional coupler disposed between the transmit switch and the chip under test, comprising a plurality of sets of forward ports and reflective ports;
before the high-power analysis path is used for carrying out high-power path test on the tested chip, the method further comprises the following steps:
signal synthesis calibration is carried out through a high-power adjusting unit;
performing transmit power calibration based on a difference between a reflective port and a forward port of the directional coupler;
and recording the insertion loss of the harmonic receiving path, and calibrating the receiving path.
9. A low power path testing method based on the radio frequency chip testing system of any of claims 1-6, comprising:
outputting a low power signal through the low power output path;
and the low-power signal passes through the chip to be tested, and the low-power analysis path is used for carrying out low-power path test on the chip to be tested.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684453A (en) * | 2012-08-31 | 2014-03-26 | 复旦大学 | Test method for mass production of integrated chips of analog digital converter |
| CN103684638A (en) * | 2013-12-17 | 2014-03-26 | 中国电子科技集团公司第四十一研究所 | Intermodulation distortion testing method of high-power device |
| CN103744010A (en) * | 2013-12-26 | 2014-04-23 | 中国电子科技集团公司第三十六研究所 | An automatic testing system and an automatic testing method of a continuous wave radio frequency power amplifier |
| CN104753553A (en) * | 2013-12-26 | 2015-07-01 | 中兴通讯股份有限公司 | Device, mobile terminal and method for improving radiofrequency link receiving/transmitting performance |
| CN114879014A (en) * | 2022-05-17 | 2022-08-09 | 加特兰微电子科技(上海)有限公司 | Radio frequency chip testing method, device, testing equipment, medium and testing system |
| CN217935623U (en) * | 2022-04-21 | 2022-11-29 | 上海聚星仪器有限公司 | Radio frequency chip testing device with multiple sending and multiple receiving functions |
-
2022
- 2022-12-05 CN CN202211548716.6A patent/CN115754682B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684453A (en) * | 2012-08-31 | 2014-03-26 | 复旦大学 | Test method for mass production of integrated chips of analog digital converter |
| CN103684638A (en) * | 2013-12-17 | 2014-03-26 | 中国电子科技集团公司第四十一研究所 | Intermodulation distortion testing method of high-power device |
| CN103744010A (en) * | 2013-12-26 | 2014-04-23 | 中国电子科技集团公司第三十六研究所 | An automatic testing system and an automatic testing method of a continuous wave radio frequency power amplifier |
| CN104753553A (en) * | 2013-12-26 | 2015-07-01 | 中兴通讯股份有限公司 | Device, mobile terminal and method for improving radiofrequency link receiving/transmitting performance |
| CN217935623U (en) * | 2022-04-21 | 2022-11-29 | 上海聚星仪器有限公司 | Radio frequency chip testing device with multiple sending and multiple receiving functions |
| CN114879014A (en) * | 2022-05-17 | 2022-08-09 | 加特兰微电子科技(上海)有限公司 | Radio frequency chip testing method, device, testing equipment, medium and testing system |
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