CN115754682A - Radio frequency chip test system and high and low power path test method - Google Patents
Radio frequency chip test system and high and low power path test method Download PDFInfo
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Abstract
The application discloses a radio frequency chip test system and a high-low power path test method. The system comprises: the signal synthesis module comprises a low-power output path and a high-power output path and is used for synthesizing and outputting low-power and high-power signals; the transmitting switch is connected with the signal synthesis module and is used for connecting and switching different channels of the tested chip; the receiving switch is connected with different paths of the chip to be tested and is switched to be connected with the paths of the receiving analysis module; and the receiving and analyzing module comprises a low-power analyzing path and a high-power analyzing path, a high-pass filter is arranged on the high-power analyzing path, and the receiving and analyzing module is used for receiving the data of the chip to be tested, analyzing and displaying the data. The invention has the advantages that the low-power path test and the high-power path test are compatible, the nonlinear components generated by the electronic switch are eliminated by switching the solid-state switch and adopting a vector synthesis mode, and the number of channels is reduced, thereby reducing the cost and the complexity of the system.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a radio frequency chip testing system and a high-low power path testing method.
Background
Testing of radio frequency chips typically includes insertion loss, gain, isolation, harmonics, output power, modulation quality, etc. The harmonic test of the radio frequency switch requires a high-power input signal, the other signals require low-power high-precision signals, and a proper switch array is selected to switch a test channel. Harmonic testing typically employs a signal source, PA, triplexer, or filter combination to provide a high purity single tone signal. If the high-purity single-tone signal passes through the electronic switch, nonlinear harmonic waves are generated again, and the test result is influenced. The linearity of the mechanical switch is high but the switching speed is low, the mass production chip test switches the switch millions of times every day, and the service life of the mechanical switch cannot be tested with high strength. If high and low power are separately tested, test time is wasted, and test cost is increased. If a switch network is not used for multiplexing a public channel, the multichannel tester is high in price and large in size.
Therefore, it is necessary to develop a system for testing a radio frequency chip based on vector composition and a method for testing high and low power paths.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.
Disclosure of Invention
The invention provides a radio frequency chip test system and a high-low power path test method. The invention integrates high-power harmonic test and broadband low-power insertion loss, gain, isolation, modulation quality and other tests, and can make the low-power path test and the high-power path test compatible, thereby meeting most of test requirements. The electronic switch switching is adopted for multi-channel testing, nonlinear components generated by the electronic switch are eliminated in a vector synthesis mode, the number of channels is reduced, the cost and the system complexity are reduced, and the problem that a solid-state switch cannot be used is effectively solved. In the face of various testing requirements, the solid-state switch switching module and the solid-state switch switching channel can be matched, and the flexibility is higher.
In a first aspect, an embodiment of the present disclosure provides a radio frequency chip test system, including:
the signal synthesis module comprises a low-power output path and a high-power output path, wherein the high-power output path is provided with a high-power adjusting unit, and the signal synthesis module is used for synthesizing and outputting low-power and high-power signals;
the transmitting switch is connected with the signal synthesis module and is used for connecting and switching different paths of the tested chip;
the receiving switch is connected with different paths of the chip to be tested and is switched to be connected with the paths of the receiving analysis module;
and the receiving and analyzing module comprises a low-power analyzing path and a high-power analyzing path, a high-pass filter is arranged on the high-power analyzing path, and the receiving and analyzing module is used for receiving the data of the chip to be tested for analysis and display.
Preferably, the signal synthesis module includes:
the signal source is connected with the input end of the first switch and used for outputting signals;
the first output end of the first switch is connected with the first input end of the second switch to form the low-power output path;
the second output end of the first switch is connected to the second input end of the second switch through the high-power regulating unit to form the high-power output path;
the output end of the second switch is connected with the transmitting selector switch.
Preferably, the high power regulating unit includes a high power amplifier and a triplexer, wherein,
one end of the high-power amplifier is connected to the second output end of the first switch, the other end of the high-power amplifier is connected to the LOW port of the triplexer, and the output port of the triplexer is connected to the second input end of the second switch;
an MID port and a HIGH port of the triplexer are respectively connected with a harmonic generation unit, wherein the harmonic generation unit comprises an I/Q modulator, a DAC and a local vibration source, the local vibration source is connected with the MID port or the HIGH port through the I/Q modulator, and the DAC is connected with the I/Q modulator.
Preferably, each input end of the receiving switch is connected with an attenuator, and the attenuators are used for attenuating high-power signals, so that the harmonic level generated by the receiving switch is reduced.
Preferably, the reception analysis module includes:
the input end of the third switch is connected with the output end of the receiving changeover switch, and the first output end of the third switch is connected with the first input end of the fourth switch to form the low-power analysis path;
the second output end of the third switch is connected to the second input end of the fourth switch through the high-pass filter to form the high-power analysis channel;
and the output end of the fourth switch is connected with a frequency spectrograph, and the frequency spectrograph is used for receiving the data of the chip to be tested, analyzing and displaying the data.
Preferably, the reception analysis module further comprises a directional coupler,
the directional coupler is arranged between the emission selector switch and the chip to be tested and comprises a plurality of groups of forward ports and reflecting ports,
the plurality of forward ports are connected with a plurality of input ends of a fifth switch, the output end of the fifth switch is connected with the third input end of the fourth switch, the plurality of reflection ports are connected with a plurality of input ends of a sixth switch, and the output end of the sixth switch is connected with the fourth input end of the fourth switch.
Preferably, the switches are all solid state switches.
In a second aspect, an embodiment of the present disclosure further provides a high power path testing method, including:
outputting a high power signal through the high power output path;
and the high-power signal passes through the chip to be tested, and a high-power path test is carried out on the chip to be tested through the high-power analysis path.
Preferably, before the high power path test is performed on the chip under test through the high power analysis path, the method further includes:
performing signal synthesis calibration through a high-power regulating unit;
calibrating the transmitting power based on the difference value of the reflecting port and the forward port of the directional coupler;
and recording the insertion loss of the harmonic receiving path and calibrating the receiving path.
Preferably, the high power path test is performed on the chip under test through the high power analysis path, and the method includes:
measuring signals of a forward port and a reflection port of the directional coupler at harmonic frequencies to obtain directional data of the directional coupler;
adjusting the output power of the signal according to the difference data obtained by calibrating the transmitting power so as to enable the transmitting signal to reach the expected power;
detecting vector signals of a forward port and a reflection port of the directional coupler;
calculating the harmonic power of the forward port according to the calibrated directional data, calculating a DAC (digital-to-analog converter) code value through interpolation, and eliminating a harmonic signal to obtain a single-tone signal;
and recording the harmonic power of the receiving channel, and compensating the insertion loss of the receiving channel to obtain the actual value of the harmonic.
Preferably, the signal synthesis calibration by the high power adjustment unit comprises:
respectively adjusting intermediate frequency voltage DAC of the I/Q modulator, and combining each group of code values of the DAC to synthesize a vector signal;
detecting the vector signal through a forward port of the directional coupler to obtain vector signal data of the I/Q modulator;
the code value combinations are stepped through the DAC code values and the resulting vector signal data is recorded.
In a third aspect, an embodiment of the present disclosure further provides a low power path testing method, including:
outputting a low power signal through the low power output path;
and the low-power signal passes through the tested chip, and the low-power analysis path is used for performing low-power path test on the tested chip.
Preferably, the transmitting power calibration is carried out by recording the difference value between the output port and the forward port of the directional coupler;
recording the insertion loss of each low-power receiving channel, and calibrating the low-power receiving channel;
and carrying out low-power path test on the tested chip through a radio frequency chip test system.
The beneficial effects are that:
1. the invention realizes the tests of high-power harmonic wave test, low-power insertion loss, harmonic wave, isolation, gain, EVM, ACPR and the like, covers the test functions of most radio frequency chips, solves the problem that the high-power and low-power channel tests cannot be compatible, and improves the test efficiency and the utilization rate of a test machine.
2. The source end adopts the directional coupler to detect the transmitting power in real time, so that the precision of the transmitting power is ensured, and mismatch errors caused by the mismatch of the source end impedance and the DUT impedance are eliminated. The receiving end adopts an attenuator to improve impedance, provides broadband 50-ohm input impedance and improves power accuracy. And the real-time dynamic synthesis of system harmonics provides enough signal-to-noise ratio for the harmonic test of the DUT.
3. The multi-channel test system usually adopts switches to switch test channels, has slow mechanical switching speed and short service life, and is not suitable for mass production test of chips. The solid-state switch can not be applied to a harmonic test system of the switch due to the characteristic that the high-power input of the solid-state switch can excite harmonic waves. The invention adopts a vector synthesis mode aiming at the multi-channel test requirements of the chip, effectively solves the harmonic problem of the solid-state switch, can flexibly match the switching module and the channel of the solid-state switch in the face of various test requirements, and reuses a radio frequency channel, thereby saving the cost, and has high and low power compatibility so as to improve the test efficiency.
The method and apparatus of the present invention have other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, wherein like reference numerals generally represent like parts in the exemplary embodiments of the present invention.
FIG. 1 shows a block diagram of a radio frequency chip test system according to an embodiment of the invention.
Fig. 2 shows a flow chart of the steps of a high power path testing method according to one embodiment of the invention.
FIG. 3 shows a flow chart of the steps of a low power path testing method according to one embodiment of the invention.
Description of the reference numerals:
100. a signal synthesis module; 101. a signal source; 102. a first switch; 103. a second switch; 104. a high power amplifier; 105. a DAC; 106. a DAC; 107. the vibration source; 108. the vibration source; 109. an I/Q modulator; 110. an I/Q modulator; 111. a triplexer; 200. a transmission changeover switch; 300. receiving a change-over switch; 301. an attenuator; 302. an attenuator; 303. an attenuator; 304. an attenuator; 400. a receiving and analyzing module; 401. a third switch; 402. a high-pass filter; 403. a fourth switch; 404. a fifth switch; 405. a sixth switch; 406. a frequency spectrograph; 407. a directional coupler.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the following describes preferred embodiments of the present invention, it should be understood that the present invention may be embodied in various forms and should not be limited by the embodiments set forth herein.
To facilitate understanding of the solution of the embodiments of the present invention and the effects thereof, three specific application examples are given below. It will be understood by those skilled in the art that this example is merely for the purpose of facilitating an understanding of the present invention and that any specific details thereof are not intended to limit the invention in any way.
Example 1
A radio frequency chip test system, comprising:
the signal synthesis module comprises a low-power output path and a high-power output path, wherein the high-power output path is provided with a high-power adjusting unit, and the signal synthesis module is used for synthesizing and outputting low-power and high-power signals;
the transmitting switch is connected with the signal synthesis module and is used for connecting and switching different paths of the chip to be tested;
the receiving switch is connected with different paths of the chip to be tested and is switched to be connected with the paths of the receiving analysis module;
and the receiving and analyzing module comprises a low-power analyzing path and a high-power analyzing path, a high-pass filter is arranged on the high-power analyzing path, and the receiving and analyzing module is used for receiving the data of the chip to be tested, analyzing and displaying the data.
In one example, the signal synthesis module includes:
the signal source is connected to the input end of the first switch and used for outputting signals;
the first output end of the first switch is connected with the first input end of the second switch to form a low-power output path;
the second output end of the first switch is connected to the second input end of the second switch through the high-power regulating unit to form a high-power output path;
the output end of the second switch is connected with the transmitting change-over switch.
In one example, the high power conditioning unit includes a high power amplifier and a triplexer, wherein,
one end of the high-power amplifier is connected to the second output end of the first switch, the other end of the high-power amplifier is connected to the LOW port of the triplexer, and the output port of the triplexer is connected to the second input end of the second switch;
the MID port and the HIGH port of the triplexer are respectively connected with a harmonic generation unit, wherein the harmonic generation unit comprises an I/Q modulator, a DAC and a local vibration source, the local vibration source is connected with the MID port or the HIGH port through the I/Q modulator, and the DAC is connected with the I/Q modulator.
In one example, an attenuator is connected to each input of the receive switch for attenuating the high power signal to reduce the level of harmonics generated by the receive switch.
In one example, the reception analysis module includes:
the input end of the third switch is connected with the output end of the receiving change-over switch, and the first output end of the third switch is connected with the first input end of the fourth switch to form a low-power analysis path;
the second output end of the third switch is connected with the second input end of the fourth switch through a high-pass filter to form a high-power analysis channel;
the output end of the fourth switch is connected with the frequency spectrograph, and the frequency spectrograph is used for receiving the data of the chip to be tested for analysis and display.
In one example, the receive analysis module further comprises a directional coupler,
the directional coupler is arranged between the emission selector switch and the chip to be tested and comprises a plurality of groups of forward ports and reflecting ports,
the plurality of forward ports are connected with a plurality of input ends of the fifth switch, the output end of the fifth switch is connected with the third input end of the fourth switch, the plurality of reflection ports are connected with a plurality of input ends of the sixth switch, and the output end of the sixth switch is connected with the fourth input end of the fourth switch.
In one example, the switches are all solid state switches.
FIG. 1 shows a block diagram of a radio frequency chip test system according to an embodiment of the invention.
Specifically, as shown in fig. 1, the rf chip testing system includes:
a signal synthesizing module 100 for synthesizing and outputting low power and high power signals, comprising:
the signal source 101 is connected to an input end of the first switch 102, and is configured to output a signal; the first output terminal of the first switch 102 is connected to the first input terminal of the second switch 103 to form a low power output path, which provides a source signal for testing, such as insertion loss, isolation, gain, output power, ACPR, EVM, and the like; a second output end of the first switch 102 is connected to a second input end of the second switch 103 through a high-power regulating unit to form a high-power output path which is mainly used for harmonic testing; the output of the second switch 103 is connected to a transmit switch 200.
The HIGH-power adjusting unit comprises a HIGH-power amplifier 104 and a triplexer 111, the triplexer 111 can filter nonlinear harmonics generated by a PA while playing a combining role, and meanwhile, MID and HIGH ports of the triplexer 111 can absorb harmonics generated by a DUT (chip) to be measured, so that the measurement accuracy is ensured. One end of the high-power amplifier 104 is connected to the second output end of the first switch 102, the other end is connected to the LOW port of the triplexer 111, and the output port of the triplexer 111 is connected to the second input end of the second switch 103; the MID port and the HIGH port of the triplexer 111 are respectively connected with a harmonic generation unit, wherein the harmonic generation unit comprises I/Q modulators 109-110, DACs 105-106 and local vibration sources 107-108, the local vibration sources 107-108 are connected with the MID port or the HIGH port through the I/Q modulators 109-110, and the DACs 105-106 are connected with the I/Q modulators 109-110. The local vibration sources 107-108 adopt 10MHz reference frequency signals of the signal source 101 to generate second and third harmonics which are phase-locked with SG for synthesis. Except that the triplexer 111 is not a broadband device, other modules can be compatible with all test frequency bands, and different triplexers can be switched by adopting a solid-state switch, so that test requirements of different frequency bands are met.
Due to multiplexing of a transmitting path, the broadband high-power PA and the triplexer 111 are multiplexed, the cost can be greatly reduced, and the size can be reduced. Can be flexibly configured according to different requirements. The solid state switch can also be used to switch different triplexers 111 to meet the test requirements of each frequency band.
The emission selector switch 200 is connected with the signal synthesis module 100 and used for connecting and switching different test paths of the tested chip; SP4T, SP8T and SP16T switches can be flexibly selected, 4, 8 and 16 channel output is realized, and various testing requirements are met. The mechanical switch is limited by switching speed and service life, is not suitable for mass production chip test systems, and can adopt a mode of combining broadband solid-state switches to realize standing waves and isolation degree which are comparable to those of the mechanical switch.
A receiving switch 300, which is connected to different paths of the tested chip and is switched to connect to the path of the receiving analysis module 400; the SP4T, SP8T and SP16T switches can be flexibly selected, and 4, 8 and 16 channel input is realized. Different from the transmission switch, attenuators 301 to 304 are added to each input port in order to reduce the rf power entering the switch 300, thereby reducing the harmonic level generated by the switch 300 and ensuring the testing accuracy.
The reception analysis module 400 includes:
the input end of the third switch 401 is connected to the output end of the receiving switch 300, and the first output end of the third switch 401 is connected to the first input end of the fourth switch 403, so as to form a low power analysis path; a second output end of the third switch 401 is connected to a second input end of the fourth switch 403 through a high-pass filter 402 to form a high-power analysis path; the output end of the fourth switch 403 is connected to the spectrometer 406, and the spectrometer 406 is configured to receive data of the chip under test for analysis and display.
The receiving and analyzing module 400 further includes a directional coupler 407, the directional coupler 407 is disposed between the transmitting switch 200 and the chip to be tested, and includes a plurality of sets of forward ports and reflecting ports, wherein the plurality of forward ports are connected to a plurality of input terminals of the fifth switch 404, and an output terminal of the fifth switch 404 is connected to the output terminal of the fifth switch 404
A third input of the fourth switch 403, a plurality of reflective ports connected to a plurality of inputs of a sixth switch 405, and an output of the sixth switch 405 connected to a fourth input of the fourth switch 403.
All the switches are solid-state switches, and nonlinear harmonics can be generated when the solid-state switches pass through high-power signals. The mechanical switch has short service life and low speed, and the switching path of the switch cannot be adopted to meet various testing requirements; the invention adopts a vector synthesis mode to generate high-purity single tone signals, and generates synthesized signals aiming at different chips in real time, thereby improving the test precision.
The receive analysis module 400 gates the receive signal, respectively the low power, high power path signal and the vector composite signal detected by the directional coupler 407, through the switch 401. The low power path receives signals such as insertion loss, isolation, gain, EVM, etc., which are input to the spectrometer 406 through the third 401 to fourth 403 switches. The high-power channel signal receives the harmonic signal gated by the third switch 401, the main frequency signal is filtered by the high-pass filter 402, and the reflected main frequency signal is attenuated again by the attenuators 301 to 304, so that the standing wave state of a DUT (chip under test) is prevented from being influenced. The directional coupler 407 adopts a bidirectional directional coupler or two unidirectional directional couplers which are cascaded to respectively extract forward transmission signals (PF 11-PF 14) and backward reflection signals (PR 11-PR 14) of each channel. The forward transmit signal into the DUT is a high power signal output by the transmit path, while introducing harmonic signals due to solid state switch nonlinearities. The DUT generates a harmonic reflected signal reflected back to the source end and a harmonic forward signal transmitted forward to the receiving path after inputting the high-power signal, and the two harmonic signals generated by the DUT are close in power. During the harmonic test, a forward transmission signal needs to be synthesized, and the harmonic signal introduced by the solid-state switch is eliminated, so that the forward transmission harmonic signal entering the DUT is at least 20dB lower than the harmonic signal generated by the DUT, and the test precision is ensured.
Example 2
Fig. 2 shows a flow chart of the steps of a high power path testing method according to one embodiment of the invention.
As shown in fig. 2, the high power path testing method includes:
outputting a high power signal through a high power output path;
and the high-power signal passes through the tested chip, and the high-power analysis channel is used for testing the high-power channel of the tested chip.
In one example, before the high power path test is performed on the chip under test through the high power analysis path, the method further includes:
performing signal synthesis calibration through a high-power regulating unit;
calibrating the transmitting power based on the difference value of the reflecting port and the forward port of the directional coupler;
and recording the insertion loss of the harmonic receiving channel and calibrating the receiving channel.
In one example, a high power path test is performed on a chip under test through a high power analysis path, comprising:
measuring signals of a forward port and a reflection port of the directional coupler on harmonic frequency to obtain directional data of the directional coupler;
adjusting the output power of the signal according to the difference data obtained by calibrating the transmitting power so as to enable the transmitting signal to reach the expected power;
detecting vector signals of a forward port and a reflection port of the directional coupler;
calculating the harmonic power of a forward port according to the calibrated directional data, obtaining DAC (digital-to-analog converter) code values through interpolation calculation, eliminating harmonic signals and obtaining single-tone signals;
and recording the harmonic power of the receiving channel, and compensating the insertion loss of the receiving channel to obtain the actual value of the harmonic.
In one example, performing signal synthesis calibration by a high power conditioning unit includes:
respectively adjusting intermediate frequency voltage DAC of the I/Q modulator, and combining each group of code values of the DAC to synthesize a vector signal;
detecting the vector signal through a forward port of the directional coupler to obtain vector signal data of the I/Q modulator;
the code value combinations are stepped through the DAC code values and the resulting vector signal data is recorded.
Specifically, the signal synthesis module generates a signal with the same amplitude and opposite phase with the harmonic signal of the system, and pre-calibration is required to reduce the calibration time during testing. Adjusting the intermediate frequency voltage DAC of the I/Q modulator respectively, wherein each code value combination of the DAC synthesizes a vector signal. And detecting the vector signal by adopting a PF1X port of the directional coupler, and entering a frequency spectrograph through a fifth switch to a fourth switch to finally obtain I/Q vector signal data. These combinations are stepped through at certain DAC code values and the resulting vector signal data is recorded.
And detecting the high-power transmitting power by a PF1X port of the directional coupler, calibrating the difference value between the output port of the directional coupler and the PF1X port, and recording.
The calibration harmonics receive the insertion loss of each channel and are recorded.
High power path testing is primarily harmonic testing. Firstly, PF1X and PR1X signals of the directional coupler are measured on harmonic frequency to obtain directional data of the directional coupler, and then the output power of a signal source is adjusted according to difference data obtained by transmitting power calibration to enable a transmitting signal to reach expected power. The vector signals of PF1X and PR1X of the directional coupler are then detected. The harmonic power of the system in the PF1X can be accurately calculated according to the calibrated directional data. In order to generate signals with the same amplitude and opposite phase with the harmonic power of the system, the signals are needed to synthesize calibrated data, and the DAC code value meeting the requirement is obtained through interpolation calculation. And eliminating harmonic signals by a mode of searching and detecting near the code value to obtain high-purity single tone signals. At this time, the harmonic power of the receiving channel is recorded, and the insertion loss of the receiving channel is compensated to obtain the actual value of the harmonic.
Example 3
FIG. 3 shows a flow chart of the steps of a low power path testing method according to one embodiment of the invention.
As shown in fig. 3, the low power path testing method includes:
outputting a low power signal through a low power output path;
the low-power signal passes through the tested chip, and the low-power path test is carried out on the tested chip through the low-power analysis path.
In one example, transmit power calibration is performed by recording the difference between the directional coupler output port and the forward port;
recording the insertion loss of each low-power receiving channel, and calibrating the low-power receiving channel;
and carrying out low-power path test on the tested chip by the radio frequency chip test system.
Specifically, a low power transmit path is routed from a signal source through a first switch to a second switch output, through a transmit switch and a directional coupler into the DUT, and transmit power detection is provided by the PF1X port of the directional coupler. The difference between the output port of the directional coupler and the port of PF1X is calibrated and recorded.
And the low-power receiving path enters the frequency spectrograph through the receiving change-over switch, the third switch and the fourth switch, the insertion loss of the receiving path is calibrated, and the recording is carried out.
The low power path test can realize the functions of insertion loss, gain, isolation, output power, ACPR, OBW, EVM and the like. The output power of the transmitting access is detected by a PF1X port of the directional coupler in real time, the directional coupler can detect the actual power of power transmission, the power mismatch caused by the impedance mismatch of a DUT standing wave and a source end is eliminated, and the transmitting power precision is improved. The low-power receiving path is matched by an attenuator at the front end, the testing precision is improved, and the power detected by the frequency spectrograph compensates the insertion loss of the receiving path to obtain the actual power. And the other tests such as ACPR, OBW, EVM and the like are analyzed by a frequency spectrograph.
It will be appreciated by persons skilled in the art that the above description of embodiments of the invention is intended only to illustrate the benefits of embodiments of the invention and is not intended to limit embodiments of the invention to any examples given.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.
Claims (10)
1. A radio frequency chip test system, comprising:
the signal synthesis module comprises a low-power output path and a high-power output path, wherein the high-power output path is provided with a high-power adjusting unit, and the signal synthesis module is used for synthesizing and outputting low-power and high-power signals;
the transmitting switch is connected with the signal synthesis module and is used for connecting and switching different paths of the tested chip;
the receiving switch is connected with different paths of the chip to be tested and is switched to be connected with the paths of the receiving and analyzing module;
and the receiving and analyzing module comprises a low-power analyzing path and a high-power analyzing path, a high-pass filter is arranged on the high-power analyzing path, and the receiving and analyzing module is used for receiving the data of the chip to be tested, analyzing and displaying the data.
2. The radio frequency chip test system of claim 1, wherein the signal synthesis module comprises:
the signal source is connected with the input end of the first switch and used for outputting signals;
the first output end of the first switch is connected with the first input end of the second switch to form the low-power output path;
the second output end of the first switch is connected to the second input end of the second switch through the high-power regulating unit to form the high-power output path;
the output end of the second switch is connected with the transmitting selector switch.
3. The RF chip test system of claim 2 wherein the high power conditioning unit includes a high power amplifier and a triplexer, wherein,
one end of the high-power amplifier is connected to the second output end of the first switch, the other end of the high-power amplifier is connected to the LOW port of the triplexer, and the output port of the triplexer is connected to the second input end of the second switch;
an MID port and a HIGH port of the triplexer are respectively connected with a harmonic generation unit, wherein the harmonic generation unit comprises an I/Q modulator, a DAC and a local vibration source, the local vibration source is connected with the MID port or the HIGH port through the I/Q modulator, and the DAC is connected with the I/Q modulator.
4. The radio frequency chip test system of claim 1, wherein each input terminal of the receiving switch is connected to an attenuator, and the attenuators are configured to attenuate high power signals, so as to reduce the harmonic level generated by the receiving switch.
5. The radio frequency chip test system of claim 1, wherein the reception analysis module comprises:
the input end of the third switch is connected with the output end of the receiving changeover switch, and the first output end of the third switch is connected with the first input end of the fourth switch to form the low-power analysis path;
the second output end of the third switch is connected to the second input end of the fourth switch through the high-pass filter to form the high-power analysis channel;
and the output end of the fourth switch is connected with a frequency spectrograph, and the frequency spectrograph is used for receiving the data of the chip to be tested, analyzing and displaying the data.
6. The radio frequency chip test system of claim 5, wherein the reception analysis module further comprises a directional coupler,
the directional coupler is arranged between the emission selector switch and the chip to be tested and comprises a plurality of groups of forward ports and reflecting ports,
the plurality of forward ports are connected with a plurality of input ends of a fifth switch, an output end of the fifth switch is connected with a third input end of the fourth switch, a plurality of reflection ports are connected with a plurality of input ends of a sixth switch, and an output end of the sixth switch is connected with a fourth input end of the fourth switch.
7. The radio frequency chip test system of any one of claims 1 to 6, wherein the switches are all solid state switches.
8. A high-power path testing method based on the RF chip testing system of any one of claims 1-7, comprising:
outputting a high power signal through the high power output path;
and the high-power signal passes through the chip to be tested, and a high-power path test is carried out on the chip to be tested through the high-power analysis path.
9. The high power path testing method of claim 8, wherein the receiving and analyzing module further comprises a directional coupler, disposed between the transmit switch and the chip under test, comprising a plurality of sets of forward ports and reflective ports;
before the high power path test is performed on the chip under test through the high power analysis path, the method further includes:
performing signal synthesis calibration through a high-power regulating unit;
calibrating the transmitting power based on the difference value of the reflecting port and the forward port of the directional coupler;
and recording the insertion loss of the harmonic receiving path and calibrating the receiving path.
10. A low power path testing method based on the rf chip testing system of any one of claims 1 to 7, comprising:
outputting a low power signal through the low power output path;
and the low-power signal passes through the tested chip, and the low-power analysis path is used for performing low-power path test on the tested chip.
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