CN115733482A - Input interface circuit and chip - Google Patents
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- CN115733482A CN115733482A CN202211525914.0A CN202211525914A CN115733482A CN 115733482 A CN115733482 A CN 115733482A CN 202211525914 A CN202211525914 A CN 202211525914A CN 115733482 A CN115733482 A CN 115733482A
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Abstract
The application provides an input interface circuit and chip, input interface circuit includes: a reference voltage generating unit configured to generate different plurality of reference voltages using a reference input voltage; a reference voltage adjustment unit configured to determine a respective reference voltage of the plurality of reference voltages as a gate reference voltage of an input tube of the input interface circuit according to a voltage of an input signal; a hysteresis generation unit configured to generate a hysteresis output signal according to the determined gate reference voltage; and a signal output unit configured to gain-adjust the hysteretic output signal to output a desired voltage domain signal, the voltage domain of the input signal being lower than the voltage domain of the desired voltage domain signal. The low-voltage-domain input threshold can be realized by using the field effect transistor, and the input threshold has small influence along with the change of the process angle and the power supply voltage of the field effect transistor.
Description
Technical Field
The present application relates generally to the field of circuit design, and more particularly, to an input interface circuit and a chip.
Background
In current input interface circuits, the voltage domain of AVCC is generally implemented as follows: the input voltage directly converts the voltage domain of the input signal, for example, the 1.2V voltage domain, to the voltage domain of the AVCC through the schmitt gate, the not gate, and the level shifter.
However, in the design of the existing input interface circuit, the input threshold of some schmitt gates is greatly influenced by the power supply voltage, and meanwhile, the input transistors with the same size are greatly influenced by the threshold voltage of the field effect transistor, so that the input interface circuit is sensitive to the process angle of the field effect transistor; it is also difficult to control the voltage trigger points of the upper and lower thresholds in the design circuit.
Disclosure of Invention
An object of the present application is to provide an input interface circuit and a chip, which are used to solve the problem that the input threshold of a schmitt gate is greatly influenced by a power supply voltage and by the transistor threshold voltage of a field effect transistor.
In a first aspect, the present application provides an input interface circuit comprising: a reference voltage generating unit configured to generate different plurality of reference voltages using a reference input voltage; a reference voltage adjustment unit configured to determine a respective reference voltage of the plurality of reference voltages as a gate reference voltage of an input tube of the input interface circuit according to a voltage of an input signal; a hysteresis generation unit configured to generate a hysteresis output signal according to the determined gate reference voltage; and a signal output unit configured to gain-adjust the hysteretic output signal to output a desired voltage domain signal, the voltage domain of the input signal being lower than the voltage domain of the desired voltage domain signal.
In the application, the field effect transistor is utilized to realize the low-voltage domain input threshold, and the input threshold has small influence along with the change of the process angle and the power supply voltage of the field effect transistor.
In one implementation of the first aspect, the plurality of reference voltages includes a first reference voltage, a second reference voltage, and a third reference voltage, the first reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the third reference voltage.
In the implementation mode, three reference voltages with small relation with the power supply voltage are generated through the fixed reference input voltage and serve as the grid electrode reference voltage of the input tube, so that the influence of the input threshold value along with the change of the power supply voltage is small.
In an implementation manner of the first aspect, the hysteresis generation unit is configured to: generating the hysteretic output signal varying from a low level to a high level when the input signal is greater than a first input threshold voltage associated with the first reference voltage during a low to high level transition of the input signal; and generating the hysteretic output signal varying from a high level to a low level when the input signal is less than a second input threshold voltage associated with the third reference voltage during a transition of the input signal from a high level to a low level, the first input threshold voltage being greater than the second input threshold voltage.
In one implementation of the first aspect, the reference voltage adjustment unit is configured to select a respective reference voltage of the plurality of reference voltages as the gate reference voltage according to a voltage magnitude of the input signal by a first switch control signal that is an inverted signal of the desired voltage domain signal and a second switch control signal that is an inverted signal of the first switch control signal.
In one implementation of the first aspect, the reference voltage generation unit comprises: the circuit comprises an operational amplifier, a first MOS tube, a second MOS tube, a first resistor, a second resistor, a third resistor and a fourth resistor; the first reference voltage is determined by a loop current, a first equivalent resistance value, a threshold voltage of the second MOS transistor and the reference input voltage, and the first equivalent resistance value is the sum of series resistance values of the second resistor, the third resistor and the fourth resistor; the second reference voltage is determined by the loop current, a second equivalent resistance value, a threshold voltage of the second MOS transistor and the reference input voltage, and the second equivalent resistance value is the sum of series resistance values of the third resistor and the fourth resistor; the third reference voltage is determined by the loop current, a third equivalent resistance value, the threshold voltage of the second MOS transistor, and the reference input voltage, and the third equivalent resistance value is the resistance value of the fourth resistor.
In the implementation mode, the low-voltage domain input threshold is realized through the 5V field effect transistor, and the cost is reduced.
In one embodiment of the first aspect, the first MOS transistor, the first resistor, the second resistor, the third resistor, the second MOS transistor, and the fourth resistor are electrically coupled in series with each other between a power supply terminal and a forward input terminal of the operational amplifier; a negative input terminal of the operational amplifier receives the reference input voltage, and an output terminal of the operational amplifier is electrically coupled to a grid electrode of the first MOS transistor; the grid electrode of the second MOS tube is electrically coupled to the drain electrode of the second MOS tube and the third resistor.
In one implementation manner of the first aspect, the reference voltage adjusting unit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; the first switch, the second switch and the third switch form a first adjusting unit, and the first adjusting unit is controlled to be switched on and off by a first switch control signal; the fourth switch, the fifth switch and the sixth switch form a second adjusting unit, and the second adjusting unit is controlled to be switched on and off by a second switch control signal.
In an implementation manner of the first aspect, in response to that the input signal is in a first state, the first switch control signal controls the first adjusting unit to be turned on, the second switch control signal controls the second adjusting unit to be turned off, and a gate reference voltage of an input tube of the input interface circuit is switched to the first reference voltage; and responding to the second state of the input signal, the second switch control signal controls the second adjusting unit to be switched on, the first switch control signal controls the first adjusting unit to be switched off, and the grid reference voltage of the input tube of the input interface circuit is switched to the third reference voltage.
In an implementation manner of the first aspect, the reference voltage adjusting unit further includes: a capacitor configured to: in response to the first switch control signal, a first terminal and a second terminal of the capacitor are electrically coupled to the first reference voltage and the second reference voltage, respectively, and the first terminal is electrically coupled to a gate of the input tube; and in response to the second switch control signal, the first and second terminals of the capacitor are electrically coupled to the second and third reference voltages, respectively, and the second terminal is electrically coupled to the gate of the input tube.
In the implementation mode, when the grid of the input tube is switched to be referenced, the capacitor can shorten the stabilization time of the grid of the input tube.
In one embodiment of the first aspect, the hysteresis generating unit includes a third MOS transistor and a fourth MOS transistor electrically coupled in series with each other between a power supply terminal and the input signal; the source electrode of the third MOS tube is electrically coupled to the power supply terminal, and the drain electrode of the third MOS tube is electrically coupled to the drain electrode of the fourth MOS tube; the fourth MOS transistor is an input transistor of the input interface circuit, the input signal is input into the input interface circuit via a source electrode of the fourth MOS transistor, and the hysteretic output signal is generated at drain electrodes of the third MOS transistor and the fourth MOS transistor.
In the implementation mode, the influence of the input threshold value along with the change of the threshold voltage of the field effect transistor is small by utilizing the threshold voltage compensation relation of the second MOS transistor and the fourth MOS transistor.
In one implementation manner of the first aspect, in response to the input signal being in a first state, a first voltage is generated at the drains of the third MOS transistor and the fourth MOS transistor, and the first switch control signal and the second switch control signal with opposite levels from each other are generated according to the first voltage; in response to the input signal being in a second state, a second voltage is generated at the drains of the third MOS transistor and the fourth MOS transistor, and the first switch control signal and the second switch control signal are generated according to the second voltage, wherein the levels of the first switch control signal and the second switch control signal are opposite to each other, and the first voltage is lower than the second voltage.
In one embodiment of the first aspect, the signal output unit includes a first inverter and a second inverter; the first inverter and the second inverter are connected in series, the first switch control signal is output from an output terminal of the first inverter, and the desired voltage domain signal and the second switch control signal inverted from the first switch control signal are output from an output terminal of the second inverter.
In one embodiment of the first aspect, the signal output unit further comprises a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter; the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series; the hysteresis output signal is input by the first inverter and is output as the desired voltage domain signal through the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter in sequence; wherein the sixth inverter outputs the second switching control signal, and the seventh inverter outputs the first switching control signal.
In one embodiment of the first aspect, the signal output unit is electrically coupled to an external digital circuit to transmit the desired voltage domain signal to the external digital circuit.
A second aspect of the embodiments of the present application provides a chip, including: the input interface circuit.
In the input interface circuit and the chip, the pure 5V field effect transistor can be used for realizing the low-voltage domain input threshold, and the input threshold has small influence along with the change of the process angle and the power supply voltage of the field effect transistor. The input threshold of a low voltage domain is realized through the field effect transistor of 5V, and the cost is reduced. Three reference voltages with small relation with the power supply voltage are generated through the fixed reference voltage and serve as the grid electrode reference voltage of the input tube, so that the influence of the input threshold value changing along with the power supply voltage is small. By utilizing the threshold voltage compensation relation of the second MOS tube and the fourth MOS tube, the influence of the input threshold value along with the threshold voltage change of the field effect tube is small. The capacitor can shorten the stabilization time of the grid of the input tube when the grid of the input tube switches the reference.
Drawings
Fig. 1 is a schematic structural diagram of an input interface circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic circuit diagram of an input interface circuit according to an embodiment of the present application.
Fig. 3 is a schematic circuit diagram of an input interface circuit according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, and the type, number and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The Schmitt gate, the NOT gate and the level shifter in the input interface circuit are improved, and the voltage domain of the input signal is directly converted into the voltage domain of the AVCC.
The principle and implementation of an input interface circuit and a chip of the present embodiment will be described in detail below with reference to all the accompanying drawings, so that those skilled in the art can understand the input interface circuit and the chip of the present embodiment without creative efforts.
Fig. 1 shows a schematic structural diagram of an input interface circuit according to an embodiment of the present application. As shown in fig. 1, the input interface circuit 10 includes: a reference voltage generating unit 11, a reference voltage adjusting unit 12, a hysteresis generating unit 13, and a signal output unit 14.
The reference voltage generating unit 11 is configured to generate different multiple reference voltages using a reference input voltage.
The reference voltage adjusting unit 12 is configured to determine a respective reference voltage of the plurality of reference voltages as a gate reference voltage of an input tube of the input interface circuit according to a voltage of the input signal. In some embodiments, the reference voltage adjusting unit 12 selects a corresponding reference voltage among the plurality of reference voltages as the gate reference voltage according to the voltage magnitude of the input signal through a first switch control signal that is an inverted signal of the desired voltage domain signal and a second switch control signal that is an inverted signal of the first switch control signal.
The hysteresis generating unit 13 is configured to generate a hysteresis output signal according to the determined gate reference voltage. In some embodiments, the hysteresis generating unit 13 generates the hysteresis output signal changed from the low level to the high level when the input signal is greater than the first input threshold voltage associated with the first reference voltage during the change of the input signal from the low level to the high level. Further, the hysteresis generating unit 13 generates a hysteresis output signal varying from a high level to a low level when the input signal is less than a second input threshold voltage associated with a third reference voltage during the input signal varying from the high level to the low level, the first input threshold voltage being greater than the second input threshold voltage.
The signal output unit 14 is configured to gain adjust the hysteretic output signal to output a desired voltage domain signal, the voltage domain of the input signal being lower than the voltage domain of the desired voltage domain signal. For example, the input signal may be an input signal of a low voltage domain of 1.2V or 1.8V, and the voltage of the desired voltage domain signal refers to an AVCC voltage domain signal, such as 5V.
Fig. 2 shows a schematic circuit diagram of an input interface circuit according to an embodiment of the present application. As shown in FIG. 2, the reference voltage includes a first reference voltage V ref_h A second reference voltage V ref_m And a third reference voltage V ref_l 。
Wherein the first reference voltage V ref_h Is higher than the second reference voltage V ref_m Said secondReference voltage V ref_m Higher than the third reference voltage V ref_l 。
As shown in fig. 2, the reference voltage generating unit 11 includes: the circuit comprises an operational amplifier I0, a first MOS tube M1, a second MOS tube M2, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4.
The first reference voltage V ref_h Through a loop current, a first equivalent resistance value, a threshold voltage of the second MOS transistor M2 and the reference voltage V ref Determining; the first equivalent resistance value is the sum of series resistance values of the second resistor R2, the third resistor R3, and the fourth resistor R4.
The second reference voltage V ref_m Through the loop current, the second equivalent resistance value, the threshold voltage of the second MOS transistor M2 and the reference voltage V ref Determining; the second equivalent resistance value is the sum of the series resistance values of the third resistor R3 and the fourth resistor R4.
The third reference voltage V ref L is determined by a loop current, a third equivalent resistance value, a threshold voltage of the second MOS transistor M2 and the reference voltage Vref; the third equivalent resistance value is the resistance value of the fourth resistor R4.
Specifically, the second resistor R2 and the third resistor R3 have the same resistance value, and the first reference voltage is expressed as: v ref_h ＝I1*(R2+R3+R4)+V th2 +V ref (ii) a The second reference voltage is represented as: v ref_m ＝I1*(R3+R4)+V th2 +V ref (ii) a The third reference voltage is represented as: v ref_l ＝I1*R4+V th2 +V ref The gate voltage of the fourth MOS transistor M4 is determined by the states of the switches in the reference voltage adjusting unit 12.
The loop current is a current in a loop formed by the operational amplifier I0, the PMOS transistor M1, the resistors R1, R2, R3, R4, R5, and the NMOS transistor M2 shown in fig. 2, and is represented by I1.
As shown in fig. 2, the reference voltage adjusting unit 12 includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5 and a sixth switch S6.
The first switch S1, the second switch S2 and the third switch S3 form a first adjusting unit, and the first adjusting unit is controlled to be turned on and off by a first switch control signal ENA.
The fourth switch S4, the fifth switch S5 and the sixth switch S6 form a second adjusting unit, and the second adjusting unit is controlled to be turned on and off by a second switch control signal ENB.
In one embodiment, when the INPUT signal INPUT is in different states, the gate reference voltages of the INPUT transistors of the INPUT interface circuit are different:
in response to the INPUT signal INPUT being in the first state, the first switch control signal controls the first adjusting unit to be turned on, the second switch control signal controls the second adjusting unit to be turned off, and the gate reference voltage of the INPUT tube of the INPUT interface circuit is switched to the first reference voltage.
In response to the INPUT signal INPUT being in the second state, the second switching control signal controls the second adjusting unit to be turned on, the first switching control signal controls the first adjusting unit to be turned off, and the gate reference voltage of the INPUT tube of the INPUT interface circuit is switched to the third reference voltage.
As shown in fig. 2, the hysteresis generating unit 13 includes a third MOS transistor M3 and a fourth MOS transistor M4 electrically coupled in series with each other between a power supply terminal and the input signal; the fourth MOS transistor M4 is an INPUT transistor of the INPUT interface circuit, and the INPUT signal INPUT is INPUT to the INPUT interface circuit through a source of the fourth MOS transistor M4.
In response to the INPUT signal INPUT being in the first state, the drain of the third MOS transistor M3 INPUTs a first voltage, and generates the first switch control signal ENA and the second switch control signal ENB according to the first voltage.
In response to the INPUT signal INPUT being in a second state, the drain of the third MOS transistor M3 INPUTs a second voltage, and generates the first switch control signal ENA and the second switch control signal ENB with opposite levels according to the second voltage; wherein the first voltage is lower than the second voltage.
Specifically, when the INPUT signal INPUT is in the first state, i.e., the INPUT signal INPUT is low, the drain of the third MOS transistor M3 is low, at this time, the first switch control signal ENA is high, the second switch control signal ENB is low, the gate reference voltage of the fourth MOS transistor M4 is the first reference voltage Vref _ h, when the INPUT signal INPUT is in the second state, i.e., the INPUT signal INPUT changes from low to high, the INPUT signal voltage is greater than Vref _ h-Vth4, the fourth MOS transistor M4 is turned off, the drain of the third MOS transistor M3 is slowly raised to VCC, the first switch control signal ENA changes from high to low, the second switch control signal ENB changes from low to high, the capacitor (capacitor C1 in fig. 2 or capacitor C4 in fig. 3) is reversed, the reference voltage of the fourth MOS transistor M4 changes to Vref _ l, when the INPUT signal voltage changes from high to low, the INPUT signal voltage is lower than Vref _ l-Vref, the fourth MOS transistor M4 is turned on, the drain of the third MOS transistor M3 is turned on, and the drain of the low MOS transistor M3 is controlled by the INPUT angle threshold value Vref, which is achieved by the low process.
As shown in fig. 2, the signal output unit 14 includes a first inverter I1 and a second inverter I2. The first inverter I1 and the second inverter I2 are connected in series, and the first switch control signal ENA is output from an output end of the first inverter I1; a second switching control signal ENB inverted from the first switching control signal ENA is output from an output terminal of the second inverter I2. At this time, the output terminal of the second inverter I2 also outputs the desired voltage domain signal YP in phase with the input signal.
As shown in fig. 2, the reference voltage adjusting unit further includes a capacitor C1. The capacitor C1 is connected in series between the first switch S1 and the second switch S2, and is configured to shorten a stabilization time of the gate of the input tube M4 when the gate reference voltage of the input tube M4 of the input interface circuit is switched to a different reference voltage.
In response to the first switch control signal ENA, a first terminal and a second terminal of the capacitor C1 are electrically coupled to the first reference voltage Vref _ h and the second reference voltage Vref _ M, respectively, and the first terminal is electrically coupled to the gate of the input tube M4; and in response to the second switch control signal ENB, the first and second terminals of the capacitor C1 are electrically coupled to the second and third reference voltages Vref _ M and Vref _ l, respectively, and the second terminal is electrically coupled to the gate of the input tube M4.
Fig. 3 shows a circuit schematic of an input interface circuit according to another embodiment of the present application. As shown in fig. 3, the signal output unit further includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter.
The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series;
the hysteresis output signal is input by the first inverter and passes through the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter in sequence to output the expected voltage domain signal; wherein the sixth inverter outputs the second switching control signal, and the seventh inverter outputs the first switching control signal.
As shown in fig. 3, the reference voltage adjusting unit further includes a capacitor C4. The capacitor C4 is connected in series between the first switch S1 and the second switch S2, and is configured to shorten a settling time of a gate of an input tube M4 of the input interface circuit when the gate reference voltage of the input tube M4 is switched to a different reference voltage.
In response to the first switch control signal ENA, a first terminal and a second terminal of the capacitor C4 are electrically coupled to the first reference voltage Vref _ h and the second reference voltage Vref _ M, respectively, and the first terminal is electrically coupled to the gate of the input tube M4; and in response to the second switch control signal ENB, the first and second terminals of the capacitor C4 are electrically coupled to the second and third reference voltages Vref _ M and Vref _ l, respectively, and the second terminal is electrically coupled to the gate of the input tube M4.
As shown in fig. 3, the reference voltage adjusting unit further includes a resistor R0 and capacitors C0 to C3. One end of the resistor R0 is connected to one end of the capacitor C0, the other end is connected to the gate of M1, and the other end of the capacitor C0 is connected to the drain of M1. R0 and C0 are stability compensation RC of a loop formed by the operational amplifier I0, MOS tubes M1 and M2 and resistors R1-R5. Loop stability compensation may also be achieved in other ways. The capacitor C1, the capacitor C2, and the capacitor C3 serve as decoupling capacitors when the reference voltages Vref _ h, vref _ m, and Vref _ l are output, respectively.
Specifically, in conjunction with fig. 3, the hysteresis window independent of the power supply and process corner is implemented by a circuit, and the whole process is as follows:
1. firstly, reference input voltage V ref Three reference voltages Vref _ h, vref _ M and Vref _ l are generated by a loop of the resistors R1-R4 through the operational amplifier I0 and the MOS transistors M1 and M2, and the grid voltage of M4 is determined by the states of the switches S1-S6.
2. The following of the input logic level is achieved by matching M1 and M3 with M2 and M4, i.e., (W1/L1)/(W3/L3) = (W2/L2)/(W4/L4). Wherein, W1, W2, W3, W4 respectively represent the width (width) of the channel of M1, M2, M3, M4, L1, L2, L3, L4 respectively represent the length (length) of the channel of M1, M2, M3, M4, and the ratio of the two represents the ratio of the width to the length of the channel.
When the INPUT signal voltage INPUT is at a high level, M4 is turned off, the second switch control signal ENB is at a high level, vref _ l is directly connected to the gate of M4, and the charge Q1= V across the capacitor C4 at this time ref_m -V ref_l (= I1 × R2), when the input voltage of the input signal decreases from the high level to the low level, when (V) gs4 -V th4 )＝I1*R4+V th2 +V ref -V in -V th4 >At 0, since M1 and M3 match M2 and M4, then V th2 ≈V th4 Then the input low threshold voltage is V ref + I1R 4, M4 starts to conduct, the drain voltage of M4 is reduced, when the drain voltage of M4 is reduced to the AND gateWhen the voltage level of the capacitor C4 is at a logic low level, the AND gate outputs a high level, the gain is increased through the multi-stage NOT gate, the first switch control signal ENA output by the inverter I7 is at a high level, at the moment, vref _ h is directly connected to the grid electrode of M4, at the moment, the two pole plates of the capacitor C4 are inverted, the charge on the capacitor C4 is transferred to the grid electrode of M4, and the grid electrode of M4 can be accelerated to be stabilized to V ref_h When the input voltage of the input signal rises from low to high, when (V) gs4 -V th4 )＝I1(R2+R3+R4)+Vt h2 +V ref -V in -V th4 >At 0 time, due to V th2 ≈V th4 Then the input high threshold voltage is V ref + I1 (R2 + R3+ R4), a higher level is needed to turn off M4, thereby creating a hysteresis window that compensates for the fet threshold variation and has little effect on the supply voltage.
In one embodiment, in combination with the circuits shown in fig. 2 or fig. 3, the input interface circuit is connected to an external digital circuit, and transmits the output desired voltage domain signal to the external digital circuit.
The chip provided by the application comprises the input interface circuit described in the above embodiment. The input interface circuit includes: a reference voltage generating unit configured to generate different plurality of reference voltages using a reference input voltage; a reference voltage adjustment unit configured to determine a respective reference voltage of the plurality of reference voltages as a gate reference voltage of an input tube of the input interface circuit according to a voltage of an input signal; a hysteresis generation unit configured to generate a hysteresis output signal according to the determined gate reference voltage; and a signal output unit configured to gain-adjust the hysteretic output signal to output a desired voltage domain signal, the voltage domain of the input signal being lower than the voltage domain of the desired voltage domain signal.
The description of the structures corresponding to the above drawings has emphasis, and for parts of a certain structure that are not described in detail, reference may be made to the description of other structures.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.
Claims (15)
1. An input interface circuit, comprising:
a reference voltage generating unit configured to generate different plurality of reference voltages using a reference input voltage;
a reference voltage adjustment unit configured to determine a respective reference voltage of the plurality of reference voltages as a gate reference voltage of an input tube of the input interface circuit according to a voltage of an input signal;
a hysteresis generation unit configured to generate a hysteresis output signal according to the determined gate reference voltage; and
a signal output unit configured to gain-adjust the hysteretic output signal to output a desired voltage domain signal, the voltage domain of the input signal being lower than the voltage domain of the desired voltage domain signal.
2. The input interface circuit of claim 1,
the plurality of reference voltages include a first reference voltage, a second reference voltage, and a third reference voltage, the first reference voltage being greater than the second reference voltage, the second reference voltage being greater than the third reference voltage.
3. The input interface circuit of claim 2, wherein the hysteresis generation unit is configured to:
generating the hysteretic output signal varying from a low level to a high level when the input signal is greater than a first input threshold voltage associated with the first reference voltage during a low to high level transition of the input signal; and
generating the hysteretic output signal varying from a high level to a low level when the input signal is less than a second input threshold voltage associated with the third reference voltage during a transition of the input signal from a high level to a low level, the first input threshold voltage being greater than the second input threshold voltage.
4. The input interface circuit of claim 2, wherein the reference voltage adjustment unit is configured to select a respective reference voltage of the plurality of reference voltages as the gate reference voltage according to a voltage magnitude of the input signal by a first switch control signal that is an inverse of the desired voltage domain signal and a second switch control signal that is an inverse of the first switch control signal.
5. The input interface circuit according to claim 2, wherein the reference voltage generating unit comprises: the transistor comprises an operational amplifier, a first MOS transistor, a second MOS transistor, a first resistor, a second resistor, a third resistor and a fourth resistor;
the first reference voltage is determined by a loop current, a first equivalent resistance value, a threshold voltage of the second MOS transistor and the reference input voltage, and the first equivalent resistance value is the sum of series resistance values of the second resistor, the third resistor and the fourth resistor;
the second reference voltage is determined by the loop current, a second equivalent resistance value, a threshold voltage of the second MOS transistor and the reference input voltage, and the second equivalent resistance value is the sum of series resistance values of the third resistor and the fourth resistor;
the third reference voltage is determined by the loop current, a third equivalent resistance value, the threshold voltage of the second MOS transistor, and the reference input voltage, and the third equivalent resistance value is the resistance value of the fourth resistor.
6. The input interface circuit of claim 5, wherein the first MOS transistor, the first resistor, the second resistor, the third resistor, the second MOS transistor, and the fourth resistor are electrically coupled in series with each other between a power supply terminal and a forward input terminal of the operational amplifier;
a negative input terminal of the operational amplifier receives the reference input voltage, and an output terminal of the operational amplifier is electrically coupled to a grid electrode of the first MOS tube;
the grid electrode of the second MOS tube is electrically coupled to the drain electrode of the second MOS tube and the third resistor.
7. The input interface circuit of claim 4, wherein the reference voltage adjustment unit comprises: a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch;
the first switch, the second switch and the third switch form a first adjusting unit, and the first adjusting unit is controlled to be switched on and off by a first switch control signal;
the fourth switch, the fifth switch and the sixth switch form a second adjusting unit, and a second switch control signal controls the second adjusting unit to be switched on and off.
8. The input interface circuit of claim 7,
responding to the input signal in a first state, the first switch control signal controls the first adjusting unit to be switched on, the second switch control signal controls the second adjusting unit to be switched off, and the grid reference voltage of an input tube of the input interface circuit is switched to the first reference voltage;
and responding to the second state of the input signal, the second switch control signal controls the second adjusting unit to be switched on, the first switch control signal controls the first adjusting unit to be switched off, and the grid reference voltage of the input tube of the input interface circuit is switched to the third reference voltage.
9. The input interface circuit of claim 7, wherein the reference voltage adjustment unit further comprises: a capacitor configured to:
in response to the first switch control signal, a first terminal and a second terminal of the capacitor are electrically coupled to the first reference voltage and the second reference voltage, respectively, and the first terminal is electrically coupled to a gate of the input tube; and
in response to the second switch control signal, the first and second terminals of the capacitor are electrically coupled to the second and third reference voltages, respectively, and the second terminal is electrically coupled to a gate of the input tube.
10. The input interface circuit of claim 7, wherein the hysteresis generation unit comprises a third MOS transistor and a fourth MOS transistor electrically coupled in series with each other between a power supply terminal and the input signal;
the source electrode of the third MOS tube is electrically coupled to the power supply terminal, and the drain electrode of the third MOS tube is electrically coupled to the drain electrode of the fourth MOS tube;
the fourth MOS transistor is an input transistor of the input interface circuit, the input signal is input into the input interface circuit via a source electrode of the fourth MOS transistor, and the hysteretic output signal is generated at drain electrodes of the third MOS transistor and the fourth MOS transistor.
11. The input interface circuit of claim 10, wherein in response to the input signal being in a first state, a first voltage is generated at the drains of the third MOS transistor and the fourth MOS transistor, and the first switch control signal and the second switch control signal are generated with opposite levels from each other according to the first voltage;
in response to the input signal being in a second state, a second voltage is generated at the drains of the third MOS transistor and the fourth MOS transistor, and the first switch control signal and the second switch control signal are generated according to the second voltage, wherein the levels of the first switch control signal and the second switch control signal are opposite to each other, and the first voltage is lower than the second voltage.
12. The input interface circuit according to claim 7, wherein the signal output unit includes a first inverter and a second inverter;
the first inverter and the second inverter are connected in series, the first switch control signal is output from an output terminal of the first inverter, and the desired voltage domain signal and the second switch control signal inverted from the first switch control signal are output from an output terminal of the second inverter.
13. The input interface circuit according to claim 12, wherein the signal output unit further comprises a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter;
the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series;
the hysteresis output signal is input by the first inverter and is output as the expected voltage domain signal after sequentially passing through the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter; wherein the sixth inverter outputs the second switching control signal, and the seventh inverter outputs the first switching control signal.
14. The input interface circuit of claim 1,
the signal output unit is electrically coupled to an external digital circuit to transmit the desired voltage domain signal to the external digital circuit.
15. A chip, comprising: an input interface circuit as claimed in any one of claims 1 to 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211525914.0A CN115733482A (en) | 2022-11-30 | 2022-11-30 | Input interface circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211525914.0A CN115733482A (en) | 2022-11-30 | 2022-11-30 | Input interface circuit and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115733482A true CN115733482A (en) | 2023-03-03 |
Family
ID=85299877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211525914.0A Pending CN115733482A (en) | 2022-11-30 | 2022-11-30 | Input interface circuit and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115733482A (en) |
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2022
- 2022-11-30 CN CN202211525914.0A patent/CN115733482A/en active Pending
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