CN112331245A - Voltage selection circuit suitable for nonvolatile memory - Google Patents

Voltage selection circuit suitable for nonvolatile memory Download PDF

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Publication number
CN112331245A
CN112331245A CN202011220565.2A CN202011220565A CN112331245A CN 112331245 A CN112331245 A CN 112331245A CN 202011220565 A CN202011220565 A CN 202011220565A CN 112331245 A CN112331245 A CN 112331245A
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voltage
conversion module
level conversion
resistor
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CN112331245B (en
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唐明华
谭彩虹
肖永光
燕少安
李刚
李正
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Xiangtan University
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Xiangtan University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

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Abstract

The invention discloses a voltage selection circuit suitable for a nonvolatile memory, which comprises a high-voltage comparison circuit and a voltage selection circuit, wherein the high-voltage comparison circuit comprises a first branch circuit and a second branch circuit, the first branch circuit comprises a first resistance voltage division module, a first comparator and a first level conversion module which are sequentially connected, the second branch circuit comprises a second resistance voltage division module, a second comparator and a second level conversion module which are sequentially connected, and the voltage selection circuit comprises a third level conversion module and a transmission gate which are sequentially connected. The high-voltage comparison circuit obtains the maximum voltage of a first input voltage and a second input voltage through a first branch circuit and a second branch circuit, the maximum voltage output by the high-voltage comparison circuit is connected to the input end of the voltage selection circuit, and the voltage is selected through the combined action of a third level conversion module, a transmission gate and a selection control signal; the circuit has the advantages of simple structure, wide voltage application range, high response speed and high output precision.

Description

Voltage selection circuit suitable for nonvolatile memory
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a voltage selection circuit suitable for a nonvolatile memory.
Background
In non-volatile memory applications, such as EERPOM, FLASH, MTP, high voltages are needed for erase-write programming, which can be up to tens of volts, and the voltage values also need to change accordingly in different operating states, which may be the switching between high voltage and low voltage, or the switching between two signals with smaller voltage difference, so that the use of a voltage selection circuit is unavoidable. In a conventional voltage selection circuit, such as the classical alternative circuit shown in fig. 1, the inverter I1, the transmission gates I2 and I3 switch the voltage according to whether the transistors are turned on or off, but when the input voltage is much larger than the power voltage, the transmission gates cannot be cut off, so that the circuit cannot achieve the correct function.
Based on the above-mentioned problems, in the case of no additional high voltage input, considering that the large voltage of the two input voltages can be used for the control of the transmission gate, a high voltage selection circuit is required. Fig. 2 is a schematic diagram of a high voltage selection circuit in the prior art, in which a first PMOS transistor MP1 and a second PMOS transistor MP2 are used for selection, but when the difference between two input voltages V1 and V2 is small, neither MP1 nor MP2 is turned on, so that the circuit cannot select a correct high voltage.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a voltage selection circuit suitable for a nonvolatile memory, which has a simple structure, a fast response speed, and a high output accuracy.
The technical scheme for solving the problems is as follows: a voltage selection circuit suitable for a nonvolatile memory comprises a high voltage comparison circuit and a voltage selection circuit, the high-voltage comparison circuit comprises a first branch circuit and a second branch circuit, the first branch circuit comprises a first resistance voltage division module, a first comparator and a first level conversion module which are connected in sequence, the second branch circuit comprises a second resistance voltage division module, a second comparator and a second level conversion module which are connected in sequence, the input ends of the first resistance voltage division module and the second resistance voltage division module are connected with a first input voltage and a second input voltage, the voltage selection circuit comprises a third level conversion module and a transmission gate which are sequentially connected, wherein the input end of the third level conversion module is connected with the output end of the first level conversion module and the output end of the second level conversion module, and the output end of the third level conversion module outputs a selection signal after passing through the transmission gate; the high-voltage comparison circuit obtains the maximum voltage of the first input voltage and the second input voltage through the first branch circuit and the second branch circuit, the maximum voltage output by the high-voltage comparison circuit is connected to the input end of the voltage selection circuit, and the voltage is selected through the combined action of the third level conversion module, the transmission gate and the selection control signal.
In the voltage selection circuit for the non-volatile memory, in the first branch, the first resistor voltage division module includes first to fourth resistors, a positive input terminal of the first comparator is connected to one end of the first resistor and one end of the second resistor, the other end of the first resistor is connected to the first input voltage, the other end of the second resistor is grounded, a negative input terminal of the first comparator is connected to one end of the third resistor, one end of a fourth resistor is connected, the other end of the third resistor is connected with a second input voltage, the other end of the fourth resistor is grounded, the output end of the first comparator is connected with the VSEL port of the first level conversion module, the VIN port of the first level conversion module is connected with the first input voltage, the VOUT _ N port of the first level conversion module is suspended, the VOUT port of the first level conversion module is connected with the grid electrode of a third PMOS tube, and the source electrode of the third PMOS tube is connected with the second input voltage.
In the above voltage selection circuit for a non-volatile memory, in the second branch, the second resistor voltage division module includes fifth to eighth resistors, a positive input terminal of the second comparator is connected to one end of the fifth resistor and one end of the sixth resistor, the other end of the fifth resistor is connected to the second input voltage, the other end of the sixth resistor is grounded, a negative input terminal of the second comparator is connected to one end of the seventh resistor and one end of the eighth resistor, the other end of the seventh resistor is connected to the first input voltage, the other end of the eighth resistor is grounded, an output terminal of the second comparator is connected to a VSEL port of the second level conversion module, a VIN port of the second level conversion module is connected to the second input voltage, a VOUT _ N port of the second level conversion module is suspended, a VOUT port of the second level conversion module is connected to a gate of the fourth PMOS transistor, and a source of the fourth PMOS transistor is connected to the first input voltage, and the drain electrode of the fourth PMOS tube and the drain electrode of the third PMOS tube are connected together and used as the output end of the high-voltage comparison circuit.
In the voltage selection circuit suitable for the nonvolatile memory, a VSEL port of a third level conversion module is connected with a selection control signal, a VIN port of the third level conversion module is connected with an output end of a high-voltage comparison circuit, a transmission gate comprises a first NMOS transistor, a second NMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor, the VOUT port of the third level conversion module is connected with the grid electrode of the fifth PMOS tube and the grid electrode of the second NMOS tube, the VOUT _ N port of the third level conversion module is connected with the grid electrode of the first NMOS tube and the grid electrode of the sixth PMOS tube, the source electrode of the first NMOS tube and the source electrode of the fifth PMOS tube are connected together and connected with a second input voltage, the source electrode of the second NMOS tube and the source electrode of the sixth PMOS tube are connected together and connected with a first input voltage, and the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube are connected together and used as the output end of the voltage selection circuit to output the selected voltage.
The voltage selection circuit for the non-volatile memory comprises a first level conversion module, a second level conversion module and a third level conversion module, wherein the first level conversion module comprises a second phase inverter, a third NMOS transistor, a fourth NMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor, the input end of the second phase inverter is used as a VSEL port of the first level conversion module, the output end of the second phase inverter is connected with the input end of the third phase inverter and the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the output end of the third phase inverter is connected with the gate of the third NMOS transistor, the source of the third NMOS transistor is grounded, the drain of the third NMOS transistor, the drain of the seventh PMOS transistor and the gate of the eighth PMOS transistor are connected together and used as a VOUT _ N port of the first level conversion module, the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are connected together and used as a VIN port of the first level conversion module, and the drain electrode of the eighth PMOS tube, the grid electrode of the seventh PMOS tube and the drain electrode of the fourth NMOS tube are connected together and are used as a VOUT port of the first level conversion module.
The invention has the beneficial effects that:
1. the high-voltage comparator circuit obtains the maximum voltage of the first input voltage and the second input voltage through the first branch circuit and the second branch circuit, the maximum voltage output by the high-voltage comparator circuit is connected to the input end of the voltage selection circuit, and the voltage is selected through the combined action of the third level conversion module, the transmission gate and the selection control signal.
2. The invention has wide applicable input voltage range, and no matter the difference value of the input voltages is too large or too small, the phenomena of electric leakage and the like can not occur, wherein the large voltage range between the two input voltages is from the minimum conduction voltage of an MOS tube to the breakdown voltage of the MOS tube, and the small voltage can be as low as 0V, thereby solving the problem that the output voltage of the existing voltage selection circuit is inaccurate when the difference value of the two input voltages is too large or too small in a nonvolatile memory.
3. The invention has high precision, can realize accurate output of voltage as long as the difference between two input voltages is not less than 0.5mV, has high response speed, and can obtain accurate output voltage value within 10 ns.
Drawings
Fig. 1 is a circuit schematic of a classical alternative circuit.
Fig. 2 is a circuit schematic of a prior art high voltage selection circuit.
Fig. 3 is a schematic circuit diagram of the high voltage comparator circuit of the present invention.
FIG. 4 is a schematic circuit diagram of the voltage selection circuit of the present invention.
Fig. 5 is a schematic circuit diagram of the level shift module according to the present invention.
FIG. 6 is a waveform diagram of the simulation of the present invention with varying input voltage.
FIG. 7 is a waveform diagram of simulation with a small difference in input voltage according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings and examples.
A voltage selection circuit suitable for a nonvolatile memory comprises a high voltage comparison circuit and a voltage selection circuit, the high-voltage comparison circuit comprises a first branch circuit and a second branch circuit, the first branch circuit comprises a first resistance voltage division module, a first comparator and a first level conversion module which are connected in sequence, the second branch circuit comprises a second resistance voltage division module, a second comparator and a second level conversion module which are connected in sequence, the input ends of the first resistance voltage division module and the second resistance voltage division module are connected with a first input voltage and a second input voltage, the voltage selection circuit comprises a third level conversion module and a transmission gate which are sequentially connected, wherein the input end of the third level conversion module is connected with the output end of the first level conversion module and the output end of the second level conversion module, and the output end of the third level conversion module outputs a selection signal after passing through the transmission gate; the high-voltage comparison circuit obtains the maximum voltage of the first input voltage and the second input voltage through the first branch circuit and the second branch circuit, the maximum voltage output by the high-voltage comparison circuit is connected to the input end of the voltage selection circuit, and the voltage is selected through the combined action of the third level conversion module, the transmission gate and the selection control signal.
As shown in fig. 3, in the high voltage comparison circuit, the first resistance voltage division module includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, a positive input terminal of a first comparator I4 is connected to one end of a first resistor R1 and one end of a second resistor R2, the other end of the first resistor R1 is connected to the first input voltage VINA, the other end of the second resistor R2 is grounded, a negative input terminal of the first comparator I4 is connected to one end of a third resistor R3 and one end of a fourth resistor R4, the other end of the third resistor R3 is connected to the second input voltage VINB, the other end of the fourth resistor R4 is grounded, an output terminal of the first comparator I4 is connected to a VSEL port of a first level conversion module I5, a VIN port of the first level conversion module I VIN 6 is connected to the first input voltage VINA, a _ N port of the first level conversion module I5, and a floating gate VOUT _ MP port of the first level conversion module I5 is connected to a third PMOS gate 5, the source of the third PMOS transistor MP3 is connected to the second input voltage VINB.
As shown in fig. 3, the second resistance voltage dividing module includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, a positive input terminal of the second comparator I6 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, the other end of the fifth resistor R5 is connected to the second input voltage VINB, the other end of the sixth resistor R6 is grounded, a negative input terminal of the second comparator I6 is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, the other end of the seventh resistor R7 is connected to the first input voltage VINA, the other end of the eighth resistor R8 is grounded, an output terminal of the second comparator I6 is connected to the VSEL port of the second level converting module I7, the vivin port of the second level converting module I7 is connected to the second input voltage nb, the VOUT _ N port of the second level converting module I7 is connected to the floating gate terminal of the PMOS 4 of the second level converting module I7, the source of the fourth PMOS transistor MP4 is connected to the first input voltage VINA, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3 and serves as the output terminal of the high voltage comparator circuit.
As shown in fig. 4, in the voltage selection circuit, a VSEL port of a third level conversion module I8 is connected to a selection control signal SELA, a VIN port of the third level conversion module I8 is connected to an output end of the high voltage comparison circuit, the transmission gate includes a first NMOS transistor MN1, a second NMOS transistor MN2, a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6, a VOUT port of the third level conversion module I8 is connected to a gate of the fifth PMOS transistor MP5 and a gate of the second NMOS transistor MN2, a VOUT _ N port of the third level conversion module I8 is connected to a gate of the first NMOS transistor MN1 and a gate of the sixth PMOS transistor MP6, a source of the first NMOS transistor MN1 and a source of the fifth PMOS transistor MP5 are connected together and connected to a second input voltage VINB, a source of the second NMOS transistor MN2 and a source of the sixth PMOS transistor MP8 are connected together and connected to a first input voltage na, a drain of the first NMOS transistor MN1, a drain of the first NMOS transistor MN2, a drain of the second NMOS transistor MP6 and a drain of the fifth PMOS transistor MP6 are connected to a drain of the first NMOS, The drains of the sixth PMOS transistors MP6 are connected together and output the selected voltage as the output terminal of the voltage selection circuit.
The first level conversion module, the second level conversion module and the third level conversion module have the same structure. As shown in fig. 5, the first level shift module includes a second inverter I9, a third inverter I10, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a seventh PMOS transistor MP7, and an eighth PMOS transistor MP8, an input terminal of the second inverter I9 is used as a VSEL port of the first level shift module, an output terminal of the second inverter I9 is connected to an input terminal of the third inverter I10 and a gate terminal of the fourth NMOS transistor MN4, a source terminal of the fourth NMOS transistor MN4 is grounded, an output terminal of the third inverter I10 is connected to a gate terminal of the third NMOS transistor MN3, a source terminal of the third NMOS transistor MN3 is grounded, a drain terminal of the third NMOS transistor MN3, a drain terminal of the seventh PMOS transistor MP7, a gate terminal of the eighth PMOS transistor MP8 is connected together and used as a VOUT _ N port of the first level shift module, a source terminal of the seventh PMOS transistor MP7 and a source terminal of the eighth PMOS transistor MP8 are connected together and used as a drain terminal of the first level shift module, a gate terminal of the eighth PMOS transistor MP8, a gate terminal of the seventh PMOS transistor MP7, The drains of the fourth NMOS transistor MN4 are connected together and act as the VOUT port of the first level shifter module.
The working principle of the invention is as follows:
the function of the high voltage comparator circuit is to compare the maximum voltage between the first input voltage VINA and the second input voltage VINB, and the schematic diagram is shown in fig. 3. In a non-volatile memory, such as an EEPROM or a FLASH, a maximum high voltage can reach tens of volts, and a general comparator requires that the voltage values of the positive input terminal and the negative input terminal are smaller than the power supply voltage, otherwise, the comparison cannot be performed, so when the voltages of the VINA and the VINB reach tens of volts, a first resistance voltage division module composed of a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, and a second resistance voltage division module composed of a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8 are required to perform voltage division, and the voltage values after voltage division are:
Figure BDA0002761833860000081
Figure BDA0002761833860000082
Figure BDA0002761833860000083
Figure BDA0002761833860000084
wherein, V1 is the voltage at point 1 in fig. 3, V2 is the voltage at point 2, V3 is the voltage at point 3, V4 is the voltage at point 4, and the resistance values of R1 ═ R3 ═ R5 ═ R7, R2 ═ R4 ═ R6 ═ R8, after voltage division by resistors, the voltage values of V1, V2, V3, and V4 are guaranteed to be smaller than the power supply voltage of the comparator.
After voltage division is carried out on the VINA and the VINB through resistors, the voltage is respectively sent to a positive input end and a negative input end of the comparator. When VINA > VINB, the positive input voltage V1> the negative input voltage V2 of the first comparator I4, so that the output of the first comparator I4 is high and is provided to the VSEL terminal of the first Level Shift circuit I5. The Level Shift circuit, i.e. the Level Shift circuit, has an internal structure as shown in fig. 5, and is composed of a second inverter I9, a third inverter I10, two PMOS transistors MP7 and MP8, and two NMOS transistors MN3 and MN4, where VSEL is an input control signal, VIN is a converted voltage signal, and VOUT _ N are output signals with opposite states. When VSEL is low, MN3 is turned off, MN4 is turned on, so VOUT becomes 0, and MP7 is turned on, so VOUT _ N becomes VIN; when VSEL is high, MN3 turns on, MN4 turns off, VOUT _ N is 0 and connected to the gate of MP8, so MP8 turns on and VOUT is VIN.
VIN port of I5 is connected with VINA, therefore when VSEL is high level, VOUT end outputs VINA, and is connected with the grid of MP3, MP3 source is connected with VINB, because VINA>VINB, so that the gate of MP3Potential difference V with sourceGS>0, MP3 is in the off state. Meanwhile, the output of the second comparator I6 is low and is sent to the VSEL terminal of the second Level Shift circuit I6, when VSEL is equal to low Level, the output of VOUT terminal is 0 and is connected to the gate of MP4, the source of MP4 is connected to VINA due to the VINA>VINB, so that the potential difference V between the gate and the source of MP4GS<When 0, MP4 is turned on, and the output maximum voltage signal HV equals VINA. In the same way, when VINA<In VINB, MP3 is turned on, MP4 is turned off, and the maximum voltage signal HV becomes VINB.
It should be noted that the large voltage in VINA and VINB needs to be larger than the minimum on-voltage of PMOS, otherwise the potential difference | V of the gate and source of MP3, MP4GS|<L threshold voltage VTHMaking neither MP3, MP4 conductive; in addition, the large voltage in VINA and VINB needs to be smaller than the breakdown voltage of MOS transistor, otherwise the breakdown phenomenon occurs, and the small voltage in VINA and VINB can be as low as 0V.
An output signal HV of the high-voltage comparison circuit is connected to an input end of the voltage selection circuit, and the structure of the voltage selection circuit is as shown in fig. 4, and the voltage selection circuit mainly includes a third Level Shift circuit I8, a third transmission gate composed of MN1 and MP5, and a fourth transmission gate composed of MN2 and MP6, where SELA is an input selection control signal, HV is an input maximum voltage signal, VINA is a first input voltage, VINB is a second input voltage, and OUT is a circuit output voltage.
When SELA is high, the output of VOUT end of I8 is HV, and is connected to the gates of MP5 and MN 2; the output of the terminal VOUT _ N is 0, and is connected to the gates of MN1 and MP 6. The sources of MN1 and MP5 are connected to VINB due to HV>VINB, therefore MN1 and MP5 are both off. The sources of MN2 and MP6 are connected with VINA, and the potential difference | V between the gate and the source satisfies MN2 or MP6GS|>L threshold voltage VTHUnder the condition of | the fourth transmission gate is turned on, and the output voltage OUT is equal to VINA. Similarly, when SEL is low, the output from VOUT terminal of I8 is 0, and the output from VOUT _ N terminal is HV, since HV is>VINA, therefore MN2 and MP6 both turned off. The sources of MN1 and MP5 are connected to VINB, and the potential difference | V between the gate and the source is satisfied with MN1 or MP5GS|>L threshold voltage VTHUnder the condition of |The third transmission gate is turned on, and the output voltage OUT is VINB.
Simulation result
In the voltage comparison circuit, the simulated waveform when the input voltage is changed is shown in fig. 6. VINB rises from 0V to 10V in 0 μ s to 5 μ s, and falls from 10V to 0V again in 5 μ s to 10 μ s, VINA is maintained at 3V, and as can be seen from the waveform of the maximum voltage HV, when VINA > VINB, HV becomes equal to VINA; when VINA < VINB, HV ═ VINB. The output voltage OUT is controlled by the selection control signal SELA, and as can be seen from the waveform, when SELA is 3.3V, OUT is VINA; when SELA is 0V, OUT is VINB, and the voltage output is correct.
The simulated waveform when the difference between the two input voltages is small is shown in fig. 7. Since VINA is maintained at 4.0005V and VINB is maintained at 4.0V, it can be seen that the maximum voltage HV can still be compared when the difference between the two input voltages is small, and then HV is 4.0005V. The voltage value of the output signal OUT is also correct, and when SELA is 3.3V, OUT is 4.0005V, and when SELA is 0V, OUT is 4.0V.
The simulation waveform result can be analyzed to obtain that the invention has wide applicable input voltage range, can realize the selective switching between different voltages, has high circuit precision, and can output correct voltage even if the difference value between the two input voltages is as low as 0.5 mV. In addition, the response speed is high, and correct voltage output can be obtained within 10 ns.

Claims (5)

1. A voltage selection circuit for a non-volatile memory, comprising: the high-voltage power supply comprises a high-voltage comparison circuit and a voltage selection circuit, wherein the high-voltage comparison circuit comprises a first branch circuit and a second branch circuit, the first branch circuit comprises a first resistance voltage division module, a first comparator and a first level conversion module which are sequentially connected, the second branch circuit comprises a second resistance voltage division module, a second comparator and a second level conversion module which are sequentially connected, the input ends of the first resistance voltage division module and the second resistance voltage division module are respectively connected with a first input voltage and a second input voltage, the voltage selection circuit comprises a third level conversion module and a transmission gate which are sequentially connected, the input end of the third level conversion module is connected with the output end of the first level conversion module and the output end of the second level conversion module, and the output end of the third level conversion module outputs a selection signal after passing through the transmission gate; the high-voltage comparison circuit obtains the maximum voltage of the first input voltage and the second input voltage through the first branch circuit and the second branch circuit, the maximum voltage output by the high-voltage comparison circuit is connected to the input end of the voltage selection circuit, and the voltage is selected through the combined action of the third level conversion module, the transmission gate and the selection control signal.
2. The voltage selection circuit for a non-volatile memory as claimed in claim 1, wherein: in the first branch circuit, the first resistor voltage division module comprises first to fourth resistors, a positive input end of a first comparator is connected with one end of the first resistor and one end of the second resistor, the other end of the first resistor is connected with a first input voltage, the other end of the second resistor is grounded, a negative input end of the first comparator is connected with one end of the third resistor and one end of the fourth resistor, the other end of the third resistor is connected with a second input voltage, the other end of the fourth resistor is grounded, an output end of the first comparator is connected with a VSEL (voltage level shifter) port of the first level shifter module, a VIN (voltage input) port of the first level shifter module is connected with the first input voltage, a VOUT _ N (voltage output) port of the first level shifter module is suspended, a VOUT port of the first level shifter module is connected with a grid electrode of a third PMOS (P-channel metal oxide semiconductor) transistor, and a source electrode of.
3. The voltage selection circuit for a non-volatile memory as claimed in claim 2, wherein: in the second branch circuit, the second resistance voltage-dividing module comprises fifth to eighth resistors, the positive input end of the second comparator is connected with one end of the fifth resistor and one end of the sixth resistor, the other end of the fifth resistor is connected with the second input voltage, the other end of the sixth resistor is grounded, the negative input end of the second comparator is connected with one end of the seventh resistor, one end of an eighth resistor is connected, the other end of a seventh resistor is connected with a first input voltage, the other end of the eighth resistor is grounded, the output end of a second comparator is connected with a VSEL port of a second level conversion module, a VIN port of the second level conversion module is connected with a second input voltage, a VOUT _ N port of the second level conversion module is suspended, a VOUT port of the second level conversion module is connected with a grid electrode of a fourth PMOS tube, a source electrode of the fourth PMOS tube is connected with the first input voltage, and a drain electrode of the fourth PMOS tube is connected with a drain electrode of a third PMOS tube and serves as the output end of the high-voltage comparison circuit.
4. The voltage selection circuit for a non-volatile memory as claimed in claim 3, wherein: in the voltage selection circuit, a VSEL port of a third level conversion module is connected with a selection control signal, a VIN port of the third level conversion module is connected with the output end of the high-voltage comparison circuit, a transmission gate comprises a first NMOS tube, a second NMOS tube, a fifth PMOS tube and a sixth PMOS tube, the VOUT port of the third level conversion module is connected with the grid electrode of the fifth PMOS tube and the grid electrode of the second NMOS tube, the VOUT _ N port of the third level conversion module is connected with the grid electrode of the first NMOS tube and the grid electrode of the sixth PMOS tube, the source electrode of the first NMOS tube and the source electrode of the fifth PMOS tube are connected together and connected with a second input voltage, the source electrode of the second NMOS tube and the source electrode of the sixth PMOS tube are connected together and connected with a first input voltage, and the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube are connected together and used as the output end of the voltage selection circuit to output the selected voltage.
5. The voltage selection circuit for a non-volatile memory as claimed in claim 4, wherein: the first level conversion module, the second level conversion module and the third level conversion module have the same structure, the first level conversion module comprises a second phase inverter, a third NMOS tube, a fourth NMOS tube, a seventh PMOS tube and an eighth PMOS tube, the input end of the second phase inverter is used as a VSEL port of the first level conversion module, the output end of the second phase inverter is connected with the input end of the third phase inverter and the grid electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the output end of the third phase inverter is connected with the grid electrode of the third NMOS tube, the source electrode of the third NMOS tube is grounded, the drain electrode of the third NMOS tube, the drain electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube are connected together and used as a VOUT _ N port of the first level conversion module, the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube are connected together and used as a VIN port of the first level conversion module, the drain electrode of the eighth PMOS tube, the, And the grid electrode of the seventh PMOS tube and the drain electrode of the fourth NMOS tube are connected together and are used as a VOUT port of the first level conversion module.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114678937A (en) * 2022-04-22 2022-06-28 上海筱珈科技有限公司 Multi-battery management circuit and method
CN115167598A (en) * 2022-07-26 2022-10-11 圣邦微电子(苏州)有限责任公司 Power supply voltage selection circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847249B1 (en) * 2003-10-09 2005-01-25 Analog Devices, Inc. Highest available voltage selector circuit
CN102130492A (en) * 2010-07-31 2011-07-20 华为技术有限公司 Device and method for selecting power supply
CN104133515A (en) * 2014-07-09 2014-11-05 刘银 PMOS transistor substrate selection circuit
CN109215719A (en) * 2018-11-22 2019-01-15 四川知微传感技术有限公司 A kind of multifunctional electric switching circuit for OTP programming
CN109546998A (en) * 2019-01-22 2019-03-29 上海艾为电子技术股份有限公司 A kind of voltage selecting circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847249B1 (en) * 2003-10-09 2005-01-25 Analog Devices, Inc. Highest available voltage selector circuit
CN102130492A (en) * 2010-07-31 2011-07-20 华为技术有限公司 Device and method for selecting power supply
CN104133515A (en) * 2014-07-09 2014-11-05 刘银 PMOS transistor substrate selection circuit
CN109215719A (en) * 2018-11-22 2019-01-15 四川知微传感技术有限公司 A kind of multifunctional electric switching circuit for OTP programming
CN109546998A (en) * 2019-01-22 2019-03-29 上海艾为电子技术股份有限公司 A kind of voltage selecting circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114678937A (en) * 2022-04-22 2022-06-28 上海筱珈科技有限公司 Multi-battery management circuit and method
CN115167598A (en) * 2022-07-26 2022-10-11 圣邦微电子(苏州)有限责任公司 Power supply voltage selection circuit
CN115167598B (en) * 2022-07-26 2024-03-15 圣邦微电子(苏州)有限责任公司 Power supply voltage selection circuit

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