CN115732430A

CN115732430A - Packaging structure and packaging method of photoelectric detection chip

Info

Publication number: CN115732430A
Application number: CN202211482710.3A
Authority: CN
Inventors: 韩德俊; 刘宇霄; 杨茹
Original assignee: Beijing Normal University
Current assignee: Beijing Normal University
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2023-03-03

Abstract

The invention provides a packaging structure and a packaging method of a photoelectric detection chip, wherein the packaging structure comprises: the packaging substrate is provided with a first electrode and a second electrode on the back surface, and a first conductive bonding pad and a second conductive bonding pad on the front surface; the front side of the photoelectric detection chip, which is close to one side of the second conductive pad, and the opposite side of the front side of the photoelectric detection chip are provided with front electrodes, the back electrode is electrically connected with the first conductive pad through a first conductive connector, and the front electrode, which is close to one side of the second conductive pad, is electrically connected with the second conductive pad through a second conductive connector; the packaging insulator is at least packaged between the second conductive connecting body and the side wall of the photoelectric detection chip and between the second conductive connecting body and the non-active area on the front surface of the photoelectric detection chip; the first photoelectric detection chip and the second photoelectric detection chip are respectively attached to one side deviating from the centers of the first packaging area and the second packaging area and deviating away from the second conductive electric connector.

Description

Packaging structure and packaging method of photoelectric detection chip

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and a packaging method of a photoelectric detection chip.

Background

PET (Positron Emission Tomography) scanners are one of the most advanced nuclear medicine imaging devices today. Since SiPM (Silicon photomultiplier) has the advantages of high photon detection efficiency, low bias voltage, compactness, etc., siPM has been the best choice for PET imaging devices compared to other detection devices. For example, TSV (Through-Silicon Vias) packages have the disadvantages of high cost and technical difficulty, and conventional wire bonding has the disadvantage of large dead area, which seriously hinders the improvement of package density. The smaller the dead area, the higher the integration of the device, and the smaller the area of a single pixel, which means that it has higher resolution in practical applications. That is, the dead zone area has a significant impact on the detection efficiency.

The applicant's chinese patent application No. cn202110065307.X provides a method and a structure for packaging a photodetection chip, in which a front electrode of the photodetection chip and a substrate pad are electrically connected using silver paste, and SU-8 photoresist is used as a reliable insulating medium. The packaging structure and the packaging method can improve the efficiency of packaging photoelectric detection chips in batches; meanwhile, the dead zone area of a packaging body introduced by packaging can be obviously reduced, so that the packaging filling factor of the photoelectric detection chip is improved, the packaging filling rate can be greatly improved by the packaging mode, and compared with the TSV technology, the packaging method has the advantages of relatively simple packaging process and lower cost. However, the package structure obtained by this packaging method has problems in mounting, which are specifically shown as follows: in the aspect of structure, two devices are taken as a period, and the metal electrodes on the surfaces of the devices are required to be ensured to be pasted head to head, namely, the devices cannot be pasted in the same direction, and one half of the devices are required to rotate 180 degrees, so that a rotation angle is easy to exist during pasting, and the yield is greatly reduced. In addition, the packaging process has poor repeatability, making it difficult to apply to mass production. In addition, the prepared packaging structure has over-thin surface protection, which leads to poor reliability in severe environments. In a word, the yield of the packaging structure obtained by the packaging technology is low and difficult to promote, and the reliability is required to be improved, so that the technology cannot be well applied to mass production. Therefore, how to further improve the yield and reliability of the package structure preparation is the biggest problem to be solved to promote the development of the technology.

Disclosure of Invention

In view of the problems in the prior art, the present invention provides a novel packaging structure and packaging method for a photo-detection chip, so as to improve the yield and reliability of the photo-detection chip.

According to an aspect of the present invention, there is provided a package structure of a photodetecting chip,

the package structure includes: the photoelectric detection device comprises a packaging substrate, a photoelectric detection chip attached to the packaging substrate, a packaging insulator, a protective layer coated on the photoelectric detection chip and a conductive connecting body for electrically connecting the photoelectric detection chip and the packaging substrate; the back surface of the packaging substrate is provided with a first electrode and a second electrode, the front surface of the packaging substrate is provided with a first conductive bonding pad and a second conductive bonding pad, the first conductive bonding pad is connected with the first electrode through a first conductive through hole, and the second conductive bonding pad is connected with the second electrode through a second conductive through hole; the method is characterized in that:

the photoelectric detection chip comprises a first photoelectric detection chip and a second photoelectric detection chip, wherein front electrodes are arranged on one sides of the front surfaces of the first photoelectric detection chip and the second photoelectric detection chip, which are close to the second conductive pad, and opposite sides of the front surfaces of the first photoelectric detection chip and the second photoelectric detection chip, back electrodes are arranged on the back surfaces of the first photoelectric detection chip and the second photoelectric detection chip, the back electrodes are electrically connected with the first conductive pad through a first conductive connector, and the front electrodes on one sides of the photoelectric detection chip, which are close to the second conductive pad, are electrically connected with the second conductive pad through a second conductive connector;

the packaging insulator is at least packaged between the second conductive connector and the side wall of the photoelectric detection chip and between the second conductive connector and the inactive area of the front surface of the photoelectric detection chip, so that the second conductive connector is electrically isolated from the side wall of the photoelectric detection chip and the second conductive connector is electrically isolated from the inactive area of the front surface of the photoelectric detection chip;

the packaging substrate comprises a first packaging area and a second packaging area which are connected and symmetrically arranged, and the first photoelectric detection chip and the second photoelectric detection chip are respectively attached to the first packaging area and the second packaging area, deviate from the centers of the first packaging area and the second packaging area and deviate from one side far away from the second conductive electric connector.

In some embodiments of the present invention, the second conductive connector crosses over a sidewall of the package insulator to connect with the front electrode of the photodetecting chip and the second conductive pad, the second conductive connector is further electrically isolated from the back electrode of the photodetecting chip; the second conductive connector is conductive silver glue or conductive silver paste made of spherical silver particles.

In some embodiments of the present invention, the package insulator is attached to a package substrate, and a window is left on the second conductive pad; the second conductive connector fills a window on the second conductive pad.

In some embodiments of the present invention, an insulating medium covers the top of the second conductive via, and the insulating medium isolates the first conductive pad from the second conductive pad; the insulating medium is light imaging solder resist ink; the encapsulation insulator also covers a partial area of the front side of the photo-imageable solder resist ink so that the second conductive connector is isolated from the back electrode of the photodetecting chip.

In some embodiments of the present invention, the first conductive connector is a conductive silver paste or silver paste made of spherical silver particles; the packaging insulator is an epoxy insulator structure formed on the packaging substrate after the photoresist is processed by utilizing a photoetching technology; the epoxy type insulating structure covers the side surface and part or all of the non-active area of the edge of the upper surface of the photoelectric detection chip; the protective layer is an insulating organic silicon pouring sealant protective layer, and the thickness of the protective layer is 200-400 mu m.

In another aspect of the present invention, a method for packaging a photodetecting chip is further provided, the method comprising the following steps:

a first package substrate forming step: mounting a photoelectric detection chip on a pre-prepared packaging substrate to form a first packaging base body, so that the back surface of the photoelectric detection chip is attached to the front surface of the packaging substrate, wherein the back surface of the packaging substrate is provided with a first electrode and a second electrode, the front surface of the packaging substrate is provided with a first conductive bonding pad and a second conductive bonding pad, the first conductive bonding pad is connected with the first electrode through a first conductive through hole, and the second conductive bonding pad is connected with the second electrode through a second conductive through hole; the packaging substrate comprises a first packaging area and a second packaging area which are connected and symmetrically arranged, and the first photoelectric detection chip and the second photoelectric detection chip are respectively attached to the first packaging area and the second packaging area, deviate from the centers of the first packaging area and the second packaging area and deviate from one side far away from the second conductive electric connector; the photoelectric detection chip comprises a first photoelectric detection chip and a second photoelectric detection chip, wherein front electrodes are arranged on one sides of the front surfaces of the first photoelectric detection chip and the second photoelectric detection chip, which are close to the second conductive pad, and opposite sides of the front surfaces of the first photoelectric detection chip and the second photoelectric detection chip, back electrodes are arranged on the back surfaces of the first photoelectric detection chip and the second photoelectric detection chip, the back electrodes are electrically connected with the first conductive pad through a first conductive connector, and the front electrodes on one sides of the photoelectric detection chip, which are close to the second conductive pad, are electrically connected with the second conductive pad through a second conductive connector;

a second package substrate forming step: forming a patterned packaging insulator on the first packaging substrate by utilizing a photoetching technology to obtain a second packaging substrate comprising the first packaging substrate and the packaging insulator, so that the packaging insulator partially covers the side wall of the photoelectric detection chip and the non-active area on the front surface of the photoelectric detection chip;

a third package base forming step: forming a second conductive connector on the second package substrate along at least a part of the surface of the package insulator to connect the front electrode of the photodetection chip with the second conductive pad, thereby obtaining a third package substrate including the second package substrate and the second conductive connector;

a packaging unit forming step: and coating a protective layer on the third packaging substrate to obtain the packaging structure of the photoelectric detection chip.

In some embodiments of the present invention, the second package base forming step includes: coating photoresist on the first packaging substrate; soft baking the coated photoresist; coating the photoresist again; soft baking the recoated photoresist; exposing and post-baking the packaging substrate by using a mask; and developing and hardening the packaging substrate to obtain the packaging insulator.

In some embodiments of the present invention, the first package base formed in the first package base forming step includes a photo-detecting chip array formed of a plurality of photo-detecting chips attached to the package substrate; in the second packaging substrate forming step, when the first packaging substrate is coated with the photoresist, the photoresist is coated twice to enable the photoresist to uniformly cover the photoelectric detection surface of the chip and the interval between adjacent chips; the packaging structure of the photoelectric detection chip formed in the packaging unit forming step is a packaging structure of a photoelectric detection chip array; the method further comprises the following steps: and cutting the packaging structure of the photoelectric detection chip array to form a plurality of independent photoelectric detection chip packaging units.

In some embodiments of the present invention, before the first package base forming step, the method further comprises: and (3) adopting a thin metal layer for evaporation and photoetching corrosion to manufacture an alignment mark on the packaging substrate for mounting the photoelectric detection chip.

In another aspect of the present invention, there is also provided a packaging structure of a photodetecting chip prepared according to the above packaging method of photodetecting chips.

The packaging structure and the packaging method of the photoelectric detection chip can reduce the chip mounting error caused by rotating the photoelectric detection chip, greatly reduce the process complexity and increase the yield of finished products.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.

It will be appreciated by those skilled in the art that the objects and advantages that can be achieved with the present invention are not limited to the specific details set forth above, and that these and other objects that can be achieved with the present invention will be more clearly understood from the detailed description that follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. For purposes of illustrating and describing some portions of the present invention, corresponding parts of the drawings may be exaggerated, i.e., may be larger, relative to other components in an exemplary apparatus actually manufactured according to the present invention. In the drawings:

fig. 1 is a cross-sectional view of a photodetection chip package structure according to an embodiment of the present invention.

Fig. 2A is a schematic top view of a package substrate of a photodetecting chip according to an embodiment of the present invention.

Fig. 2B is a schematic top view of a back surface of a package substrate of a photodetection chip according to an embodiment of the present invention.

Fig. 3 is a flowchart of a method for packaging a photodetection chip according to an embodiment of the present invention.

Fig. 4 is a schematic top view of a front surface of a first package substrate according to an embodiment of the invention.

Fig. 5 is a cross-sectional view of a first package substrate according to an embodiment of the invention.

Fig. 6 is a schematic top view of a front surface of a second package substrate according to an embodiment of the invention.

Fig. 7 is a cross-sectional view of a second package substrate according to an embodiment of the invention.

Fig. 8 is a schematic top view of a front surface of a third package substrate according to an embodiment of the invention.

Fig. 9 is a cross-sectional view of a third package substrate in accordance with an embodiment of the present invention.

Fig. 10 is a cross-sectional view of the final packaged unit in accordance with an embodiment of the present invention.

Description of reference numerals:

10: a package substrate; 20: a front side first conductive pad; 30: a first conductive via;

40: a back first electrode; 50: insulating solder resist ink; 60: a front second conductive pad;

70: a second conductive via; 80: a back second electrode; 90: a photoelectric detection chip;

100: a back electrode of the chip; 110: a first conductive connector; 120: a chip front electrode;

130: an SU-8 package insulator; 140: a second conductive connector; 150: an organic silicon pouring sealant protective layer; 160: cutting a channel; 170: and the chip is an active area.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.

It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.

It should be emphasized that the term "comprises/comprising/comprises/having" when used herein, is taken to specify the presence of stated features, elements, steps or components, but does not preclude the presence or addition of one or more other features, elements, steps or components. It is also noted herein that the term "coupled," if not specifically stated, may refer herein to not only a direct connection, but also an indirect connection in which an intermediate is present.

The embodiment of the invention improves the existing packaging structure of the photoelectric detection chip and provides a novel packaging structure of the photoelectric detection chip. As shown in fig. 1, the package structure includes: a package substrate 10, a photo-detecting chip (chip for short) 90, a package insulator 130, a protection layer 150, and

conductive connectors

110 and 140 electrically connecting the photo-detecting chip 90 and the package substrate 10. The photo detection chip 90 is attached to the front surface of the package substrate 10, that is, the back surface of the photo detection chip is attached to the front surface of the package substrate. The back electrode 100 of the photodetection chip 90 is electrically connected and fixed to the first conductive pad 20 on the front side of the package substrate through the first conductive connector 110, and the front electrode 120 of the photodetection chip 90 is electrically connected to the second conductive pad 60 through the second conductive connector 140. As shown in fig. 1, 2A and 2B, the front surface of the package substrate 10 has a first conductive pad 20 and a second conductive pad 60, the back surface of the package substrate 10 has a first electrode 40 and a second electrode 80, the first conductive pad 20 and the first electrode 40 are connected by a first conductive via 30, and the second conductive pad 60 and the second electrode 80 are connected by a second conductive via 70. In fig. 2A, a wiring region defined by oblique lines is copper-plated, and a solid-line square region in the region is exposed with copper, and the exposed copper portion serves as a second conductive pad 60. The second conductive pad 60 may then be electrically connected to the second electrode 80 on the back side of the package substrate 10 through the second conductive via 70. In the examples shown in fig. 2A and 2B, the shapes and positions of the first and second

conductive pads

20 and 60, the shapes and positions of the first and

second electrodes

40 and 80, and the positions of the first and second

conductive vias

30 and 70 are merely examples, and the

conductive pads

20 and 60, and the

electrodes

40 and 80 may each have other shapes and may be arranged at other positions as appropriate, and the conductive vias may be arranged at other positions as appropriate. In the embodiment of the present invention, the package substrate 10 may be manufactured by using a mature Printed Circuit Board (PCB) manufacturing process, or may be manufactured by using a through-hole silicon (TSV) process.

Further, in the example of the front surface of the package substrate 10 shown in fig. 2A, the area around the first conductive pad 20 and the second conductive pad 60 and the area around the second conductive via 70 may be covered with an insulating medium 50, and the insulating medium 50 is used to isolate the first conductive pad 20 from the second conductive pad 60, and also isolate the second conductive via 70 from the back electrode 100 of the photodetecting chip. In one embodiment of the present invention, the insulating medium 50 is photo-imageable solder resist ink with excellent insulating properties, or other insulating medium with good insulating properties. The second conductive pad 60 may be partially blocked by the insulating dielectric 50 to expose only a portion of the second conductive pad 60, see fig. 4. The copper-laid area between the second conductive pad 60 and the second conductive via 70 is covered by the insulating medium 50.

In the existing package of the photodetection chip, two photodetection chips are used as a cycle, i.e. a package unit is packaged, because the existing photodetection chip is provided with the front electrode 120 only on one side of the front surface, and the front electrodes 120 of the two photodetection chips are electrically connected to the second conductive pad 60 between the two chips through the second conductive connector 140, it is necessary to ensure that the metal electrodes (front electrodes) on the surfaces of the two photodetection chips are mounted "head-to-head" in mounting, i.e. the photodetection chips cannot be mounted in the same direction, so that half of the photodetection chips need to be rotated by 180 ° in advance in mounting, which results in relatively complex process, and the rotation angle easily occurs during mounting, so that the front electrodes are difficult to be positioned at the predetermined position, thereby affecting the alignment and good connection with the second conductive connector 140, and reducing the yield. In the embodiment of the present invention, in order to overcome this problem, the front electrodes 120 are disposed on one side of the front surface of the photodetection chip 90 close to the second conductive connector 140 and the second conductive pad 60 and the opposite side thereof, so that two metal electrodes (front electrodes) on the surfaces of two photodetection chips in one package unit can be mounted close to the second conductive connector 140 and the second conductive pad 60 "head to head" without rotating any photodetection chip during mounting, that is, since each chip is designed with two electrodes, half of the devices do not need to be rotated 180 ° during mounting, thereby reducing mounting errors caused by rotation, greatly reducing process complexity, and increasing yield.

In order to isolate the second conductive connecting body 140 from the sidewall of the photodetecting chip 90 and the second conductive connecting body 140 from the inactive region of the front portion of the photodetecting chip 90, the embodiment of the present invention forms an insulating structure as the package insulator 130 at least between the second conductive connecting body 140 and the sidewall of the photodetecting chip 90 and between the second conductive connecting body 140 and the inactive region of the front portion of the photodetecting chip 90. In an example of the present invention, at least the chip sidewalls of both sides of the photodetecting chip provided with the front electrode 120 and the chip front portion non-active region are covered by the package insulator 130. In addition, a partial region of the front surface of the insulating ink 50 may also be covered by the encapsulation insulator 130 to isolate the second conductive connector 140 from the rear electrode of the chip.

The protection layer 150 is used to coat on the photodetection chip 90 for protection, or the protection layer 150 is coated on the surface of the package substrate including the package substrate, the chip, the package insulator and the second conductive connector for protecting the package substrate. As an example, the protection layer 150 may be a transparent insulating silicone sealant protection layer, but the invention is not limited thereto, and may be other materials suitable for protection.

In some embodiments of the present invention, the first conductive connector 110 may use conductive silver paste or silver paste with low resistivity, low thickness, high thermal conductivity, high adhesion and low temperature curing for connecting the chip back electrode and the first conductive pad and fixing the chip. The second conductive connector 140 may be formed by a dot coating or screen printing technique of a conductive silver paste assisted by uv curing and heating, and since the conductive silver paste or silver paste has good fluidity, it may completely cover the front electrode and the second conductive pad of the chip, and has a low resistivity after low temperature curing. In the embodiment of the invention, the conductive silver paste or silver paste made of spherical silver particles is adopted instead of the conductive silver paste or silver paste made of flaky silver particles, so that the packaging yield is increased.

The chip active region 170 of the photo detection chip 90 is shown in fig. 4. In the conventional packaging method, if the package substrate 10 is divided into two connected portions (two package regions) corresponding to the two photodetection chips 90 to be packaged, the two photodetection chips 90 are respectively attached to the center positions of the two package regions, in this case, if the conductive silver paste is used as the conductive connectors (such as the conductive connectors 110 and 140), although the electrode connection can be made flexible, since the inactive area (dead area) of the packaged photoelectric devices needs to be reduced as much as possible, the conductive silver paste is designed to be thin, which is very easy to cause open circuit in the subsequent dicing process, resulting in low yield and difficult to improve. In the embodiment of the present invention, compared to the existing packaging method, the photodetection chip 90 is mounted at a position deviated from the center of the two parts, and more specifically, the photodetection chip 90 is deviated to the side without the second conductive connection body 140, so as to increase the thickness of the conductive silver paste used as the second conductive connection body, to avoid the probability of causing open circuit in the subsequent dicing process as much as possible, and further increase the yield of the product.

In the package structure shown in fig. 1, a plurality of photodetection chips are packaged to form a photodetection chip array, and the package structure uses two devices as a cycle, that is, as a unit of the array, in practical applications, the packaged chips can be cut along the position of the cutting position of the designed cutting street 160, and only a part of the second conductive connecting body is left as a conductive medium after cutting, so as to obtain a plurality of independent photodetection chip package structures, as shown in fig. 10.

The packaging method of the photodetection chip package structure as above is described below. As shown in fig. 3, the method includes the following steps.

Step S110, a first package substrate forming step.

In this step, the photo-detection chip 90 is employed with front electrodes disposed on both opposite sides of the front surface. The photodetection chip 90 is attached to the package substrate 10 prepared in advance to form a first package base, so that the back surface of the photodetection chip is attached to the front surface of the package substrate.

In this step, when mounting the photodetection chip 90, since the front electrodes are disposed on both sides of the photodetection chip 90, it is not necessary to rotate half of the photodetection chips by 180 °, thereby reducing the mounting error caused by the rotation. Meanwhile, the two chips to be attached to the same package substrate are as close to the edge of the package substrate as possible, and a gap as large as possible is reserved between the two chips, so that a thicker conductive silver adhesive used as a second conductive connector is formed in the subsequent packaging process, that is, compared with the prior art, the photoelectric detection chip 90 is moved outwards from the center, so that the yield of packaged products is increased, and the invalid area caused by packaging can be further reduced.

In the embodiment of the present invention, before the first package substrate forming step S110 is performed, the wafer is first diced to obtain individual photodetection chips, and the photodetection chips to be packaged and the package substrate are cleaned after dicing. The cleaning step comprises the steps of boiling ethanol to remove organic matters or grease, then washing with deionized water, drying with dry nitrogen after the washing is finished, baking for a certain time to clean the organic matters or grease, and drying. After the cleaning is completed, the first package substrate forming step S110 may be performed.

In the existing process, three sides of the photoelectric detection chip obtained by cutting without the conductive silver paste are usually left with non-active regions with the width of 100 μm, and in the embodiment of the invention, smaller non-active regions can be left, for example, non-active regions with the width of 50 μm are left, so that narrow-side packaging is realized. This is because the position is biased toward the edge without the conductive silver paste at the time of mounting, and a low dicing speed and a thicker blade are used, which can reduce an ineffective area due to packaging.

In an embodiment of the present invention, the package substrate may be prepared in advance using a printed circuit board process or a through silicon via process, and has first and second back electrodes, first and second conductive pads, and first and second conductive via structures as shown in fig. 2A and 2B. In addition, the top of the second conductive via may be covered with an insulating medium (e.g., insulating ink) 50, which isolates the second conductive via 70 from the backside electrode 100 of the photo-detection chip and isolates the first conductive pad from the second conductive pad. The insulating medium 50 may be a photo-imageable solder resist ink or other insulating medium that is preferably insulating. The design of coating the insulating medium in the embodiment of the invention can reduce the adverse effect of the line width process on the packaging substrate. The second conductive via is insulated from the chip back electrode, otherwise short-circuiting is caused, and the coating of the insulating medium is smaller than the manufacturing of a small through hole and a wiring packaging dead zone. In the prior art, the size of the second conductive via is usually designed to be 400 μm by 500 μm, and in the embodiment of the present invention, the size of the second conductive via may be 470 μm by 600 μm, the width of the via is increased by 70 μm, the length is increased by 100 μm, which is equivalent to the thickness of the side conductive silver paste of a single device after dicing is increased by 35 μm, and the length is increased by 100 μm, so as to greatly increase the yield and reliability, and also further reduce the invalid dimension introduced by the package according to the requirement.

In the first package base forming step S110, a proper amount of first conductive connectors 110 may be formed on the surface of the first conductive pads 20 on the front surface of the package substrate 10. The first conductive connecting body 110 may use conductive silver paste or silver paste with low resistivity, low thickness, high thermal conductivity, high adhesion and low temperature curing for connecting the chip back electrode and the first conductive pad and fixing the chip. In some embodiments, the first conductive connector 110 is fabricated by a general method of dispensing a proper amount of conductive silver paste or by a standard chip silver paste mounting process, and further, the chip back electrode is mounted on the first conductive pad 20 of the package substrate downward. Preferably, the first conductive connector 110 is in an amount to cover the first conductive pad 20 as much as possible without overflowing from the side to contact the sidewall. The chip 90 is mounted and the electrical connection of the chip back electrode 100 to the first conductive pad 20 is completed, forming a first package base. Fig. 4 and 5 are top and cross-sectional views of a first package substrate in an embodiment of the invention. Fig. 4 shows the chip active region 170, and compared with the existing packaging method, the patch is no longer in the center position, but is biased to the side without the conductive silver paste in the future, so that the thickness of the conductive silver paste serving as the second conductive connector formed in the subsequent step can be increased, the open circuit caused when the packaged product is cut is reduced, and the product yield is increased.

As described above, the invention prevents the photoelectric detection chip from being rotated during mounting, greatly reduces errors and improves the product yield. However, in order to further improve the positioning accuracy during the die attaching, in the embodiment of the present invention, a die attaching alignment mark may be formed on a package substrate (e.g., a PCB substrate) before the die attaching for alignment during the die attaching.

The patch alignment mark can be formed simultaneously with the bonding pad and the wiring when the PCB substrate is manufactured. The chip mounting on the PCB substrate needs an alignment mark which can be automatically identified by a chip mounter, and the conventional method is to finish the chip mounting together with the mounting or circuit pattern on the PCB substrate. The thinnest thickness of the copper foil of the PCB substrate is generally 17.5um, and the precision loss of the single side of the corroded strip width is larger than 26um (lateral corrosion of 1.5 times of the thickness), so that the alignment mark pattern is seriously deformed. Such a loss of accuracy of the alignment mark is not a problem in the case of a package having a low requirement for the placement accuracy, but in the case of the placement having a high requirement for the alignment accuracy, the yield is low if the placement accuracy error is controlled to be within 7 μm, for example. Therefore, in the embodiment of the invention, after the mounting or circuit pattern manufacturing is completed on the PCB substrate, the alignment mark is specially manufactured on the PCB substrate by adopting the thin metal layer evaporation and combining the photoetching corrosion method, if the thickness of the metal layer is 0.1-1 micron, the precision loss of the single side of the pattern after corrosion is only 0.15-1.5 micron, and the requirement of the narrow-edge packaging for the high-precision patch with the alignment precision of 5-7 microns can be met.

Step S120, a second package substrate forming step.

After the first package substrate is formed, the second package substrate forming step S120 may be continuously performed. In this step S120, a patterned package insulator 130 is formed on the first package substrate by using a photolithography technique, and a second package substrate including the first package substrate and the package insulator 130 is obtained, such that the package insulator 130 partially covers the non-active region of the front surface of the photodetection chip and completely covers the sidewalls.

In one embodiment of the present invention, the package insulator is a photoresist, preferably a SU-8 epoxy type near ultraviolet curing negative photoresist. In the case that the patterned insulating structure in the second package is a SU-8 cured photoresist, the first package substrate needs to be entirely cleaned and dried before step S120 is performed to ensure the cleanliness requirement of the SU-8 photoresist on the substrate, and then step S120 is performed.

The step S120 may further include the steps of:

(1) And spin-coating a photoresist, such as SU-8 epoxy type ultraviolet curing negative photoresist (SU-8 photoresist for short), on the first packaging substrate.

(2) After the photoresist coating is finished, the photoresist is subjected to soft baking (prebaking).

More specifically, the coated photoresist is soft-baked at two-stage temperature design (firstly, baking at 65 ℃ for 30min, and then baking at 95 ℃ for 30 min), so that the first layer of photoresist is initially cured, and the adhesion of the photoresist in the later step is ensured.

(3) And spin-coating SU-8 photoresist again, namely performing secondary coating of the photoresist.

(4) After the second coating, the photoresist was subjected to a sufficient soft bake (secondary prebake).

More specifically, the coated photoresist was soft baked at a two-stage temperature design (65 ℃ C. For 5min, then 95 ℃ C. For 30 min). In the embodiment of the invention, the advantages of adopting twice spin coating and twice prebaking are as follows: the existing scheme needs to select a photoresist with higher viscosity (such as SU-8 2100 photoresist with the viscosity reaching 45000 cSt) to coat the corners as much as possible, and the process has contingency, poor filling effect repeatability and easy bubble occurrence; according to the invention, by adopting a secondary photoresist throwing scheme, photoresist with smaller viscosity (such as 340-4500cSt photoresist, for example SU-8 3010 type photoresist with viscosity of 400 cSt) can be selected, so that the surface photoresist can be ensured to be thinner, the subsequent use of conductive silver paste for electrical connection is facilitated, meanwhile, the side wall can be completely coated, the process repeatability is good, and the yield of finished products can be greatly improved.

(5) And carrying out ultraviolet exposure and postbaking on the packaging substrate.

More specifically, a reticle (mask) is designed in advance according to the position and width of a packaging insulator required by a design structure, and exposure operation is controlled by using the mask, so that only part of SU-8 photoresist undergoes a photochemical reaction; then, baking is carried out after exposure at two temperatures (65 ℃ for 5min, and then 95 ℃ for 10 min), and crosslinking of the photosensitive SU-8 photoresist is promoted. After post-baking, the device is further placed on a hot plate to be cooled from 95 ℃ to room temperature, and in doing so, the side wall retraction (microstructure damage) caused by quenching can be prevented, so that the product yield is increased.

(6) And developing and hardening the packaging matrix.

To obtain a higher aspect ratio package insulator structure, the package substrate may be first ultrasonically developed in a developer for 10 minutes to ensure that most of the negative photoresist in the unexposed areas is removed (if it is a positive photoresist, the exposed areas are dissolved), and then further ultrasonically developed in a fresh developer for 30 minutes to ensure that the photoresist in the pattern details is sufficiently removed.

Washing in isopropanol for 10 seconds after the development, finally washing in deionized water for 20 seconds to wash away the developing solution and photoresist dissolved in the developing solution, preliminarily forming a second packaging matrix after the completion, and then hardening the formed second packaging matrix by heating at 150 ℃ for 3 hours, so that the second packaging matrix has more sufficient cross-linking reaction and better mechanical stress. The developing time and the cleaning time are only examples and can be flexibly adjusted, and the invention is not limited thereto.

The SU-8 photoresist can be used for manufacturing a step structure with a very high aspect ratio, the formed packaging insulator structure can complete better insulation protection on the side face of a chip, and the SU-8 photoresist has excellent chemical stability (corrosion resistance) and thermal stability after being completely cured.

Fig. 6 and 7 are a top view and a cross-sectional view, respectively, of a front side of a second package substrate in an embodiment. As shown in fig. 6 and 7, the SU-8 epoxy type package insulator structure after the photolithography can well cover part or all of the non-active region of the edge of the side surface and the upper surface of the photodetection chip, and in addition, the package insulator structure is completely attached to the package substrate, leaving only one window on the second conductive pad.

The invention adopts photoresist as surface protective material. The existing process adopts photoresist with higher viscosity, so that great risk exists to cause uneven filling and corner exposure, the repeatability of the process cannot be ensured, the process cannot be applied to mass production, the requirement on the size of a device is strict, and the universality is not good. In the embodiment of the invention, the photoresist with lower viscosity, such as SU-8 3010 type photoresist with viscosity of 400cSt, is adopted, so that the corner gaps are fully filled, the height of the surface insulator can be reduced, the connection difficulty of the second conductive connector in the subsequent steps is reduced, the number of circuit breaking devices can be greatly reduced, and the yield is increased.

Step S130, a third package base forming step.

After the second package substrate is generated, a third package substrate forming step S130 may be performed. In this step S130, a second conductive connector 140 is formed on the second package base along at least a portion of the surface of the package insulator to connect the front electrode 120 of the photodetection chip and the second conductive pad 60, resulting in a third package base comprising the second package base and the second conductive connector 140.

More specifically, in step S130, a second conductive connector may be formed by dispensing (dispensing conductive paste), screen printing conductive paste, or the like, so as to link and cure the front electrode of the photodetecting chip and the second conductive pad on the front surface of the package substrate, so that the second conductive connector completely fills the window on the second conductive pad.

As an example of the present invention, the second conductive connector may be formed by using a dot coating or screen printing technique of a conductive silver paste assisted by uv curing and heating, which may completely cover the front electrode of the chip and the second conductive pad due to its better fluidity and has a lower resistivity after being cured at a low temperature.

In the embodiment of the invention, the height of the second conductive connector can be slightly higher than that of the packaging insulator, the structure is complete, and the second conductive connector completely covers the second conductive bonding pad and the front electrode of the chip.

After the second conductive connectors 140 are formed, a third package substrate including a second package substrate and second conductive connectors is formed. Fig. 8 and 9 are a plan view and a sectional view, respectively, of the front surface of a third package base in an embodiment. As shown in fig. 8 and 9, the second conductive connector 140 may have a height slightly higher than the window on the second conductive pad, and the second conductive connector is connected to the front electrode of the photo-detecting chip across the sidewall of the insulator, but is completely isolated from the side and back electrodes of the photo-detecting chip.

Step S140, a package unit forming step.

After the third package base is generated, the package unit forming step S140 may be performed. In step S140, a thin organic silicon potting adhesive protection layer 150 is coated on the surface of the third packaging substrate, so as to obtain a packaging unit of the photodetecting chip. The thickness of the organic silicon pouring sealant protective layer is slightly higher than that of the second conductive connector, and the organic silicon pouring sealant protective layer can be cured at 100 ℃ for 1 hour and 150 ℃ for 4 hours. The protective layer forming process in the prior art uses epoxy resin, the formed surface has the thickness of 80-100 mu m, and the protective layer is too thin, so that the reliability of the protective layer in severe environment is greatly reduced. Compared with the existing packaging method, the invention changes the protective material into the organic silicon pouring sealant, thickens the protective layer by about 200 microns, namely the thickness of the protective layer is 200-400 microns, greatly improves the protection of the protective layer on the surface, and has better performance in an aging test.

After the organic silicon pouring sealant protective layer is cured, the packaged chip array is scribed along the designed scribing position (such as scribing position 160), so as to form an independent packaging structure (packaging unit) corresponding to each photoelectric detection chip. More specifically, the chip may be scribed along the second conductive connecting body at a position close to the front electrode of the chip, and a certain second conductive connecting body is left as an electrical connection structure of the final second conductive pad and the front electrode of the chip, thereby forming an independent packaging unit as shown in fig. 10. In accordance with this step, in step S130, the width of the second conductive connector may be formed to be slightly wider than the cutting width, and the width of the cutting blade may be increased according to the actual cutting accuracy and the allowable tolerance. After cutting, the individual package units are thoroughly cleaned, including cleaning the surface silicone potting adhesive layer with a soft brush. After cleaning, the product can be dried by dry nitrogen and baked for a certain time to clean and dry.

In the embodiment of the invention, the array packaged chip is cut to form a plurality of independent photoelectric detection chip packaging units, wherein the maximum packaging dead zone edge width of each independent packaging unit can be determined by the width of the insulator and the width of the residual second conductive connecting bodies after cutting.

Experimental research shows that compared with the packaging method and the packaging structure provided by the chinese patent application cn202110065307.X, the chip packaging method and the packaging structure provided by the present application greatly improve the reliability and yield of products, the yield can be increased from 20% to the maximum after cutting 93.37%, and the size after packaging can be further reduced, the improved process steps can be applied to the packaging of devices of more types and sizes, and the compatibility of the process is greatly increased.

As can be seen from the above, the chip packaging method and the chip packaging structure of the present invention are improved in the following respects, compared with the prior art: (1) The layout of the device is changed, and the photoelectric detection chip is changed into a structure with electrode connection points on both sides, so that the chip is not required to rotate during chip mounting, the chip mounting error caused by rotation is reduced, the complexity is reduced, and the yield is increased; and the photoelectric detector is moved outwards from the center of the corresponding area of the packaging substrate so as to increase the packaging yield and further reduce the invalid area brought by packaging. (2) The photoresist with lower viscosity than that of the prior art is adopted, so that the corner gaps are fully filled, the height of the surface insulator is reduced, the connection difficulty of the second conductive connector is reduced, the number of circuit breaking devices is greatly reduced, and the yield is increased. (3) When the packaging insulator is formed, twice whirl coating is adopted, and abnormal electrical characteristics caused by non-uniform coating of the insulating medium are reduced. (4) The conductive silver paste or silver paste made of the spherical silver particles is adopted instead of the flaky particles, so that the packaging yield is increased. (5) The silicon resin pouring sealant commonly used by the LED is selected as the protective layer, the thickness of the protective layer is increased, the conductive connector is protected, and the reliability of the packaged device is greatly improved. The invention overcomes the defects of low yield, low reliability and the like in the prior art and can be used for mass production.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments in the present invention.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A package structure of a photodetection chip, the package structure comprising: the photoelectric detection device comprises a packaging substrate, a photoelectric detection chip attached to the packaging substrate, a packaging insulator, a protective layer coated on the photoelectric detection chip and a conductive connecting body for electrically connecting the photoelectric detection chip and the packaging substrate; the back surface of the packaging substrate is provided with a first electrode and a second electrode, the front surface of the packaging substrate is provided with a first conductive bonding pad and a second conductive bonding pad, the first conductive bonding pad is connected with the first electrode through a first conductive through hole, and the second conductive bonding pad is connected with the second electrode through a second conductive through hole; the method is characterized in that:

the photoelectric detection chip comprises a first photoelectric detection chip and a second photoelectric detection chip, wherein front electrodes are arranged on one sides of the front surfaces of the first photoelectric detection chip and the second photoelectric detection chip, which are close to the second conductive bonding pad, and the opposite sides of the front surfaces of the first photoelectric detection chip and the second photoelectric detection chip are respectively provided with a front electrode, the back electrodes are arranged on the back surfaces of the first photoelectric detection chip and the second photoelectric detection chip, the back electrodes are electrically connected with the first conductive bonding pad through a first conductive connector, and the front electrodes on one sides of the photoelectric detection chip, which are close to the second conductive bonding pad, are electrically connected with the second conductive bonding pad through a second conductive connector;

2. The package structure of claim 1, wherein the second conductive connector crosses over a sidewall of the package insulator to connect with the front electrode of the photodetecting chip and the second conductive pad, the second conductive connector being further electrically isolated from the back electrode of the photodetecting chip;

the second conductive connector is conductive silver glue or conductive silver paste made of spherical silver particles.

3. The package structure of claim 2,

the packaging insulator is attached to the packaging substrate, and a window is reserved on the second conductive pad;

the second conductive connector fills a window on the second conductive pad.

4. The package structure according to claim 1, wherein an insulating medium covers the top of the second conductive via, and the insulating medium isolates the first conductive pad from the second conductive pad;

the insulating medium is light imaging solder resist ink;

the encapsulation insulator also covers a partial area of the front side of the photo-imageable solder resist ink so that the second conductive connector is isolated from the back electrode of the photodetecting chip.

5. The package structure of claim 1,

the first conductive connector is conductive silver glue or silver paste made of spherical silver particles;

the packaging insulator is an epoxy insulator structure formed on the packaging substrate after the photoresist is processed by utilizing a photoetching technology;

the epoxy type insulating structure covers the side surface and part or all of the non-active area of the edge of the upper surface of the photoelectric detection chip;

the protective layer is an insulating organic silicon pouring sealant protective layer, and the thickness of the protective layer is 200-400 mu m.

6. A packaging method of a photoelectric detection chip is characterized by comprising the following steps:

7. The packaging method of claim 6,

the first conductive connector and the second conductive connector are conductive silver paste or silver paste made of spherical silver particles;

the packaging insulator is an epoxy insulator structure formed on the packaging substrate after the photoresist is processed by utilizing a photoetching technology; the epoxy type insulating structure covers the side surface and part or all of the non-active area of the edge of the upper surface of the photoelectric detection chip;

In the third packaging substrate forming step, forming the second conductive connecting body in a dispensing or screen printing mode; the second conductive connector crosses over the side wall of the packaging insulator to be connected with the front electrode of the photoelectric detection chip and the second conductive bonding pad, and is isolated from the side surface of the photoelectric detection chip by the packaging insulator; the second conductive connector is also isolated from a back electrode of the photoelectric detection chip;

the second conductive connector fills a window on the second conductive pad.

8. The method of packaging of claim 6, wherein prior to the first package base forming step, the method further comprises:

an insulating medium covers the top of the second conductive through hole, and the insulating medium isolates the second conductive through hole from a back electrode of the photoelectric detection chip and isolates the first conductive pad from the second conductive pad;

the insulating medium is light imaging solder resist ink;

the packaging insulator also covers partial area of the front side of the photo-imaging solder resist ink so that the second conductive connector is isolated from the back electrode of the photoelectric detection chip.

9. The method of claim 6, wherein the second package base forming step comprises:

coating photoresist on the first packaging substrate;

soft baking the coated photoresist;

coating photoresist again;

soft baking the recoated photoresist;

exposing and post-baking the packaging substrate by using a mask; and

and developing and hardening the packaging substrate to obtain the packaging insulator.

10. The packaging method according to claim 6,

the packaging insulator is an epoxy insulator structure formed on the packaging substrate after the photoresist is processed by utilizing a photoetching technology; the photoresist is SU-8 epoxy negative photoresist, and the viscosity of the photoresist is 340-4500cSt; the epoxy type insulating structure covers the side surface and part or all of the non-active area of the edge of the upper surface of the photoelectric detection chip;

11. The packaging method according to claim 6,

the first package base formed in the first package base forming step includes a photodetection chip array formed by a plurality of photodetection chips attached to the package substrate;

in the step of forming the second packaging substrate, when the first packaging substrate is coated with the photoresist, the photoresist is coated twice to uniformly cover the photoelectric detection surface of the chip and the interval between adjacent chips;

the packaging structure of the photoelectric detection chip formed in the packaging unit forming step is a packaging structure of a photoelectric detection chip array;

the method further comprises the following steps: and cutting the packaging structure of the photoelectric detection chip array to form a plurality of independent photoelectric detection chip packaging units.

12. The method of packaging of claim 6, wherein prior to the first package base forming step, the method further comprises:

and (3) adopting a thin metal layer for evaporation and photoetching corrosion to manufacture an alignment mark on the packaging substrate for mounting the photoelectric detection chip.