CN115718544A

CN115718544A - Electronic device

Info

Publication number: CN115718544A
Application number: CN202210608664.0A
Authority: CN
Inventors: 翁赞博
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2021-08-25
Filing date: 2022-05-31
Publication date: 2023-02-28
Also published as: TW202309622A; TWI824542B

Abstract

The invention provides an electronic device, which comprises a substrate, a first electrode, a second electrode, a first signal line, a second signal line, a sensing electrode and a sensing signal line. The first electrode is disposed on the substrate. The second electrode is disposed on the substrate and adjacent to the first electrode in a first direction. The first signal line is electrically connected to the first electrode. The second signal line is electrically connected with the second electrode. The sensing signal line is electrically connected with the sensing electrode. In a top view, the sensing signal line is disposed between the first signal line and the second signal line in the first direction.

Description

Electronic device

Technical Field

The present disclosure relates to an electronic device, and more particularly, to an electronic device having a sensing electrode.

Background

In recent years, touch display devices have been widely used in various electronic products, such as mobile phones, personal Digital Assistants (PDAs), or palm-type personal computers. A touch display device generally includes a touch panel and a display panel. The user can touch the image displayed on the touch display device to input information or control the electronic product. The performance of the touch display device still needs to be improved.

Disclosure of Invention

An embodiment of the present disclosure provides an electronic device, including a substrate, a first electrode, a second electrode, a first signal line, a second signal line, a sensing electrode, and a sensing signal line. The first electrode is disposed on the substrate. The second electrode is disposed on the substrate and adjacent to the first electrode in a first direction. The first signal line is electrically connected to the first electrode. The second signal line is electrically connected with the second electrode. The sensing signal line is electrically connected with the sensing electrode. In a top view, the sensing signal line is disposed between the first signal line and the second signal line in the first direction.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a schematic view of an electronic device of the present disclosure;

FIG. 2 is another schematic view of an electronic device of the present disclosure;

FIG. 3 is another schematic view of an electronic device of the present disclosure;

FIG. 4 is another schematic view of an electronic device of the present disclosure;

FIG. 5 is another schematic view of an electronic device of the present disclosure;

FIG. 6 is another schematic view of an electronic device of the present disclosure;

FIG. 7 is a schematic diagram illustrating a relationship between gate lines, signal lines, sensing electrodes, and sensing signal lines according to the disclosure;

FIG. 8 is another schematic view of an electronic device of the present disclosure;

fig. 9 is a schematic diagram of a processing unit of the present disclosure.

Reference numerals

100. 500, 600, 800: electronic device

110. 712: substrate

110S, 510, 610, 710S, 810: array substrate

520. 620 _1to 620_P, 630, 820 _1to 820_P: circuit board

SE1, SE2: sensing electrode

RP1, RP2: pixel column

PIX ₁₁ ～PIX _1N 、PIX _M1 ～PIX _MN : pixel

D1 to D3: direction of rotation

E _{11_1} ～E _{11_3} 、E _{1N_1} ～E _{1N_3} 、E _{M1_1} ～E _{M1_3} 、E _{MN_1} ～E _{MN_3} : electrode for electrochemical cell

LN ₁ ～LN _K : signal line

LS1, LS2: sensing signal line

PD ₁ ～PD _K 、PA ₁ ～PA _K PB, 980: connecting pad

S1, S2, SA1: sensing connecting pad

PC1, PC2: dummy pad

511. 611, 612: gate driver

GL ₁ ～GL _M : gate line

111 to 113: sub-pixel

521. 621_1 to 621_P, 821 _u1 to 821_P: processing unit

631: power supply circuit

632: time sequence controller

633: voltage converter

711. 724: polaroid

713. 715, 717, 719, 721: insulating layer

714: first conductive layer

716: second conductive layer

718: common electrode

720: third conductive layer

722: liquid crystal layer

723: color filter substrate

725: cover plate layer

910: analog circuit

920: micro control circuit

930: touch sensing circuit

940: display driving circuit

950: high impedance circuit

960: buffer setting circuit

971 to 973: switch with a switch body

DS1 to DS4: a distance;

w21 to W28, W41 to W48: width of

A ₁ ～A _K And AS1: conductive adhesive

AA: active region

NA: peripheral region

100: electronic device with a detachable cover

110: substrate

110S: array substrate

SE1, SE2: sensing electrode

RP1, RP2: pixel column

PIX ₁₁ ～PIX _1N 、PIX _M1 ～PIX _MN : pixel

D1 to D3: direction of rotation

LN ₁ ～LN _K : signal line

LS1, LS2: sensing signal line

PD ₁ ～PD _K : connecting pad

S1, S2: sensing connecting pad

111 to 113: sub-pixel

DS1 to DS4: distance between two adjacent plates

AA: active region

NA: peripheral region

Detailed Description

In order to make the objects, features and advantages of the present disclosure comprehensible, embodiments accompanied with figures are described in detail below. The present disclosure provides different examples to illustrate technical features of different embodiments of the present disclosure. The configuration of the components in the embodiments is for illustration and is not intended to limit the disclosure. In addition, the reference numerals in the embodiments are partially repeated to simplify the description, and do not indicate the relationship between different embodiments.

In the various embodiments of the present disclosure described below, the orientations "up" and "down" are used to indicate relative positional relationships, and are not intended to limit the present disclosure. The term "a structure (or layer, element, substrate) on/above another structure (or layer, element, substrate) as used in this disclosure may mean that two structures are adjacent and directly connected, or may mean that two structures are adjacent and not directly connected, and the indirect connection means that at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate space) is provided between the two structures, the lower surface of one structure is adjacent or directly connected to the upper surface of the intermediate structure, the upper surface of the other structure is adjacent or directly connected to the lower surface of the intermediate structure, and the intermediate structure may be a single-layer or multi-layer solid structure or a non-solid structure, without limitation. In the present disclosure, when a structure is "on" another structure, it may mean that the structure is "directly" on the other structure or "indirectly" on the other structure, that is, at least one structure is further interposed between the structure and the other structure.

The electrical connection or coupling described in the present disclosure may refer to a direct connection or an indirect connection, in which case, the terminals of the two circuit components are directly connected or connected with each other by a conductor segment, and in which case, the terminals of the two circuit components have a switch, a diode, a capacitor, an inductor, a resistor, other suitable components, or a combination of the above components, but is not limited thereto.

In the present disclosure, the thickness, length and width may be measured by an optical microscope, and the thickness may be measured by a cross-sectional image in an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison. If the first value is equal to the second value, it implies that there may be an error between the first value and the second value within about 10%, more preferably within 5%, or within 2%, or within 1%, or within 0.5%.

The use of ordinal numbers such as "first," "second," etc., in the specification and claims to modify a component is not by itself intended to imply any previous order to the component(s), nor the order in which a component may be sequenced or order in a method of manufacture, but are used to imply that the component having a certain name is explicitly identified as such. The claims may not use the same words in the specification, and accordingly, a first element in a specification may be a second element in a claim.

It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure. Features of the various embodiments may be combined and matched as desired, without departing from the spirit or ambit of the invention.

In addition, in the drawings or the description, the same reference numerals are used for similar or identical parts. In the drawings, the shape or thickness of the embodiments may be exaggerated for simplicity or convenience of illustration. Components not shown or described in the drawings are in a form known to those skilled in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Fig. 1 is a schematic view of an electronic device of the present disclosure. As shown, the electronic device 100 includes an array substrate 110S. The array substrate 110S may include a substrate 110, sensing electrodes SE1 and SE2, pixel rows RP1 and RP2, and signal lines LN ₂ 、LN ₃ And a sensing signal line LS1. Sensing electrodes SE1 and SE2, pixel columns RP1 and RP2, and signal line LN ₂ (or called first signal line), signal line LN ₃ Or the second signal line, and the sensing signal line LS1 may be disposed on the substrate 110. The pixel column RP1 can include an electrode E _{11_2} And E _{11_3} . Electrode E _{11_2} And E _{11_3} Adjacent to each other in a direction D1 (or first direction). Signal line LN ₂ (first signal line) electrically connected to the electrode E _{11_2} (or first electrode). Signal line LN ₃ (second signal line) electrically connected to the electrode E _{11_3} (or second electrode). The sensing signal line LS1 is electrically connected to the sensing electrode SE1. As shown in fig. 1, in a top viewA sensing signal line LS1 is disposed on the signal line LN in the direction D1 ₂ And LN ₃ In the meantime. According to some embodiments, the direction D1 may be an extending direction of a gate line (as shown in fig. 5) on the substrate 110.

According to some embodiments, the array substrate 110S may include a plurality of driving elements (not shown) arranged in an array, such as a plurality of Thin Film Transistors (TFTs). The present disclosure does not limit the kind of the electronic device 100. In one possible embodiment, the electronic device 100 may include a display apparatus, an antenna device, a sensing device, or a splicing device, but not limited thereto. In addition, the electronic device 100 may be a bendable or flexible electronic device. In some embodiments, the electronic device 100 may include, for example, a liquid crystal (liquid crystal), or a light emitting diode. The light emitting diode may include, for example, an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (QD, which may be, for example, a QLED or a QDLED), a fluorescent light (fluorescent), a phosphorescent light (phosphor), or other suitable materials, and the materials may be arranged and combined arbitrarily, but not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device 100 can be any permutation and combination of the foregoing, but not limited thereto.

As shown in fig. 1, the substrate 110 may be divided into an active area AA and a peripheral area NA. The peripheral region NA is adjacent to the active region AA. According to some embodiments, the active area AA is located at a middle position of the substrate 110, the peripheral area NA is located near an edge of the substrate, and one side of the peripheral area NA may be an edge of the substrate 110. The pixel rows RP1 and RP2 are disposed on the substrate 110, and may be disposed in the active area AA of the substrate 110 and arranged along a direction D2 (or a second direction). The pixel column RP1 has pixels PIX ₁₁ ～PIX _1N . Pixel PIX ₁₁ ～PIX _1N Are arranged in sequence in the direction D1. The directions D1 and D2 may be different, for example, perpendicular to each other, but not limited thereto. In the present embodiment, the pixel PIX ₁₁ ～PIX _1N May have a plurality of electrodes, e.g.,has three electrodes. For example, pixel PIX ₁₁ Having an electrode E _{11_1} ～E _{11_3} Pixel PIX _1N Having an electrode E _{1N_1} ～E _{1N_3} . When the electronic device 100 has a display function, the active area AA may be a display area.

In some embodiments, the pixel PIX ₁₁ ～PIX _1N Has a plurality of sub-pixels, e.g., has three sub-pixels. Each sub-pixel presents a corresponding color. By pixel PIX ₁₁ As an example, the pixel PIX ₁₁ Including sub-pixels 111-113. The present disclosure does not limit the colors that the pixels 111-113 exhibit. In one possible embodiment, the sub-pixel 111 represents one of red, green and blue, the sub-pixel 112 represents another of red, green and blue, and the sub-pixel 113 represents the last of red, green and blue. In this example, electrode E _{11_1} Refers to the pixel electrode, electrode E, included in the sub-pixel 111 _{11_2} Refers to the pixel electrode, electrode E, included in the sub-pixel 112 _{11_3} Refers to the pixel electrode included in the sub-pixel 113. According to some embodiments, one sub-pixel may include a pixel electrode and a driving component (e.g., a TFT, not shown). The driving components may include a semiconductor, a gate, a source, and a drain. The source electrode can be electrically connected with the corresponding data line, and the grid electrode can be electrically connected with the corresponding grid line. The pixel electrode may be an electrode electrically connected to a driving element (e.g., a TFT, not shown) on the substrate 110, for example, an electrode electrically connected to a drain electrode in the TFT.

Pixel PIX _M1 ～PIX _MN Are arranged in sequence in the direction D1. Due to the pixel PIX _M1 ～PIX _MN Is similar to the pixel PIX ₁₁ ～PIX _1N The features of (1) are not described in detail. For convenience of illustration, fig. 1 only shows pixel columns RP1 and RP2, but is not intended to limit the disclosure. In other embodiments, the electronic device 100 has more pixel columns. In this example, the pixel rows are arranged in sequence along the direction D2. For convenience of illustration, fig. 1 only shows the sensing electrodes SE1, SE2, but not to limit the disclosure. The present disclosure does not limit the number of sensing electrodes. In other embodiments, an electronic device100 have more sensing electrodes. In other embodiments, a plurality of sensing electrodes may be disposed on the substrate 100, for example, the sensing electrodes may be arranged in the direction D1 and the direction D2 to form a matrix.

Electrode E _{11_1} ～E _{11_3} Are arranged in sequence in the direction D1. Electrode E _{11_2} In the direction D1 with the electrode E _{11_1} (or called third electrode) and electrode E _{11_3} Are adjacently arranged. Electrode E _{1N_1} ～E _{1N_3} Are arranged in sequence in the direction D1. Electrode E _{1N_2} Adjacent electrodes E in the direction D1 _{1N_1} And E _{1N_3} . Electrode E _{M1_1} ～E _{M1_3} Arranged in sequence in the direction D1. Electrode E _{M1_2} Adjacent electrodes E in the direction D1 _{M1_1} And E _{M1_3} . Electrode E _{MN_1} ～E _{MN_3} Are arranged in sequence in the direction D1. Electrode E _{MN_2} Adjacent electrodes E in the direction D1 _{MN_1} And E _{MN_3} . At electrode E _{11_2} And electrode E _{11_1} In the case of a pixel electrode, the electrode E _{11_2} In the direction D1 with the electrode E _{11_1} Arranged adjacently, in the direction D1, to the pixel electrode E _{11_2} And a pixel electrode E _{11_1} There are no other pixel electrodes in between.

As shown in fig. 1, in a top view, the sensing electrode SE1 may be disposed in the active area AA of the substrate 110, overlapping with the pixel column RP 1. In other embodiments, the sensing electrode SE1 may overlap with more pixel columns. In the present embodiment, sensing electrode SE1 and electrode E _{11_1} ～E _{1N_} At different layers. For example, sensing electrode SE1 and electrode E _{11_2} Located in different layers. For example, in the direction D3, the sensing electrode SE1 can be located at the electrode E _{11_1} ～E _{1N_3} And with electrode E _{11_1} ～E _{1N_3} And (4) overlapping. For example, in top view, sensing electrode SE1 and electrode E _{11_2} And E _{11_3} And (4) overlapping. According to the present disclosure, the sensing electrode may have a touch function, a fingerprint recognition function, or a combination thereof.

The sensing electrode SE2 overlaps the pixel column RP 2. In other embodiments, the sense electrode SE2 overlaps more pixel columns. In the present embodiment, electricity is sensedElectrode SE2 and electrode E _{M1_1} ～E _{MN_3} Located in different layers. For example, in a top view, the sensing electrode SE2 is located at the electrode E _{M1_1} ～E _{MN_3} And with electrode E _{M1_1} ～E _{MN_3} And (4) overlapping. In some embodiments, the electrode on which sense electrode SE2 overlaps (e.g., E) _{M1_1} ～E _{MN_3} ) Electrodes other than sense electrode SE1 overlapping (e.g. E) _{11_1} ～E _{1N_3} ). In other embodiments, sense electrode SE2 may overlap a different number of electrodes than sense electrode SE1.

In some embodiments, sense electrode SE1 acts as pixel PIX ₁₁ ～PIX _1N The sensing electrode SE2 is used as the pixel PIX _M1 ～PIX _MN The common electrode of (2). In this example, the sensing electrodes SE1 and SE2 receive a common voltage (Vcom) during a display period.

In some embodiments, the electronic device 100 further includes a signal line LN ₁ ～LN _K . Signal line LN ₁ ～LN _K May extend in direction D2. Signal line LN ₁ ～LN _K Each of which is electrically connected to the plurality of electrodes. For example, a signal line LN ₁ (or third signal line) electrically connected to the electrode E _{11_1} And E _{M1_1} . Signal line LN ₂ Electrically connecting electrode E _{11_2} And E _{M1_2} . Signal line LN ₃ Electrically connecting electrode E _{11_3} And E _{M1_3} . Signal line LN _K-2 Electrically connecting electrode E _{1N_1} And E _{MN_1} . Signal line LN _K-2 Electric connection electrode E _{1N_2} And E _{MN_2} . Signal line LN _K Electrically connecting electrode E _{1N_3} And E _{MN_3} . For the sake of illustration, FIG. 1 shows only the signal lines LN ₁ Electrically connecting electrode E _{11_1} And E _{M1_1} However, the present disclosure is not limited thereto. In some embodiments, a signal line LN ₁ In the direction D2, an electrode E can be connected _{11_1} And E _{M1_1} Other electrodes (not shown) than the above. Similarly, other signal lines may also be connected to other electrodes in the direction D2, and are not described herein again. Signal line LN ₁ ～LN _K Arranged in sequence in the direction D1 and extending in the direction D2. In some embodiments, a signal line LN ₁ ～LN _K The data line is used for transmitting data signals and can be used as a data line (data line).

In other embodiments, the electronic device 100 further includes sensing signal lines LS1 and LS2. The sensing signal line LS1 is electrically connected to the sensing electrode SE1. The present disclosure does not limit the position of the sensing signal line LS1. In the present embodiment, the sensing signal lines LS1 are located at the same pixel (e.g. PIX) ₁₁ ) Between the signal lines of adjacent sub-pixels. For example, in a top view, as shown in fig. 1, the sensing signal line LS1 may be disposed on the signal line LN in the direction D1 ₂ And LN ₃ But not to limit the disclosure. As shown in FIG. 1, according to some embodiments, a signal line LN ₂ And LN ₃ Electrodes E electrically connected respectively _{11_2} And an electrode E _{11_3} Can be in the same pixel PIX ₁₁ In (1). In another possible embodiment, the sensing signal line LS1 is disposed on the signal line LN in the direction D1 ₁ And LN ₂ In the meantime.

The sensing signal line LS2 is electrically connected to the sensing electrode SE2. In a top view, the sensing signal line LS2 is disposed on the signal line LN in the direction D1 _K-1 And LN _K But not to limit the disclosure. In another embodiment, the sensing signal line LS2 may be disposed on the signal line LN in the direction D1 _K-2 And LN _K-1 In between. In one possible embodiment, the number of sensing signal lines may be the same as the number of sensing electrodes.

In the present embodiment, the signal line LS1 and the signal line LN are sensed ₁ ～LN ₃ Located in different layers. For example, a signal line LN ₂ And the sensing signal line LS1 are located at different layers. For example, in a cross-sectional view, as shown in FIG. 7, the sensing signal line LS1 is located at the signal line LN ₁ ～LN ₃ Above (b). Similarly, a sense signal line LS2 and a signal line LN _K-2 ～LN _K Are different layers. For example, in a cross-sectional view, the sensing signal line LS2 is located at the signal line LN _K-2 ～LN _K Above (b). In this example, the sensing signal lines LS1 and LS2 are located at the same conductive positionLayer, signal line LN ₁ ～LN ₃ And LN _K-2 ～LN _K Is located on the other conductive layer. The sensing signal lines LS1 and LS2 and the signal line LN will be described later with reference to FIG. 7 ₁ ～LN ₃ And LN _K-2 ～LN _K In a stacked relationship therebetween.

In some embodiments, as shown in fig. 1, the electronic device 100 further includes a pad PD ₁ ～PD _K . Pad PD ₁ ～PD _K Disposed on the substrate 110, may be disposed in a peripheral area NA of the substrate 110. In this example, the pad PD ₁ ～PD _K Respectively electrically connected with signal lines LN ₁ ～LN _K . For example, the pad PD ₂ (or called first pad) electrically connected to the signal line LN ₂ (iii) pad PD ₃ (or called second pad) electrically connected to the signal line LN ₃ (iii) pad PD ₁ (or called third pad) electrically connected to the signal line LN ₁ Pad PD _K-2 Electrically connected signal line LN _K-2 (iii) pad PD _K-1 Electrically connected signal line LN _K-1 (iii) pad PD _K Electrically connected signal line LN _K . In some embodiments, the pad PD ₁ ～PD _K For receiving a voltage level provided by a control circuit (not shown) external to the substrate 110. In this case, the control circuit passes through the pad PD ₁ ～PD _K Control electrode E _{11_1} ～E _{1N_3} And E _{M1_1} ～E _{MN_3} The voltage level of (d).

The electronic device 100 further includes sensing pads S1 and S2. The sensing pads S1 and S2 are disposed on the substrate 110 and may be disposed in a peripheral area NA of the substrate 110. The sensing pad S1 is electrically connected to the sensing signal line LS1. The sensing pad S2 is electrically connected to the sensing signal line LS2. In the direction D1, the sensing pad S1 is disposed on the pad PD ₂ And PD ₃ In the meantime. In one possible embodiment, in a top view, as shown in fig. 1, the pad PD ₂ And PD ₃ The distance DS2 in the direction D1 is greater than the pad PD ₂ And PD ₁ Distance DS1 in direction D1. In other embodiments, the sensing pad S2 is disposed on the pad PD in the direction D1 _K-1 And PD _K In the meantime. In a top view, as shown in fig. 1, the pad PD _K-1 And PD _K The distance DS4 in the direction D1 is greater than the pad PD _K-1 And PD _K-2 Distance DS3 in direction D1. In some embodiments, in the top view, in the direction D1, the widths of the pads S1 and S2 and the pad PD are sensed ₁ ～PD _K May be equal in width. According to some embodiments, the width of the pad S1 and the pad PD are sensed in the direction D1 ₁ ～PD _K May be equal in width.

In another possible embodiment, the sensing signal line LS2 is located at the signal line LN _K-2 And LN _K-1 In between (not shown). In this example, the sensing pad S2 is disposed on the pad PD in the direction D1 _K-2 And PD _K-1 In between. Therefore, in a top view (not shown), the pad PD _K-1 And PD _K-2 The distance in the direction D1 can be larger than the pad PD _K-1 And PD _K A distance in the direction D1.

Fig. 2 is another schematic diagram of the electronic device of the present disclosure. Fig. 2 is similar to fig. 1, except that the width of the sensing pads S1 and S2 is greater than the width of the sensing pad PD in the direction D1 ₁ ～PD _K Is measured. In fig. 2, the positions of the sensing signal lines LS1 and LS2 and the sensing pads S1 and S2 are different from those in fig. 1. Also, as shown in FIG. 2, according to some embodiments, a sensing signal line LS1 is located at the signal line LN ₃ And LN ₄ In the meantime. In this example, the signal line LN ₃ And LN ₄ Electrode E connected electrically _{11_3} And E _{12_1} At different pixels (e.g. PIX) ₁₁ And PIX ₁₂ ) In (1). Pixel PIX ₁₁ And a pixel PIX ₁₂ Are different pixels adjacent in the direction D1. The sensing signal line LS1 is arranged in the direction D1 with the pixel PIX ₁₁ Electrically connected signal line LN ₃ And pixel PIX ₁₂ Electrically connected signal line LN ₄ In the meantime. Although the signal line LN of FIG. 2 ₄ Coupling electrode E _{12_1} But are not intended to limit the disclosure. In some embodiments, the signal line LN ₄ More electrodes are connected. For example, in the direction D1, the pixel PIX _M1 To the right of another adjacent pixel (not shown). In this example, a signal line LN ₄ Further connecting adjacent pixels PIX _M1 The electrode of the pixel on the right (not shown). Furthermore, according to some embodiments, the width of the sensing pad S1 in the direction D1 may be larger than the width of the sensing pad PD ₁ ～PD _K At least one of (a) and (b). For example, in the direction D1, the width W24 of the sensing pad S1 may be greater than the pad PD ₂ Width W22. For example, the width W24 of the sensing pad S1 is greater than the width PD of the pad ₁ ～PD ₃ Width W21-W23, and width W28 of sensing pad S2 is greater than pad PD _K-2 、PD _K-1 、PD _K Width W25-W27. In this example, the pad PD ₁ ～PD ₃ The widths W21-W23 can be equal, and the pads PD are connected _K-2 、PD _K-1 、PD _K May be equal, but the disclosure is not limited thereto. The width W21 and the width W25 may be equal or unequal. In addition, in fig. 2, the pad PD ₁ ～PD ₃ And the sensing bonding pads S1 are arranged in sequence in the direction D1, the bonding pads PD _K-2 、PD _K-1 、PD _K And the sensing pads S2 are arranged in sequence in the direction D1.

In the embodiment, in a top view, as shown in fig. 2, in the direction D1, the sensing pad S1 is not located on the pad PD ₂ And PD ₃ In between. In the direction D1, the sensing pad S1 may be located on the pad PD ₃ Outside, the sensing pad S2 may be located at the pad PD _k Outside of (a). In this case, the pad PD ₂ And PD ₃ The distance in the direction D1 may be equal to the pad PD ₂ And PD ₁ A distance in the direction D1. Pad PD ₃ And PD ₄ The distance in the direction D1 can be larger than the pad PD ₂ And PD ₃ A distance in the direction D1. In addition, in a top view, the pad PD _K-1 And PD _K The distance in the direction D1 may be equal to the pad PD _K-1 And PD _K-2 A distance in the direction D1.

Fig. 3 is another schematic view of the electronic device of the present disclosure. Fig. 3 is similar to fig. 1, except that the adjacent pads are staggered in the direction D1. As shown in fig. 3, in the direction D1, the pad PD ₁ And PD ₂ Are arranged adjacently and in a staggered way, and the pads PD are connected ₂ And the sensing pads S1 are arranged adjacently and in a staggered manner. Specifically, in the direction D1, the pad PD ₁ May be misaligned pads PD ₂ The sensing pad S1 may be a non-aligned pad PD ₂ (iii) pad PD ₁ And the sensing pad S1 may be aligned. Pad PD ₁ Sensing connecting pad S1 and connecting pad PD _K-2 And the sensing pads S2 are sequentially arranged and aligned in the direction D1. Pad PD ₂ 、PD ₃ 、PD _K-1 And PD _K Are sequentially arranged and aligned in the direction D1. In this embodiment, in the direction D1, the pad PD is connected ₁ The sensing connecting pad S1 and the connecting pad PD _K-2 And sensing the pad S2 not contacting the pad PD ₂ 、PD ₃ 、PD _K-1 And PD _K And (4) overlapping. In other embodiments, in the direction D1, the pad PD is connected ₁ Sensing connecting pad S1 and connecting pad PD _K-2 And at least one part of the sensing connecting pad S2 and the connecting pad PD ₂ 、PD ₃ 、PD _K-1 And PD _K At least one of which overlap. In the present disclosure, the alignment may mean that the center of the two pads is connected to the direction D1, and the misalignment may mean that the center of the two pads is connected to the direction D1. The direction D1 may be an extending direction of a gate line (shown in fig. 5) on the substrate 110.

Fig. 4 is another schematic view of the electronic device of the present disclosure. Fig. 4 is similar to fig. 3, except that the width W42 of the sensing pad S1 in the direction D1 of fig. 4 is greater than the width of the pad PD ₁ Width W41 of pad PD ₂ Width W43 and pad PD ₃ And the width W46 of the sensing pad S2 in the direction D1 is greater than the width of the pad PD _K-2 Width W45 of, pad PD _K-1 Width W47 and pad PD _K Width W48. According to some embodiments, the width W42 of the sensing pad S1 in the direction D1 may be greater than the width of at least one pad. In the present embodiment, the widths W41, W43 to W45, W47 and W48 may be equal.

As shown in fig. 4, in the direction D1, the pad PD ₁ And a sensing pad S1, wherein the sensing pad S1 and the pad PD are arranged adjacently and in a staggered manner ₂ Are adjacent and staggered. Specifically, in the direction D1, the pad PD ₁ And the sensing pad S1 are not alignedTest pad S1 and pad PD ₂ May be misaligned, and the pads PD ₁ And PD ₂ May be aligned. Pad PD ₁ 、PD ₂ 、PD _K-2 And PD _K-1 Are sequentially arranged and aligned in the direction D1. Sensing pad S1 and pad PD ₃ Sensing connecting pad S2 and connecting pad PD _K Are sequentially arranged and aligned in the direction D1. In other embodiments, in the direction D1, the pad PD is connected ₁ 、PD ₂ 、PD _K-2 And PD _K-1 At least one part of the sensor, the sensing pad S1 and the pad PD ₃ Sensing connecting pad S2 and connecting pad PD _K At least one of (a) and (b) overlap.

The disclosure does not limit the positions of the sensing pads S1 and S2. In this embodiment, the sensing pad S1 is located on the pad PD ₁ And PD ₂ Between, the sensing pad S2 is located at the pad PD _K-2 And PD _K-1 In the meantime. In another possible embodiment, the sensing pad S1 is located on the pad PD ₂ And PD ₃ In between. In another possible embodiment, the sensing pad S2 may be located on the pad PD _K-1 And PD _K In between.

Fig. 5 is another schematic view of the electronic device of the present disclosure. The electronic device 500 includes an array substrate 510 and a circuit board 520. The array substrate 510 includes a substrate 110, and electrodes, signal lines, sensing electrodes, sensing signal lines, pads, and sensing pads 8230, etc. disposed on the substrate 110, as described above with reference to fig. 1, which are not repeated herein. Conductive adhesive A is arranged between the array substrate 510 and the circuit board 520 ₁ ～A _K And AS1. Conductive adhesive A ₁ ～A _K And AS1 for electrically connecting the pads PD of the array substrate 510 ₁ ～PD _K One of the sensing pads S1 and the pad PA of the circuit board 520 ₁ ～PA _K And one of the sensing pads SA1. For example, conductive paste A ₁ Pad PD electrically connected to array substrate 510 ₁ Pad PA with circuit board 520 ₁ The conductive adhesive AS1 electrically connects the sensing pad S1 of the array substrate 510 and the sensing pad SA1 of the circuit board 520, and the conductive adhesive a _K Pad PD electrically connected to array substrate 510 _K Pad PA with circuit board 520 _K . In one possible embodiment, the guideElectric adhesive A ₁ ～A _K And AS1 is an Anisotropic Conductive Film (ACF). In the present embodiment, the structure of the array substrate 510 is similar to that of the array substrate 110S in fig. 1, and is not repeated herein. For convenience of illustration, fig. 5 omits the sensing signal line LS2 and the sensing electrode SE2 of fig. 1.

In some embodiments, the electronic device 500 further includes a gate driver 511 and a plurality of gate lines GL ₁ ～GL _M . For convenience of illustration, only three gate lines are shown in fig. 5, but the disclosure is not limited thereto. The gate driver 511 provides a driving signal to the gate line GL ₁ ～GL _M . Gate line GL ₁ ～GL _M May be disposed on the substrate 110, sequentially arranged in the direction D2, and extending in the direction D1. In this case, the gate driver 511 may be disposed on the substrate 110 at one side (e.g., the left side) of the substrate 110. In the present embodiment, the gate driver 511 can be integrated into the array substrate 510, so the gate driver 511 can be referred to as a Gate On Panel (GOP). In another possible embodiment, the gate driver 511 may be located on another circuit board (different from the array substrate 510). The number and location of the gate drivers are not limited by this disclosure. In another possible embodiment, the electronic device 500 has more gate drivers.

In the present embodiment, the electronic device 500 further includes a plurality of sub-pixels. Each sub-pixel is coupled to a gate line and a signal line. For convenience of illustration, FIG. 5 shows sub-pixels 111-113. The sub-pixel 111 is coupled to the gate line GL ₁ And signal line LN ₁ . The sub-pixel 112 is coupled to the gate line GL ₁ And signal line LN ₂ . The sub-pixel 113 is coupled to the gate line GL ₁ And signal line LN ₃ . In the present embodiment, the signal line LN ₁ Electrically connecting the electrode E in the sub-pixel 111 _{11_1} Over signal line LN ₂ Electrically connected to the electrode E in the sub-pixel 112 _{11_2} Over signal line LN ₃ Electrically connecting the electrode E in the sub-pixel 113 _{11_3} . In one possible embodiment, electrode E _{11_1} ～E _{11_3} Are all pixel electrodes.

Circuit board 520 comprises a pad PA ₁ ～PA _K And a sensing pad SA1. Pad PA ₁ ～PA _K Through the conductive adhesive A ₁ ～A _K Electrically connecting the pad PD ₁ ～PD _K . The sensing pad SA1 is electrically connected to the sensing pad S1 through the conductive adhesive AS1. In other embodiments, the circuit board 520 further includes a processing unit 521. The processing unit 521 is electrically connected to the pad PA ₁ ～PA _K And a sensing pad SA1. In this case, the processing unit 521 passes through the pad PA of the circuit board 520 ₁ ～PA _K And a sensing pad SA1 indirectly electrically connected to the pad PD of the array substrate 510 ₁ ～PD _K And a sensing pad S1. For example, the pad PD ₂ (or called first pad), pad PD ₃ The sensing pad S1 and the processing unit 521 are electrically connected to each other.

The present disclosure does not limit the circuit architecture of the processing unit 521. In one embodiment, the processing unit 521 is a Touch and Display Driver Integration Chip (Touch and Display Driver Integration Chip). During a display period, the processing unit 521 passes through the pad PA ₁ ～PA _K Providing a display signal to the pad PD ₁ ～PD _K . In this example, the pad PD ₁ ～PD _K And pad PA ₁ ～PA _K Also referred to as display pads. Since the sensing pad SA1 is located between two display pads (e.g. PA) ₂ And PA ₃ ) And thus the distance between adjacent display pads is large. Referring to fig. 1 and 5, in the top view, the sensing signal line LS1 is located between two adjacent signal lines LN ₂ And LN ₃ The distance DS2 between adjacent signal lines can be increased, so that the adjacent pad PD on the array substrate 110S (or 510) ₂ And PD ₃ The distance between them increases. And, the corresponding adjacent pads PA on the circuit board 520 electrically connected to the array substrate 110S (or 510) ₂ And PA ₃ The distance between the pads is increased, so that the bonding pad PA can be reduced ₂ And PA ₃ The length of the trace with the processing unit 521, and the impedance of the trace is reduced.

In another embodiment, the processing unit 521 provides a common voltage through the sensing pad SA1 during the display periodThe pre-sensing electrode SE1. At this time, the sensing electrode SE1 serves as a common electrode. During a sensing period, the processing unit 521 provides a sensing signal to the sensing electrode SE1 through the sensing pad SA1, and detects a level change of the sensing electrode SE1. The processing unit 521 determines whether the display area corresponding to the sensing electrode SE1 is touched according to the level change of the sensing electrode SE1. In other embodiments, the processing unit 521 may be integrated into the array substrate 510. In this case, the processing unit 521 can be directly electrically connected to the signal line LN ₁ ～LN _K And a sensing signal line LS1.

In some embodiments, the pad PA of the circuit board 520 ₁ ～PA _K And the position configuration and size of the sensing pad SA1 are determined by the pad PD of the array substrate 510 ₁ ～PD _K And sensing the position configuration and the size of the pad S1. For example, the sensing pad S1 of the array substrate 510 is located on the pad PD ₂ And PD ₃ In between, the sensing pad SA1 of the circuit board 520 is located at the pad PA ₂ And PA ₃ In the meantime. In addition, the width of the sensing pad S1 of the array substrate 510 in the direction D1 and the pad PD ₁ ～PD _K The width in the direction D1 is equal, so the width of the sensing pad SA1 of the circuit board 520 in the direction D1 is equal to the width of the pad PA ₁ ～PA _K The width in the direction D1 is the same.

In other embodiments, as shown in fig. 2, when the width of the sensing pad S1 of the array substrate 510 in the direction D1 is larger than the width of the pad PD ₁ ～PD _K When the width in the direction D1 is larger, the width of the sensing pad SA1 of the circuit board 520 in the direction D1 is larger than the width of the pad PA ₁ ～PA _K Width in direction D1.

Fig. 6 is another schematic view of the electronic device of the present disclosure. Fig. 6 is similar to fig. 5, except that the array substrate 610 of fig. 6 has

gate drivers

611 and 612. In this embodiment, the array substrate 610 may include a plurality of gate lines, and the

gate drivers

611 and 612 may be coupled to different gate lines. For example, the gate driver 611 couples odd gate lines of the plurality of gate lines, such as GL ₁ And GL _M The gate driver 612 is coupled to even gate lines, such as GL ₂ . For convenience of illustration, only three gate lines are shown in fig. 6, but the disclosure is not limited thereto. Since the characteristics of the

gate drivers

611 and 612 are similar to those of the gate driver 511 of fig. 5, they are not described again.

In fig. 6, the electronic device 600 may include an array substrate 610, a first circuit board 620, and a second circuit board 630. The first circuit board 620 may be disposed between the array substrate 610 and the second circuit board 630. The number of the first circuit boards 620 may be one or more, and three first circuit boards 620_1, 620_2, 620 _Pare shown in FIG. 6, but the disclosure is not limited thereto. The array substrate 610 is electrically connected to the first circuit boards 620 u 1 to 620 u p through a conductive adhesive (not shown). Since the characteristics of the first circuit boards 620 _1to 620 _Pare similar to those of the circuit board 520 of FIG. 5, the description thereof is omitted. In addition, the first circuit boards 620 _1to 620 _Pare electrically connected to the second circuit board 630 through conductive adhesives (not shown) for receiving power and signals. For example, a power circuit 631 is disposed in the second circuit board 630 for providing power to the processing units 621 _u1 to 621 _pof the first circuit board 620 _u1 to 620_p. In some embodiments, the first circuit boards 620 _1to 620 _pmay be flexible circuit boards, and the second circuit board 630 may be a rigid circuit board, but the disclosure is not limited thereto.

In other embodiments, the second circuit board 630 further has a Timing Controller (TCON) 632 and a level shift (level shift) 633. The timing controller 632 provides control signals to the processing units 621\ u 1-621_P of the first circuit board 620 _u1-620 _P. The voltage converter 633 provides at least one conversion voltage to the processing units 621 _u1 to 621 _uP of the first circuit board 620 _u1 to 620 _uP. In one embodiment, the second circuit board 630 further includes a display interface (not shown) for receiving an image signal. In this example, the display interface may be an embedded display interface (eDP).

FIG. 7 is a cross-sectional view showing the gate line GL ₁ Signal line LN ₁ ～LN _K The stack relationship between the sensing electrode SE and the sensing signal lines LS1 and LS2 is schematically illustrated. The top view of fig. 1 can be referred to together with the top view of fig. 7.

An array baseThe plate 710S includes a substrate 712, a first conductive layer 714, a second conductive layer 716, and a third conductive layer 720. In the third direction D3, from bottom to top, the first conductive layer 714, the second conductive layer 716, and the third conductive layer 720 are sequentially disposed on the substrate 712. Direction D3 is different from directions D1 and D2, e.g., direction D3 may be perpendicular to directions D1 and 2. According to some embodiments, the direction D3 may be a direction perpendicular to the upper surface of the substrate 712, and may be a normal direction of the substrate 712. An insulating layer 713 is disposed on the upper surface of the substrate 712. A first conductive layer 714 is provided over the upper surface of the insulating layer 713. In one embodiment, the first conductive layer 714 has the gate line of FIG. 5, such as GL ₁ . The insulating layer 715 is disposed on an upper surface of the first conductive layer 714. The second conductive layer 716 is disposed on the upper surface of the insulating layer 715. In one possible embodiment, the second conductive layer 716 includes a signal line LN ₁ ～LN _K . As shown, a signal line LN ₁ ～LN _K Are spaced apart from each other. An insulating layer 717 is disposed on the upper surface of the second conductive layer 716. A common electrode (718) is provided on the upper surface of the insulating layer 717. In one possible embodiment, the common electrode 718 also serves as the sensing electrode SE. The common electrode 718 is maintained at a common voltage, such as 0V, during a display period. During a sensing period, the common electrode 718 receives a sensing voltage. During this time, if the common electrode 718 is not touched, the voltage of the common electrode 718 is equal to the sensing voltage. However, when the common electrode 718 is touched, the voltage of the common electrode 718 is no longer equal to the sensing voltage. Therefore, by detecting the voltage variation of the common electrode 718, it can be known whether the common electrode 718 is touched. According to some embodiments, the first conductive layer 714, the second conductive layer 716, and the third conductive layer 720 may be metal layers, but the disclosure is not limited thereto. For convenience of explanation, fig. 7 does not show the pixel electrode. According to some embodiments, the pixel electrode may be disposed between the second conductive layer 716 and the third conductive layer 720, and may be disposed above or below the common electrode 718, which is not limited in the present disclosure.

The insulating layer 719 is provided on the upper surface of the common electrode 718. The third conductive layer 720 is disposed over the insulating layer 719. In one embodiment, the third conductive layer 720 may includeSense signal lines (e.g., LS1 and LS 2). The projection position and LN of the sensing signal line on the substrate 712 ₁ ～LN _K Does not overlap with the projected position of the substrate 712. The insulating layer 721 is disposed on the upper surface of the third conductive layer 720. The liquid crystal layer 722 is disposed between the color filter substrate 723 and the array substrate 710S. The polarizer 711 may be disposed on the lower surface of the substrate 712, and the polarizer 724 may be disposed on the upper surface of the color filter substrate 723. The cover plate layer 725 may be disposed on the upper surface of the polarizer 724.

As shown in FIG. 7, the second conductive layer 716 may include a signal line LN ₁ ～LN _K . The third conductive layer 720 may include sensing signal lines (e.g., LS1 and LS 2). That is, the signal line LN ₁ ～LN _K And the sensing signal lines (e.g., LS1 and LS 2) may be located at different layers. For example, as shown in FIG. 1, a signal line LN ₂ And the sensing signal line LS1 may be located at different layers.

Fig. 8 is another schematic view of the electronic device of the present disclosure. In the embodiment, the electronic device 800 includes an array substrate 810 and circuit boards 820 u 1 to 820 u p. The array substrate 810 is electrically connected to the circuit boards 820 u 1-820 u P through the conductive adhesive. Since the structure of the array substrate 810 is similar to that of the array substrate 110S of fig. 1, the description thereof is omitted. In addition, the characteristics of circuit boards 820_1-820_P are similar to those of circuit board 520 of FIG. 5, and thus are not repeated.

In the embodiment, at least one of the circuit boards 820_1-820_P has dummy pads (dummy pads). For example, circuit board 820_2 has a dummy pad PC1, and circuit board 820 _phas a dummy pad PC2. The disclosure does not limit the location of the dummy pads. In FIG. 8, the vacant pad PC1 of circuit board 820_2 is located approximately in the middle of processing unit 821_2, while the vacant pad PC2 of circuit board 820_P is located approximately to the right of processing unit 821_P. In addition, the number of the empty connecting pads of each circuit board is not limited in the disclosure. In some embodiments, at least one of circuit boards 820 _1-820 _Pmay have more dummy pads.

Since the characteristics of the dummy pads PC1 and PC2 are similar, the function of the dummy pad PC1 will be described by taking circuit board 820 u 2 as an example. In some embodiments, when the processing unit 821_2 cannot be electrically connected to the array substrate 810 through the defective traces or the defective pads, the processing unit 821_2 can be electrically connected to the array substrate 810 by using the dummy pads PC 1. In some embodiments, the processing unit 821_2 sets the dummy pad PC1 to a high impedance (high-Z) state when the processing unit 821_2 does not output a signal to the array substrate 810 through the dummy pad PC 1.

Fig. 9 is a schematic diagram of a processing unit of the present disclosure. The processing unit 900 includes an analog circuit (analog circuit) 910, a Micro Control Unit (MCU) 920, a touch sensing circuit (touch sensing circuit) 930, a display driving circuit (display driving circuit) 940, a High-impedance circuit (High-zcirc) 950, a register setting circuit (register setting circuit) 960, switches 971-973, and a pad 980. In some embodiments, the processing unit 900 may be the processing unit in the previous embodiments, such as the processing unit 521 of FIG. 5 or any of the processing units 821 \1-821_P of FIG. 8.

During a display period, the micro-control circuit 920 controls the analog circuit 910 to enable a trigger signal SO2 via a control signal SC. The display driving circuit 940 generates a display signal SD according to the trigger signal SO2. At this time, the micro control circuit 920 drives the buffer setting circuit 960, so that the buffer setting circuit 960 enables a switching signal B. Therefore, the switch 972 is turned on to transmit the display signal SD to the pad 980. In one possible embodiment, the processing unit 900 functions as the processing unit 521 of FIG. 5. In this example, the pad 980 is electrically coupled to the pad PD of the array substrate 510 of fig. 5 ₁ . In this example, electrode E of subpixel 111 _{11_1} The display signal SD is received.

During a sensing period, the micro control circuit 920 controls the analog circuit 910 to enable a trigger signal SO1 via the control signal SC. The touch sensing circuit 930 generates a sensing signal ST according to the trigger signal SO1. During sensing, the micro control circuit 920 drives the buffer setting circuit 960, so that the buffer setting circuit 960 enables a switching signal A. Therefore, the switch 971 is turned on to transmit the sensing signal ST to the pad 980. In one possible embodiment, the processing unit 900 functions as the processing unit 521 of FIG. 5. In this case, the pad 980 is electrically coupled to the sensing pad S1 of the array substrate 510 of fig. 5. In this example, the sense electrode SE receives a sense signal ST.

In other embodiments, when the pad 980 is an empty pad, the micro-control circuit 920 drives the register setting circuit 960, such that the register setting circuit 960 enables a switching signal C. Thus, the switch 973 is turned on. The high impedance circuit 950 sets the pad 980 to a high impedance state.

In one embodiment, the register setting circuit 960 has two registers (not shown). The micro control circuit 920 sets the values of the two registers of the register setting circuit 960. The register setting circuit 960 enables one of the switching signals A-C according to the values of the two internal registers. For example, when the micro-control circuit 920 sets the values of the two registers of the register setting circuit 960 to 01, the register setting circuit 960 enables the switching signal A. When the micro control circuit 920 sets the values of the two registers of the register setting circuit 960 to 10, the register setting circuit 960 enables the switching signal B. When the micro control circuit 920 sets the values of the two registers of the register setting circuit 960 to 00, the register setting circuit 960 enables the switching signal C.

In summary, according to some embodiments, the positions of the sensing pads and the pads on the array substrate can be adjusted by adjusting the positions of the sensing signal lines and the signal lines. According to some embodiments, the sensing signal lines are located between two adjacent signal lines in the top view, and the distance between the adjacent signal lines can be increased, so that adjacent pads (e.g., PDs) on the array substrate (e.g., 510) can be formed ₂ And PD ₃ ) The distance between them increases. And, the corresponding adjacent pads (e.g., PA) on the circuit board (e.g., 520) electrically connected to the array substrate ₂ And PA ₃ ) The distance between the pads is increased, thereby reducing the pad (such as PA) ₂ And PA ₃ ) The length of the trace with the processing unit (such as 521) and reduce the impedance of the trace. Therefore, the electrical performance of the sensing electrode can be improved, the process yield is stable, and the reliability of the whole electronic device is improved.

Although the present disclosure has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. For example, the systems, devices, or methods described in the embodiments of the present disclosure may be implemented in hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present disclosure should be determined by the appended claims.

Claims

1. An electronic device, characterized in that:

a substrate;

a first electrode disposed on the substrate;

a second electrode disposed on the substrate and adjacent to the first electrode in a first direction;

a first signal line electrically connected to the first electrode;

a second signal line electrically connected to the second electrode;

a sensing electrode; and

and a sensing signal line electrically connected to the sensing electrode, wherein in a plan view, the sensing signal line is disposed between the first signal line and the second signal line in the first direction.

2. The electronic device of claim 1, further comprising:

a first pad disposed on the substrate;

a second pad disposed on the substrate; and

a sensing pad disposed on the substrate, wherein the first pad is electrically connected to the first signal line, the second pad is electrically connected to the second signal line, and the sensing pad is electrically connected to the sensing signal line.

3. The electronic device as recited in claim 2, wherein said sensing pad is disposed between said first pad and said second pad in said first direction.

4. The electronic device of claim 2, further comprising:

a third signal line;

a third pad; and

a third electrode adjacent to the first electrode in the first direction, wherein the third electrode is electrically connected to the third pad through the third signal line, wherein in the top view, a distance between the first pad and the second pad in the first direction is a distance between the first pad and the third pad in the first direction.

5. The electronic device of claim 2, wherein in the top view, a width of the sensing pad is greater than a width of the first pad in the first direction.

6. The electronic device of claim 2, further comprising:

a processing unit, wherein the first pad, the second pad and the sensing pad are electrically connected to the processing unit.

7. The electronic device of claim 2, wherein the sensing pad is misaligned with the first pad in the first direction.

8. The electronic device of claim 1, wherein the sensing electrode and the first electrode are located in different layers.

9. The electronic device of claim 1, wherein the first signal line and the sensing signal line are located in different layers.

10. The electronic device of claim 1, wherein the sensing electrode overlaps the first electrode and the second electrode in the top view.