CN115701637A - Memory computing circuit and method and resistive random access memory - Google Patents
Memory computing circuit and method and resistive random access memory Download PDFInfo
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Abstract
The invention provides a memory computing circuit and method and a resistive random access memory, wherein a first transistor and a second transistor in a j storage unit adopt a common-gate-common-source connection mode, so that an ith bit line, an ith complementary bit line and an ith source line are subjected to charge sharing. The voltage on the ith source line connected with the ith voltage reading circuit is the result of subtracting the positive product and the negative product of the input value of the word line and the storage of the storage unit, and more reading structures are not needed, so that the occupied area and the time delay expense of the memory calculation circuit are saved. Due to the connection mode of the memory unit, the bit line, the source line and the complementary bit line, the memory calculation process is essentially equivalent to the calculation of a differential signal, and further the influence of non-ideal factors such as process fluctuation on the calculation accuracy can be inhibited.
Description
Technical Field
The invention relates to the technical field of resistive random access memories, in particular to a memory computing circuit and method and a resistive random access memory.
Background
By effectively reducing power consumption and delay caused by frequent memory access, the memory computing technology based on the novel non-volatile memory is expected to greatly improve computing energy efficiency and computing power, and therefore hardware support is provided for computing tasks which take artificial intelligence as a representative and take data as a center. Among them, resistive Random Access Memories (RRAMs) have shown great potential in terms of operating power consumption, integration density, and process compatibility. The novel nonvolatile memory represented by a Resistive Random Access Memory (RRAM) has the characteristics of low power consumption, small delay, high density and high process compatibility, and the nonvolatile memory computing technology based on the RRAM can effectively reduce data movement between a processor and a memory and between memory levels (nonvolatile memory to memory), thereby greatly reducing power consumption and delay caused by the data movement, and breaking through the bottleneck caused by a memory wall. Existing memory computing techniques are subject to improvement.
Disclosure of Invention
In view of this, the present invention provides a memory computing circuit and method and a resistive random access memory, which effectively solve the technical problems existing in the prior art, reduce the power consumption of the memory computing circuit, save the occupied area and the time delay overhead of the memory computing circuit, and can suppress the influence of non-ideal factors such as process fluctuation on the computing accuracy.
In order to realize the purpose, the technical scheme provided by the invention is as follows:
an in-memory computing circuit, comprising: the memory comprises a first bit line to an Mth bit line, a first complementary bit line to an Mth complementary bit line, a first source line to an Mth source line, a first voltage reading circuit to an Mth voltage reading circuit and a first word line to an Nth word line, wherein M and N are integers more than 0;
a first memory cell to an Nth memory cell are connected between the ith bit line and the ith complementary bit line, the jth memory cell comprises a first anti-modulation device, a second anti-modulation device, a first transistor and a second transistor, the first end of the first anti-modulation device is connected with the ith bit line, the second end of the first anti-modulation device is connected with the first end of the first transistor, the second end of the first transistor is connected with the ith source line, and the grid of the first transistor is connected with the jth word line; a first end of the second anti-modulation device is connected with an ith complementary bit line, a second end of the second anti-modulation device is connected with a first end of a second transistor, a second end of the second transistor is connected with the ith source line, a grid electrode of the second transistor is connected with a jth word line, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N;
and the ith source line is connected with the ith voltage reading circuit; the ith bit line is connected with a first voltage signal, the ith complementary bit line is connected with a second voltage signal, and the ith source line is connected with a third voltage signal.
Optionally, the first voltage signal is a high level signal, and the voltage value is Vh.
Optionally, the second voltage signal is a low level signal, and the voltage value is Vl.
Optionally, the voltage value of the third voltage signal is V MID ＝(Vh+Vl)/2。
Optionally, the first transistor and the second transistor are N-type transistors.
Optionally, the ith voltage reading circuit is an ith analog-to-digital converter.
Correspondingly, the invention also provides an in-memory computing method, which adopts the in-memory computing circuit and comprises the following steps:
the ith bit line, the ith complementary bit line and the ith source line are precharged, wherein the ith bit line is accessed with a first voltage signal, the ith complementary bit line is accessed with a second voltage signal, and the ith source line is accessed with a third voltage signal.
Optionally, after the pre-charging, the method includes:
and selecting a plurality of preset word lines from the first word line to the Nth word line to be started according to input data, and reading the transient voltage variation of the ith source line by the ith voltage reading circuit.
Correspondingly, the invention also provides a resistive random access memory which comprises the memory computing circuit.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a memory computing circuit and method and a resistance change type memory, comprising: the memory cell comprises a first bit line to an Mth bit line, a first complementary bit line to an Mth complementary bit line, a first source line to an Mth source line, a first voltage reading circuit to an Mth voltage reading circuit and a first word line to an Nth word line, wherein M and N are integers more than 0; a first memory cell to an Nth memory cell are connected between the ith bit line and the ith complementary bit line, the jth memory cell comprises a first anti-modulation device, a second anti-modulation device, a first transistor and a second transistor, the first end of the first anti-modulation device is connected with the ith bit line, the second end of the first anti-modulation device is connected with the first end of the first transistor, the second end of the first transistor is connected with the ith source line, and the grid of the first transistor is connected with the jth word line; a first end of the second inhibitor is connected with an ith complementary bit line, a second end of the second inhibitor is connected with a first end of a second transistor, a second end of the second transistor is connected with the ith source line, a grid electrode of the second transistor is connected with a jth word line, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; and the ith source line is connected with the ith voltage reading circuit; the ith bit line is connected with a first voltage signal, the ith complementary bit line is connected with a second voltage signal, and the ith source line is connected with a third voltage signal.
According to the technical scheme provided by the invention, the first transistor and the second transistor in the jth storage unit adopt a common-gate-common-source connection mode, so that the ith bit line, the ith complementary bit line and the ith source line are subjected to charge sharing.
In addition, in the technical scheme provided by the invention, the voltage on the ith source line connected with the ith voltage reading circuit is the result of subtracting the positive and negative products of the input value of the word line and the storage of the storage unit, so that more reading structures are not required to be arranged, and the occupied area and the time delay expense of the memory calculation circuit are saved.
In addition, according to the technical scheme provided by the invention, due to the connection mode of the storage unit, the bit line, the source line and the complementary bit line, the memory calculation process is essentially equivalent to the calculation of a differential signal, and the influence of non-ideal factors such as process fluctuation on the calculation accuracy can be further inhibited.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a memory computing circuit according to an embodiment of the present invention;
FIG. 2 is a diagram of simulation data provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of another memory computing circuit according to an embodiment of the present invention;
fig. 4 is a flowchart of an in-memory computing method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, by effectively reducing power consumption and delay caused by frequent memory accesses, the memory computing technology based on the novel nonvolatile memory is expected to greatly improve computing energy efficiency and computing power, thereby providing hardware support for data-centric computing tasks represented by artificial intelligence. Among them, resistive Random Access Memories (RRAMs) have shown great potential in terms of operating power consumption, integration density, and process compatibility. The novel nonvolatile memory represented by a Resistive Random Access Memory (RRAM) has the characteristics of low power consumption, small delay, high density and high process compatibility, and the nonvolatile memory computing technology based on the RRAM can effectively reduce data transfer between a processor and a memory and between memory levels (nonvolatile memory to memory), thereby greatly reducing power consumption and delay caused by the data transfer, and breaking through the bottleneck caused by a memory wall. Existing memory computing techniques are subject to improvement.
Based on this, the embodiments of the present invention provide a memory computing circuit and method, and a resistive random access memory, which effectively solve the technical problems in the prior art, reduce the power consumption of the memory computing circuit, save the occupied area and the delay overhead of the memory computing circuit, and can suppress the influence of non-ideal factors such as process fluctuation on the computation accuracy.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 4.
Example one
Referring to fig. 1, a schematic structural diagram of a memory computing circuit according to an embodiment of the present invention is shown, where the memory computing circuit includes: the memory cell includes first to mth bit lines BL1 to BLm, first to mth complementary bit lines BLB1 to BLBm, first to mth source lines SL1 to SLm, first to mth voltage reading circuits 101 to 10M, and first to nth word lines WL1 to WLn, where M and N are integers greater than 0.
A first memory cell to an Nth memory cell are connected between the ith bit line BLi and the ith complementary bit line BLBi, the jth memory cell 20 comprises a first inhibitor 211, a second inhibitor 221, a first transistor 212 and a second transistor 222, a first end of the first inhibitor 211 is connected with the ith bit line BLi, a second end of the first inhibitor 211 is connected with a first end of the first transistor 212, a second end of the first transistor 212 is connected with the ith source line SLi, and a gate of the first transistor 212 is connected with the jth word line WLj; the first end of the second inhibitor 221 is connected to the ith complementary bit line BLBi, the second end of the second inhibitor 221 is connected to the first end of the second transistor 222, the second end of the second transistor 222 is connected to the ith source line SLi, the gate of the second transistor 222 is connected to the jth word line WLj, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N.
And the ith source line SLi is connected with the ith voltage reading 10i circuit; in the pre-charging stage, the ith bit line BLi is connected to a first voltage signal, the ith complementary bit line BLBi is connected to a second voltage signal, and the ith source line SLi is connected to a third voltage signal.
It can be understood that in the technical solution provided in the embodiment of the present invention, the first transistor and the second transistor in the jth memory cell adopt a cascode connection mode, so that the ith bit line, the ith complementary bit line and the ith source line perform charge sharing.
In addition, in the technical scheme provided by the embodiment of the invention, the voltage on the ith source line connected with the ith voltage reading circuit is the result of subtracting the positive and negative products of the input value of the word line and the storage value of the storage unit, so that more reading structures are not required to be arranged, and the occupied area and the time delay expense of the memory calculation circuit are saved.
In addition, according to the technical scheme provided by the embodiment of the invention, due to the connection mode of the storage unit, the bit line, the source line and the complementary bit line, the memory calculation process is essentially equivalent to the calculation of a differential signal, and the influence of non-ideal factors such as process fluctuation on the calculation accuracy can be further inhibited.
The working principle of the memory computing circuit provided by the embodiment of the invention comprises two stages, namely a pre-charging stage and an evaluation stage. In the pre-charging stage, all word lines are closed, and voltage ends respectively connected with the bit lines, the complementary bit lines and the source lines are connected for pre-charging (after the voltage ends are disconnected, the potentials can be kept by respectively connected capacitors); the first voltage signal is input to the ith bit line and charged to a corresponding voltage, the second voltage signal is input to the ith complementary bit line and charged to a corresponding voltage, and the third voltage signal is input to the ith source line and charged to a corresponding voltage. The first voltage signal provided by the embodiment of the invention is a high level signal, and the voltage value is Vh. The second voltage signal is a low level signal and has a voltage value of Vl. And the voltage value of the third voltage signal is V MID ＝(Vh+Vl)/2。
And then entering an evaluation stage, disconnecting paths between the voltage end and the bit line, between the complementary bit line and the source line, and starting a plurality of preset word lines according to input data. Further, the total resistance R of all the first resistors connected in parallel between the ith bit line and the ith source line LTOT Total resistance R of all second resistors connected in parallel between the ith complementary bit line and the ith source line RTOT Determining transient charging or transient discharging of the ith source line according to the relative magnitude relation of the voltage on the ith source line, and determining increase or decrease of the transient voltage on the ith source line; e.g. when R is LTOT Less than R RTOT When the voltage on the ith source line is higher than the voltage on the ith source line, the charging speed of the ith bit line to the ith source line is higher than the discharging speed of the ith complementary bit line to the ith source line; when R is LTOT Greater than R RTOT While, the ith bit line pairThe charging speed of the ith source line is slower than the discharging speed of the ith complementary bit line to the ith source line, and the transient voltage on the ith source line is reduced. At the moment, the transient voltage variation of the ith source line is read by an ith voltage reading circuit, and a result of subtracting the positive and negative products of the input value of the ith word line and the stored value of the corresponding connected storage unit is obtained. The output result of the ith voltage reading circuit may be a digital signal, and the present invention is not limited in particular.
It can be understood that, according to the technical solution provided by the embodiment of the present invention, the memory computing circuit is obtained based on the charge sharing design of the ith bit line, the ith complementary bit line and the ith source line. At the ith source line, the gates of a first transistor and a second transistor in the jth memory cell share a jth word line, the second ends of the first transistor and the second transistor are connected with the same ith source line, and a first resistance changer is recorded as R L And the second resistance changer is denoted as R H . When the j-th storage unit represents a signed number, the coding method shown in table 1 can be adopted:
TABLE 1
Where GND indicates that the WLj word line is off and encoded as 0, and VDD indicates that the WLj word line is on and encoded as 1. When WLj word line is turned on, the code is +1, R L Is in a Low Resistance State (LRS), R H High Resistance State (HRS), transient voltage increase of SLi; when the code is represented as-1, R L Is in a high resistance state, R H The low resistance state, the transient voltage of SLi is reduced; when the code is represented as 0, R L And R H Both are in high impedance state, and the transient voltage of SLi is unchanged.
Further referring to fig. 2, a simulation graph is provided according to an embodiment of the present invention, in which the ordinate is the voltage (in V) of SLi and the abscissa is the time (in us). FIG. 2 simulation of data with word line turned onThe number of (2) is 9 for example. Referring to the 9 curves in FIG. 2, if R is connected to 9 word lines L All are in low resistance state, and R to which 9 word lines are connected H Are all in a high resistance state, when R is LTOT Has the smallest value of R RTOT Is the highest, the transient voltage on SLi rises the highest (i.e., the transient voltage is greater than 0.8V corresponding to fig. 2). With R L The number of the middle and low resistance states is reduced, and R H The number of the middle and low resistance states is increased, and the transient voltage on the SLi is correspondingly reduced; and, R connected to 9 word lines L All are in high resistance state, and R connected by 9 word lines H In both low impedance states, the transient voltage on SLi drops to a minimum with a related trend as shown by the dashed arrow in FIG. 2. As can be seen from the data in the manner shown in fig. 2, the memory computing circuit provided by the embodiment of the present invention has correct functions.
As shown in fig. 3, a schematic structural diagram of another memory computing circuit provided in an embodiment of the present invention is shown, where the memory computing circuit includes: the memory cell includes first to mth bit lines BL1 to BLm, first to mth complementary bit lines BLB1 to BLBm, first to mth source lines SL1 to SLm, first to mth voltage reading circuits 101 to 10M, and first to nth word lines WL1 to WLn, where M and N are integers greater than 0.
A first memory cell to an Nth memory cell are connected between an ith bit line BLi and an ith complementary bit line BLBi, a jth memory cell 20 comprises a first blocking device 211, a second blocking device 221, a first transistor 212 and a second transistor 222, a first end of the first blocking device 211 is connected with the ith bit line BLi, a second end of the first blocking device 211 is connected with a first end of the first transistor 212, a second end of the first transistor 212 is connected with an ith source line SLi, and a gate of the first transistor 212 is connected with a jth word line WLj; the first end of the second inhibitor 221 is connected to the ith complementary bit line BLBi, the second end of the second inhibitor 221 is connected to the first end of the second transistor 222, the second end of the second transistor 222 is connected to the ith source line SLi, the gate of the second transistor 222 is connected to the jth word line WLj, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N.
And the ith source line SLi is connected to the ith voltage reading 10i circuit; in the pre-charging stage, the ith bit line BLi is connected to a first voltage signal, the ith complementary bit line BLBi is connected to a second voltage signal, and the ith source line SLi is connected to a third voltage signal.
As shown in fig. 3, the first transistor 212 and the second transistor 222 provided by the present invention are both N-type transistors.
As shown in fig. 3, the ith voltage reading circuit 10i provided in the embodiment of the present invention may be an ith analog-to-digital converter, and the present invention is not limited in particular.
Example two
Correspondingly, the embodiment of the invention also provides a memory computing method, which adopts the memory computing circuit provided by any one of the embodiments. As shown in fig. 4, which is a flowchart of an in-memory computing method provided in an embodiment of the present invention, the method includes:
s1, the ith bit line, the ith complementary bit line and the ith source line are precharged, wherein the ith bit line is accessed to a first voltage signal, the ith complementary bit line is accessed to a second voltage signal, and the ith source line is accessed to a third voltage signal.
As shown in fig. 4, after the pre-charging in step S1, the method includes:
s2, selecting a plurality of preset word lines from the first word line to the Nth word line to be started according to input data, and reading the transient voltage variation of the ith source line by the ith voltage reading circuit.
It can be understood that in the technical solution provided in the embodiment of the present invention, the first transistor and the second transistor in the jth memory cell adopt a cascode connection mode, so that the ith bit line, the ith complementary bit line and the ith source line perform charge sharing.
In addition, in the technical scheme provided by the embodiment of the invention, the voltage on the ith source line connected with the ith voltage reading circuit is the result of subtracting the positive and negative products of the input value of the word line and the storage value of the storage unit, so that more reading structures are not required to be arranged, and the occupied area and the time delay expense of the memory calculation circuit are saved.
In addition, according to the technical scheme provided by the embodiment of the invention, due to the connection mode of the storage unit, the bit line, the source line and the complementary bit line, the memory calculation process is essentially equivalent to the calculation of a differential signal, and the influence of non-ideal factors such as process fluctuation on the calculation accuracy can be further inhibited.
EXAMPLE III
Correspondingly, the embodiment of the invention further provides a resistance change type memory, which comprises the memory computing circuit provided by any one of the above embodiments.
The embodiment of the invention provides a memory computing circuit and a method and a resistance variable memory, comprising: the memory cell comprises a first bit line to an Mth bit line, a first complementary bit line to an Mth complementary bit line, a first source line to an Mth source line, a first voltage reading circuit to an Mth voltage reading circuit and a first word line to an Nth word line, wherein M and N are integers more than 0; a first memory cell to an Nth memory cell are connected between the ith bit line and the ith complementary bit line, the jth memory cell comprises a first anti-modulation device, a second anti-modulation device, a first transistor and a second transistor, the first end of the first anti-modulation device is connected with the ith bit line, the second end of the first anti-modulation device is connected with the first end of the first transistor, the second end of the first transistor is connected with the ith source line, and the grid of the first transistor is connected with the jth word line; a first end of the second anti-modulation device is connected with an ith complementary bit line, a second end of the second anti-modulation device is connected with a first end of a second transistor, a second end of the second transistor is connected with the ith source line, a grid electrode of the second transistor is connected with a jth word line, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N; and the ith source line is connected with the ith voltage reading circuit; the ith bit line is connected with a first voltage signal, the ith complementary bit line is connected with a second voltage signal, and the ith source line is connected with a third voltage signal.
As can be seen from the above, in the technical solution provided in the embodiment of the present invention, the first transistor and the second transistor in the jth memory cell adopt a cascode connection mode, so that the ith bit line, the ith complementary bit line, and the ith source line perform charge sharing.
In addition, in the technical scheme provided by the embodiment of the invention, the voltage on the ith source line connected with the ith voltage reading circuit is the result of subtracting the positive and negative products of the input value of the word line and the storage value of the storage unit, so that more reading structures are not required to be arranged, and the occupied area and the time delay expense of the memory calculation circuit are saved.
In addition, according to the technical scheme provided by the embodiment of the invention, due to the connection mode of the memory unit and the bit line, the source line and the complementary bit line, the memory calculation process is essentially equivalent to the calculation of a differential signal, and the influence of non-ideal factors such as process fluctuation on the calculation accuracy can be further inhibited.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. An in-memory computation circuit, comprising: the memory cell comprises a first bit line to an Mth bit line, a first complementary bit line to an Mth complementary bit line, a first source line to an Mth source line, a first voltage reading circuit to an Mth voltage reading circuit and a first word line to an Nth word line, wherein M and N are integers more than 0;
a first memory cell to an Nth memory cell are connected between the ith bit line and the ith complementary bit line, the jth memory cell comprises a first anti-modulation device, a second anti-modulation device, a first transistor and a second transistor, the first end of the first anti-modulation device is connected with the ith bit line, the second end of the first anti-modulation device is connected with the first end of the first transistor, the second end of the first transistor is connected with the ith source line, and the grid of the first transistor is connected with the jth word line; a first end of the second anti-modulation device is connected with an ith complementary bit line, a second end of the second anti-modulation device is connected with a first end of a second transistor, a second end of the second transistor is connected with the ith source line, a grid electrode of the second transistor is connected with a jth word line, i is a positive integer less than or equal to M, and j is a positive integer less than or equal to N;
and the ith source line is connected with the ith voltage reading circuit; wherein the ith bit line is accessed to a first voltage signal, the ith complementary bit line is accessed to a second voltage signal, and the ith source line is accessed to a third voltage signal.
2. The memory computing circuit of claim 1, wherein the first voltage signal is a high signal and the voltage value is Vh.
3. The memory computing circuit of claim 2, wherein the second voltage signal is a low level signal and has a voltage value of Vl.
4. The memory computing circuit of claim 3, wherein the third voltage signal has a voltage value of V MID ＝(Vh+Vl)/2。
5. The memory computing circuit of claim 1, wherein the first transistor and the second transistor are N-type transistors.
6. The memory computing circuit of claim 1, wherein the ith voltage reading circuit is an ith analog-to-digital converter.
7. An in-memory computing method using the in-memory computing circuit of any one of claims 1 to 6, the method comprising:
and precharging the ith bit line, the ith complementary bit line and the ith source line, wherein the ith bit line is accessed to a first voltage signal, the ith complementary bit line is accessed to a second voltage signal, and the ith source line is accessed to a third voltage signal.
8. The memory computing method of claim 7, comprising, after the pre-charging:
and selecting a plurality of preset word lines from the first word line to the Nth word line to be started according to input data, and reading the transient voltage variation of the ith source line by the ith voltage reading circuit.
9. A resistive random access memory comprising the in-memory computation circuit of any one of claims 1 to 6.
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