CN114743580A - Charge sharing memory computing device - Google Patents
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- CN114743580A CN114743580A CN202210658942.3A CN202210658942A CN114743580A CN 114743580 A CN114743580 A CN 114743580A CN 202210658942 A CN202210658942 A CN 202210658942A CN 114743580 A CN114743580 A CN 114743580A
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a charge sharing memory computing device, which relates to the field of memory computing and comprises a memory cell array and a bit line coupling module; the storage and calculation unit array comprises two columns of storage and four rows of storage and calculation units, each storage and calculation unit comprises an inverter and a storage unit, the input end of each inverter is connected with the weight storage node of the corresponding storage unit, the output end of each inverter of the first column of storage and calculation units is connected with a bit line BL, the output end of each inverter of the second column of storage and calculation units is connected with a bit line BLB, the bit line BL and the bit line BL of the first column of storage and calculation units are connected through a switch, and the bit line BL and the bit line BLB of the second column of storage and calculation units are connected through a switch; the bit line coupling module comprises coupling capacitors, and each column of bit lines is provided with a capacitor; the bit line coupling module is used for outputting the voltage value with high accumulated voltage in the bit line BL and the bit line BLB of the second column of memory cells. The invention expands the quantifiable voltage range.
Description
Technical Field
The present invention relates to the field of memory computing technologies, and in particular, to a charge sharing memory computing device.
Background
In recent years, there has been an increasing demand for Artificial Intelligence (AI) for energy efficient computing systems, including edge intelligence and its applications, where deep convolutional neural networks (DNN) in artificial intelligence systems require a large number of parallel product (MAC) operations. During MAC operation, data transmission between Processing Elements (PEs) and memory is inevitably subject to a large amount of weight and intermediate output, which results in unavoidable power consumption and delay, thereby limiting certain AI applications, such as battery-powered edge devices. Thus, a memory Computation (CIM) architecture has emerged that performs power-efficient parallel MAC operations by concurrently accessing multiple cells on a Bit Line (BL) of the intra-mode memory. This greatly reduces the amount of intermediate data generated and facilitates the speed of parallel computing.
The traditional memory calculation single-bit implementation scheme occupies a larger memory calculation unit area when performing model inference calculation with larger network scale and more weight bits, so that the hardware cost is higher. Meanwhile, the voltage domain memory is adopted for calculation, so that the technical difficulty that the range of quantifiable voltage is small and accurate quantification is difficult exists. Secondly, when the method is carried out, a reading interference phenomenon exists by adopting a 6TSRAM storage unit, and a computing circuit influences a weight value.
Disclosure of Invention
The invention aims to provide a charge sharing memory computing device, which enlarges the quantifiable voltage range.
In order to achieve the purpose, the invention provides the following scheme:
a charge-sharing memory computing device comprises a memory cell array, a bit line coupling module, a first switch and a second switch; the storage and calculation unit array comprises two columns of storage and calculation units with four rows, each storage and calculation unit comprises an inverter and an SRAM storage unit, the input end of each inverter is connected with a weight storage node corresponding to the SRAM storage unit, the output end of the inverter of the first column of storage and calculation unit is connected with a bit line BL, the output end of the inverter of the second column of storage and calculation unit is connected with a bit line BLB, the bit line BL of the first column of storage and calculation unit is connected with the bit line BL of the second column of storage and calculation unit through the first switch, the bit line BL of the second column of storage and the bit line BLB of the second column of storage and calculation unit are connected through the first switch, and the word lines of the SRAM storage units in each row of storage and calculation units are connected in a collinear mode; the bit line coupling module comprises a coupling capacitor unit and a bit line comparison output unit, the coupling capacitor unit comprises a first coupling capacitor, a second coupling capacitor, a third coupling capacitor and a fourth coupling capacitor, the first end of the first coupling capacitor is connected with the bit line BL of the first row of storage units, the second end of the first coupling capacitor is grounded, the first end of the second coupling capacitor is connected with the bit line BLB of the first row of storage units, the second end of the second coupling capacitor is grounded, the first end of the third coupling capacitor is connected with the bit line BL of the second row of storage units, the second end of the third coupling capacitor is grounded, the first end of the fourth coupling capacitor is connected with the bit line BLB of the second row of storage units, and the second end of the fourth coupling capacitor is grounded; when a coupling capacitor exists in the coupling capacitor unit for charging, the first switch and the second switch are both switched off; when no coupling capacitor exists in the coupling capacitor unit for charging, the first switch and the second switch are both turned on, and the bit line comparison output unit is used for outputting a voltage value with a high accumulated voltage in the bit line BL of the second row of storage units and the bit line BLB of the second row of storage units.
Optionally, the bit line comparison output unit includes a comparator and a selector, the bit line BL of the first column of storage units is connected to the first input terminal of the comparator, the bit line BLB of the first column of storage units is connected to the second input terminal of the comparator, the signal output by the output terminal of the comparator is used as the enable signal of the selector, the bit line BL of the second column of storage units is connected to the first input terminal of the selector, the bit line BLB of the second column of storage units is connected to the second input terminal of the selector, and the output of the selector is the voltage accumulation output of the storage unit array.
Optionally, the bit line comparison output unit further includes a third switch and a fourth switch, and when the comparator receives the enable signal, the third switch and the fourth switch are turned on.
Alternatively, the word lines input by the storage units in each row are all 2-bit values, the unit pulse width of the word line input by the storage unit in the first row is T0, the unit pulse width of the word line input by the storage unit in the second row is 2T0, the unit pulse width of the word line input by the storage unit in the third row is 3T0, and the unit pulse width of the word line input by the storage unit in the fourth row is 4T 0.
Optionally, the SRAM memory cell is a 6T-SRAM memory cell.
Optionally, the 6T-SRAM memory cell comprises tube TP1, tube TP2, tube TN1, tube TN2, tube TN3, and tube TN 4; the gate of the tube TP1 is connected with the gate of the tube TN1, the drain of the tube TP2, the drain of the tube TN2 and the drain of the tube TN4 respectively, the gate of the tube TP2 is connected with the gate of the tube TN2, the drain of the tube TP1, the drain of the tube TN1 and the drain of the tube TN3 respectively, the source of the tube TP1 and the source of the tube TP2 are both connected with a power supply VDD, the gate of the tube TN3 and the gate of the tube TN4 are both connected with a word line, the source of the tube TN3 is connected with the input end of an inverter, the source of the tube TN4 is connected with a bit line BLB, and the source of the tube TN1 and the source of the tube TN2 are both connected with a common terminal VSS;
the tube TP1 and the tube TP2 are both PMOS transistors, and the tube TN1, the tube TN2, the tube TN3 and the tube TN4 are all NMOS transistors.
Optionally, the inverter comprises a tube TP3 and a tube TN5, a gate of the tube TP3 and a gate of the tube TN5 are both connected with a source of the tube TN3, a source of the tube TP3 is connected with a power supply VDD, a drain of the tube TP3 and a drain of the tube TN5 are both connected with a bit line BL, and a source of the tube TN5 is grounded; the tube TP3 is a PMOS transistor, and the tube TN5 is an NMOS transistor.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a charge sharing memory computing device, wherein a weight memory cell and a bit line are connected by adopting an inverter decoupling design, the problem of reading interference caused by the computing process is avoided, two groups of adjacent 4 memory cells are adopted to form a 8-bit weight value to be multiplied by a 2-bit word line input value, the computing result is accumulated by sharing the charges of the bit lines on the same side, and the output of a voltage value with high accumulated voltage in the two bit lines is compared, so that the quantifiable voltage range is enlarged.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a diagram of a charge-sharing memory computing device according to the present invention;
FIG. 2 is a schematic diagram of a word line input pulse sequence and a switching pulse sequence according to the present invention;
FIG. 3 is a schematic diagram of a storage unit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The invention aims to provide a charge sharing memory computing device, which enlarges the quantifiable voltage range.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
FIG. 1 is a schematic diagram of a charge-sharing memory computing device according to the present invention, and as shown in FIG. 1, a charge-sharing memory computing device includes a memory cell array 101, a bit line coupling module 102, and a first switch TBLAnd a second switch TBLB(ii) a The memory cell array 101 comprises two columns and four rows of memory cells, each memory cell comprises an inverter and an SRAM memory cell, the input end of each inverter is connected with the weight storage node Q of the corresponding SRAM memory cell, the output end of the inverter of the first column of memory cells is connected with a bit line BL, the output end of the inverter of the second column of memory cells is connected with a bit line BLB, the bit line BL of the first column of memory cells is connected with the bit line BL of the second column of memory cells through a first switch, the bit line BL of the second column of memory cells is connected with the bit line of the second column of memory cellsThe lines BLB are connected through a first switch, and the word lines of the SRAM memory cells in each row of memory cells are connected in a collinear way; the bit line coupling module 102 includes a coupling capacitor unit and a bit line comparison output unit, the coupling capacitor unit includes a first coupling capacitor, a second coupling capacitor, a third coupling capacitor and a fourth coupling capacitor, a first end of the first coupling capacitor is connected to the bit line BL of the first row of storage units, a second end of the first coupling capacitor is grounded, a first end of the second coupling capacitor is connected to the bit line BLB of the first row of storage units, a second end of the second coupling capacitor is grounded, a first end of the third coupling capacitor is connected to the bit line BL of the second row of storage units, a second end of the third coupling capacitor is grounded, a first end of the fourth coupling capacitor is connected to the bit line BLB of the second row of storage units, and a second end of the fourth coupling capacitor is grounded; when there is a coupling capacitor in the coupling capacitor unit for charging, the first switch TBLAnd a second switch TBLBAre all disconnected; when the coupling capacitor unit is not charged with the coupling capacitor, the first switch TBLAnd a second switch TBLBThe bit line comparison output unit is used for outputting the voltage value with high accumulated voltage in the bit line BL of the second column of the calculation units and the bit line BLB of the second column of the calculation units.
The bit line comparison output unit comprises a comparator and a selector, a bit line BL of the first column of the storage unit is connected with a first input end of the comparator, a bit line BLB of the first column of the storage unit is connected with a second input end of the comparator, a signal output by an output end of the comparator is used as an enabling signal of the selector, a bit line BL of the second column of the storage unit is connected with a first input end of the selector, a bit line BLB of the second column of the storage unit is connected with a second input end of the selector, and the output of the selector is the voltage accumulation output of the storage unit array 101.
The bit line comparison output unit further includes a third switch T1 and a fourth switch T2, and the third switch T1 and the fourth switch T2 are turned on after the comparator receives the enable signal.
As shown in fig. 2, the word lines input to the storage units in each row are all 2-bit values, the unit pulse width of the word line WL0 input to the storage unit in the first row is T0, the unit pulse width of the word line WL1 input to the storage unit in the second row is 2T0, the unit pulse width of the word line WL2 input to the storage unit in the third row is 3T0, and the unit pulse width of the word line WL3 input to the storage unit in the fourth row is 4T 0.
As shown in FIG. 3, the SRAM memory cell is a 6T-SRAM memory cell.
The 6T-SRAM memory cell comprises a tube TP1, a tube TP2, a tube TN1, a tube TN2, a tube TN3 and a tube TN 4; the gate of the tube TP1 is connected with the gate of the tube TN1, the drain of the tube TP2, the drain of the tube TN2 and the drain of the tube TN4 respectively, the gate of the tube TP2 is connected with the gate of the tube TN2, the drain of the tube TP1, the drain of the tube TN1 and the drain of the tube TN3 respectively, the source of the tube TP1 and the source of the tube TP2 are both connected with a power supply VDD, the gate of the tube TN3 and the gate of the tube TN4 are both connected with a word line, the source of the tube TN3 is connected with the input end of an inverter, the source of the tube TN4 is connected with a bit line BLB, and the source of the tube TN1 and the source of the tube TN2 are both connected with a common terminal VSS;
the tube TP1 and the tube TP2 are both PMOS transistors, and the tube TN1, the tube TN2, the tube TN3 and the tube TN4 are all NMOS transistors.
The inverter comprises a tube TP3 and a tube TN5, the grid electrode of the tube TP3 and the grid electrode of the tube TN5 are both connected with the source electrode of the tube TN3, the source electrode of the tube TP3 is connected with a power supply VDD, the drain electrode of the tube TP3 and the drain electrode of the tube TN5 are both connected with a bit line BL, and the source electrode of the tube TN5 is grounded; the tube TP3 is a PMOS transistor, and the tube TN5 is an NMOS transistor.
The inverter is used for decoupling the weight from the bit line when the transmission gate of the high-pulse word line is in a conducting stage and is charged and discharged with the bit line, so that the read interference phenomenon is prevented.
The operation of a charge sharing memory computing device according to the present invention is described with reference to fig. 1-3.
The word lines (WL 0, WL1, WL2, WL 3) are input with a 2-bit value, and by the pulse width modulation method, 00 corresponds to the unit pulse width T0, 01 corresponds to the 2-time unit pulse width 2T0, 10 corresponds to the 3-time unit pulse width 3T0, and 11 corresponds to the 4-time unit pulse width 4T 0. The 2-bit digital input value is converted into different pulse widths and then applied to the word line WL of the memory cell. According to the weight difference in each weight storage unit, the bit line capacitance CBL0And CBLB0And charging and discharging are carried out in the word line high pulse time period. On-line capacitance CBL0The voltage value after the charge accumulation is as follows:
capacitance C in flip-bit lineBLB0The voltage value obtained by adding charges is as follows:
wherein the content of the first and second substances,V pre representing the pre-charge voltage on the coupling capacitor,V pre =0.5V，T 0 high pulse, R, representing unit width of word lineBLAnd RBLBRespectively represent Bit Line resistances (R)BL) And flip bit line resistance (R)BLB)，W iThe weight values stored in the weight storage unit (i.e., the 6T-SRAM of fig. 3) in fig. 1 are shown.
As shown in the waveform of FIG. 2, during the period of high pulse of word line, the bit line capacitance is charging and discharging, and at this time the bit line coupling switch TBLAnd a reverse bit line coupling switch TBLBAre all in an off state. The circuit state means that two columns of memory cells are performing computations separately. When the word line high pulse ends, it means that the charging and discharging of the coupling capacitor ends. Subsequent conduction of the coupling switch TBLAnd a reverse bit line coupling switch TBLBThe bit line voltage with the weight of 4 bits higher is coupled with the bit line voltage value with the weight of 4 bits lower in voltage sharing mode. Then the bit line voltage comparator switch EN _ comparator is pulled high, and the bit line voltage after voltage equalization is subjected to delta VBLAnd inverted bit line voltage Δ VBLBA comparison is made. If the bit line voltage Δ VBL>ΔVBLBThe comparator outputs 1, and if not, 0.
The voltage comparator compares the bit line voltage DeltaVBLAnd Δ VBLBIs compared with the predetermined value, the comparison result is used as an enable signal Sign for controlling the selector, and the selector selects the bit line voltage Δ V after the selector switch T1 is turned onBLAnd Δ VBLBThe higher value is output, the output is expressed as Input Weight Product (IWP), and the output value is used for quantization by the subsequent analog-to-digital conversion module.
The technical effects achieved by the invention comprise:
the invention adopts a classic 6TSRAM unit and a decoupling inverter to form a basic storage unit, and because the weight value is connected with the grid of the transistor, the reading of the weight value avoids the problem of reading interference in the calculation process, and the robustness of the circuit is enhanced.
The array arrangement of 8-bit weights formed by arranging 4 weight storage units side by side in 2 adjacent rows enlarges the weight bit width of single calculation, and can realize 2-bit input by 8-bit weight in one calculation period.
The invention outputs higher voltage value for quantization by comparing the relative sizes of the bit line voltage sharing and the bit line voltage sharing, enlarges the quantifiable voltage range compared with a single-side quantization scheme, and is more beneficial to performing analog-to-digital conversion by adopting a looser quantization scheme in the follow-up process.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (7)
1. A charge sharing memory computing device is characterized by comprising a memory cell array, a bit line coupling module, a first switch and a second switch; the storage and calculation unit array comprises two columns of storage and calculation units with four rows, each storage and calculation unit comprises an inverter and an SRAM storage unit, the input end of each inverter is connected with a weight storage node corresponding to the SRAM storage unit, the output end of the inverter of the first column of storage and calculation unit is connected with a bit line BL, the output end of the inverter of the second column of storage and calculation unit is connected with a bit line BLB, the bit line BL of the first column of storage and calculation unit is connected with the bit line BL of the second column of storage and calculation unit through the first switch, the bit line BL of the second column of storage and the bit line BLB of the second column of storage and calculation unit are connected through the first switch, and the word lines of the SRAM storage units in each row of storage and calculation units are connected in a collinear mode; the bit line coupling module comprises a coupling capacitor unit and a bit line comparison output unit, the coupling capacitor unit comprises a first coupling capacitor, a second coupling capacitor, a third coupling capacitor and a fourth coupling capacitor, the first end of the first coupling capacitor is connected with the bit line BL of the first row of storage units, the second end of the first coupling capacitor is grounded, the first end of the second coupling capacitor is connected with the bit line BLB of the first row of storage units, the second end of the second coupling capacitor is grounded, the first end of the third coupling capacitor is connected with the bit line BL of the second row of storage units, the second end of the third coupling capacitor is grounded, the first end of the fourth coupling capacitor is connected with the bit line BLB of the second row of storage units, and the second end of the fourth coupling capacitor is grounded; when a coupling capacitor exists in the coupling capacitor unit for charging, the first switch and the second switch are both switched off; when no coupling capacitor exists in the coupling capacitor unit for charging, the first switch and the second switch are both conducted, and the bit line comparison output unit is used for outputting a voltage value with a high accumulated voltage in the bit line BL of the second row of storage units and the bit line BLB of the second row of storage units.
2. The apparatus according to claim 1, wherein the bit line comparison output unit comprises a comparator and a selector, the bit line BL of the first column of the calculation units is connected to the first input terminal of the comparator, the bit line BLB of the first column of the calculation units is connected to the second input terminal of the comparator, the output terminal of the comparator outputs a signal as an enable signal of the selector, the bit line BL of the second column of the calculation units is connected to the first input terminal of the selector, the bit line BLB of the second column of the calculation units is connected to the second input terminal of the selector, and the output of the selector is a voltage accumulation output of the calculation unit array.
3. The apparatus of claim 2, wherein the bit line comparison output unit further comprises a third switch and a fourth switch, and the third switch and the fourth switch are turned on when the comparator receives the enable signal.
4. The device of claim 1, wherein the word lines input to each row of storage units are all 2-bit values, the unit pulse width of the word line input to the first row of storage units is T0, the unit pulse width of the word line input to the second row of storage units is 2T0, the unit pulse width of the word line input to the third row of storage units is 3T0, and the unit pulse width of the word line input to the fourth row of storage units is 4T 0.
5. The charge-sharing memory computing device of claim 1, wherein the SRAM memory cell is a 6T-SRAM memory cell.
6. The charge-sharing memory computing device of claim 5, wherein the 6T-SRAM memory cell comprises a pipe TP1, a pipe TP2, a pipe TN1, a pipe TN2, a pipe TN3, and a pipe TN 4; the gate of the tube TP1 is connected with the gate of the tube TN1, the drain of the tube TP2, the drain of the tube TN2 and the drain of the tube TN4 respectively, the gate of the tube TP2 is connected with the gate of the tube TN2, the drain of the tube TP1, the drain of the tube TN1 and the drain of the tube TN3 respectively, the source of the tube TP1 and the source of the tube TP2 are both connected with a power supply VDD, the gate of the tube TN3 and the gate of the tube TN4 are both connected with a word line, the source of the tube TN3 is connected with the input end of an inverter, the source of the tube TN4 is connected with a bit line BLB, and the source of the tube TN1 and the source of the tube TN2 are both connected with a common terminal VSS;
the tube TP1 and the tube TP2 are both PMOS transistors, and the tube TN1, the tube TN2, the tube TN3 and the tube TN4 are all NMOS transistors.
7. The charge-sharing memory computing device of claim 6, wherein the inverter comprises a transistor TP3 and a transistor TN5, a gate of the transistor TP3 and a gate of the transistor TN5 are both connected to a source of the transistor TN3, a source of the transistor TP3 is connected to a power supply VDD, a drain of the transistor TP3 and a drain of the transistor TN5 are both connected to a bit line BL, and a source of the transistor TN5 is grounded; the tube TP3 is a PMOS transistor, and the tube TN5 is an NMOS transistor.
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