CN113936717B - Storage and calculation integrated circuit for multiplexing weight - Google Patents
Storage and calculation integrated circuit for multiplexing weight Download PDFInfo
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- CN113936717B CN113936717B CN202111535413.6A CN202111535413A CN113936717B CN 113936717 B CN113936717 B CN 113936717B CN 202111535413 A CN202111535413 A CN 202111535413A CN 113936717 B CN113936717 B CN 113936717B
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- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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Abstract
The present invention relates to a multiplexing weight storage and calculation integrated circuit, including: an SRAM computational cell array; each SRAM calculation unit comprises a storage unit, a tube T1, a tube T2, a tube T3 and a tube T4, each calculation submodule comprises a tube TN1, a tube TN2, a tube TP1, a tube TP2, a coupling capacitor C1 and a coupling capacitor C2, a grid of the tube T1 and a grid of the tube T3 are both connected with a first weight storage point of the storage unit, and a grid of the tube T2 and a grid of the tube T4 are both connected with a second weight storage point of the storage unit; the coupling capacitor C1 is used for realizing the exclusive OR calculation of the input of the reverse input end and the weight value corresponding to the first weight storage point, and the coupling capacitor C2 is used for realizing the exclusive OR calculation of the input end and the weight value corresponding to the first weight storage point. The invention improves the utilization rate of the weight of the storage unit and reduces the read-write interference of the weight.
Description
Technical Field
The invention relates to the field of memory computing, in particular to a multiplexing weight memory and computation integrated circuit.
Background
Edge computing plays a crucial role in artificial intelligence ecosystems and AI-based internet of things (AIoT) devices, i.e., providing better real-time user experience and privacy. Energy efficiency is a priority to promote the development of intelligent edge devices; however, the traditional von neumann architecture consumes a lot of energy in data movement between the off-chip memory and the processing unit, which is a bottleneck to be solved urgently in edge computing.
In-memory Computation (CIM) eliminates the boundary between memory and processing units by implementing computation operations in memory macros, so in-memory computation is a promising approach to improve AI edge computation and AIoT device energy efficiency.
CIM may be implemented by volatile memory (e.g., SRAM-CIM) or non-volatile memory (e.g., ReRAM-CIM). But low endurance and high write energy limit the range of ReRAM-CIM to systems with sufficient memory capacity to store all the weight data needed by the target application. In contrast, SRAM-CIM has faster write speed and lower write energy, while having higher (essentially infinite) endurance, which makes it suitable for medium and small capacity systems and configurable to a wide range of neural networks. In addition, SRAM-CIM allows the use of state-of-the-art logic technology to reduce latency and improve energy efficiency.
However, when performing an operation, the conventional on-chip SRAM requires 6 transistors to store a one-bit weight value, which consumes more hardware resources, and the utilization rate of the weight is not high due to the conventional calculation method of multiplying a single input by a single weight. In the case of high hardware resource consumption and low utilization, both power consumption and area will make SRAM-based memory computations less dominant.
Meanwhile, the conventional calculation method is to accumulate the calculation result (generally expressed as voltage) on the read bit line, which easily results in two consequences, one is: if the bit line voltage swing is too large, the weight stored in the 6t sram is rewritten, i.e. so-called read-write interference, and secondly, the voltage margin of the read-write result on the read bit line is small, which is not favorable for the analog-digital converter to perform digital conversion.
Disclosure of Invention
The invention aims to provide a storage and calculation integrated circuit for multiplexing weights, which improves the utilization rate of the weights of storage units and reduces the read-write interference of the weights.
In order to achieve the purpose, the invention provides the following scheme:
a storage integrated circuit for multiplexing weights, comprising: the device comprises an SRAM (static random access memory) calculation unit array, a pre-charging module, a row selection module and an output module;
the SRAM calculation unit array comprises 256 columns and 64 rows of SRAM calculation units and a calculation submodule connected with each row of SRAM calculation units;
each SRAM calculation unit includes a memory cell, a transistor T1, a transistor T2, a transistor T3, and a transistor T4, the calculation submodule includes a transistor TN1, a transistor TN2, a transistor TP1, a transistor TP2, a coupling capacitor C1, and a coupling capacitor C2, a gate of the transistor T1 and a gate of the transistor T3 are both connected to a first weight storage point of the memory cell, a gate of the transistor T2 and a gate of the transistor T4 are both connected to a second weight storage point of the memory cell, a first pole of the transistor T1 and a first pole of the transistor T2 are both connected to an inverted input terminal, a second pole of the transistor T1 and a second pole of the transistor T2 are both connected to one end of a read bit line RBL _ U, the other end of the read bit line RBL _ U is connected to one end of the coupling capacitor C1, the other end of the coupling capacitor C1 is connected to the first pole of the transistor T1 and the first pole of the transistor TP 8, the first pole of the transistor TP1, the output terminal of the transistor TN 4 and the output module 4, the second pole of the tube T3 and the second pole of the tube T4 are both connected to one end of a read bit line RBL _ D, the other end of the read bit line RBL _ D is connected to one end of the coupling capacitor C2, the other end of the coupling capacitor C2 is connected to the first pole of the tube TN2 and the first pole of the tube TP2, the second pole of the tube TP2 is connected to the output module, the second pole of the tube TN1 and the second pole of the tube TN2 are both grounded, and the gates of the tube TP1 and the tube TP2 are both connected to the row selection module; the second pole of the tube T1 and the second pole of the tube T2 of each row of the SRAM calculation units are connected in line, and the second pole of the tube T3 and the second pole of the tube T4 of each row of the SRAM calculation units are connected in line;
the row selection module is used for selecting a row in the SRAM calculation unit array for calculation; the pre-charging module is used for charging a coupling capacitor C1 and a coupling capacitor C2 to a set voltage before the SRAM calculation unit array calculation;
when the weight value of the first weight storage point is 1, the weight value of the second weight storage point is 0, and when the weight value of the first weight storage point is 0, the weight value of the second weight storage point is 1; when the input of the reverse input end is 0, the input of the input end is 1; when the input of the reverse input end is 1, the input of the input end is 0; when the set row in the SRAM computing unit array is selected by the row selection module, the coupling capacitor C1 is used to implement exclusive nor calculation between the reverse input terminal and the weight value corresponding to the first weight storage point, and the coupling capacitor C2 is used to implement exclusive nor calculation between the input terminal and the weight value corresponding to the first weight storage point.
Optionally, the device further comprises an input module, wherein the input module is used for inputting voltages to the inverse input terminal and the input terminal respectively.
Optionally, the SRAM cell further comprises a timing control module, the timing control module is respectively connected to the SRAM cell array, the pre-charge module, the row selection module, the input module, and the output module, and the timing control module is configured to send a timing control signal.
Optionally, the voltage regulator further comprises a reference voltage module, the reference voltage module is connected to the output module, and the reference voltage module is configured to provide a reference voltage for digital-to-analog conversion of the voltage output by the second pole of the tube TP1 and the voltage output by the second pole of the tube TP2 by the output module.
Optionally, the tube T1, the tube T4, the tube TP1, and the tube TP2 are all PMOS tubes.
Optionally, the tube T2, the tube T3, the tube TN1, and the tube TN2 are all NMOS tubes.
Optionally, the storage unit is a 6-pipe SRAM.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
according to the invention, the grid of the tube T1 and the grid of the tube T3 are both connected with the first weight storage point of the storage unit, the grid of the tube T2 and the grid of the tube T4 are both connected with the second weight storage point of the storage unit, the weights stored in the first weight storage point and the second weight storage point are repeatedly utilized, the utilization rate of the weight value of the storage unit is improved, the first weight storage point and the second weight storage point are connected with the grids of the MOS tubes (the tube T1, the tube T2, the tube T3 and the tube T4), the read-write interference of the weight is avoided when the whole row is calculated and the voltage swing of the read bit line is too large, and as the two MOS tubes carry out charging and discharging on the coupling capacitor, the effect is doubled compared with the charging and discharging efficiency of a single MOS tube, the effect is realized, the voltage swing of the read bit line is increased, and the output module has enough voltage margin.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a multiplexing weight storage and computation integrated circuit structure according to the present invention;
FIG. 2 is a schematic diagram of the structure of an SRAM calculation unit and a calculation submodule according to the present invention;
FIG. 3 is a diagram illustrating the operation effect of the circuit when +1 and weight +1 are inputted;
FIG. 4 is a diagram illustrating the operation of the circuit according to the present invention with an input of-1 and a weight of + 1;
FIG. 5 is a diagram illustrating the operation of the circuit according to the present invention with input-1 and weight-1;
FIG. 6 is a diagram illustrating the operation of the circuit when +1 and weight-1 are inputted;
FIG. 7 is a diagram illustrating the operation effect of the circuit when the accumulated voltage on the coupling capacitor is outputted.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a storage and calculation integrated circuit for multiplexing weights, which improves the utilization rate of the weights of storage units and reduces the read-write interference of the weights.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic diagram of a multiplexing weight storage and calculation integrated circuit according to the present invention, and as shown in fig. 1, the multiplexing weight storage and calculation integrated circuit includes: the SRAM calculation unit comprises an SRAM calculation unit array 103, a pre-charging module 102, a row selection module 105 and an output module 104;
the SRAM calculation unit array 103 is an SRAM calculation unit array 103 with 256 columns × 64 rows, and the SRAM calculation unit array 103 includes SRAM calculation units with 256 columns × 64 rows and a calculation submodule connected to each row of the SRAM calculation units.
The SRAM calculation cell array 103 includes 64 rows of sub-arrays, each of which includes 256 columns of SRAM calculation cells and a calculation sub-module connected to the SRAM calculation cells.
As shown in fig. 2, each SRAM computing unit includes a memory cell, a pipe T1, a pipe T2, a pipe T3 and a pipe T4, the computing submodule includes a pipe TN1, a pipe TN2, a pipe TP1, a pipe TP2, a coupling capacitor C1 and a coupling capacitor C2, the gates of the pipe T1 and the pipe T3 are connected to the first weight storage point Q of the memory cell, the gates of the pipe T2 and the pipe T4 are connected to the second weight storage point Q of the memory cell, the first poles of the pipe T1 and the pipe T QB 2 are connected to the inverting input (inverting input in fig. 2), the second pole of the pipe T1 and the second pole of the pipe T2 are connected to one end of a Read Bit Line RBL _ U, the other end of the Read Bit Line RBL _ U (Read Bit Line _ Up, upper Read Bit Line) is connected to one end of the coupling capacitor C1, the other end of the coupling capacitor C1 is connected to the first pole TP 58 of the pipe TN 3872 and the output module (output module 104), a first pole of the tube T3 and a first pole of the tube T4 are both connected to an input terminal (input in fig. 2), a second pole of the tube T3 and a second pole of the tube T4 are both connected to one end of a Read Bit Line RBL _ D (Read Bit Line _ Down, below), the other end of the Read Bit Line RBL _ D is connected to one end of a coupling capacitor C2, the other end of the coupling capacitor C2 is connected to the first pole of the tube TN2 and the first pole of the tube TP2, the second pole of the tube TP2 is connected to the output module 104 (digital-analog converter in the output module 104), the second pole of the tube TN1 and the second pole of the tube TN2 are both grounded, the gate of the tube TP1 and the gate of the tube TP2 are both connected to the row selection module 105, and the gate of the tube TP1 and the gate of the tube TP2 are both connected to the row selection signal of the row selection module 105 (row selection in fig. 2); the second pole of the tube T1 and the second pole of the tube T2 of each row of SRAM calculation cells are connected in line, and the second pole of the tube T3 and the second pole of the tube T4 of each row of SRAM calculation cells are connected in line. The digital-to-analog conversion in fig. 2-7 represents a digital-to-analog converter. Wherein the tube T1, the tube T2, the read bit line above, the coupling capacitor C1 and the grounding tube TN1 (tube TN 1) form an exclusive OR logic calculation circuit above; similarly, the tube T3, the tube T4, the lower read bit line, the coupling capacitor C2 and the grounding tube TN2 (tube TN 2) form the lower exclusive OR logic calculation circuit.
The integrated circuit for multiplexing weight calculation further comprises an input module 106, wherein the input module 106 is used for inputting voltages to an inverse input end and an input end respectively.
The integrated circuit for calculating the multiplexing weight further comprises a timing control module which is respectively connected with the SRAM calculation unit array 103, the pre-charging module 102, the row selection module 105, the input module 106 and the output module 104 and used for sending a timing control signal.
The integrated circuit for calculating the multiplexing weight further comprises a reference voltage module 101, the reference voltage module 101 is connected with the output module 104, and the reference voltage module 101 is used for providing reference voltages for the output module 104 to perform digital-to-analog conversion on the voltage output by the second pole of the tube TP1 and the voltage output by the second pole of the tube TP 2.
Tube T1, tube T4, tube TP1, and tube TP2 are all PMOS tubes. The tube T2, the tube T3, the tube TN1, and the tube TN2 are all NMOS tubes.
The storage unit is 6-tube SRAM.
The row selection module 105 is used for selecting a row in the SRAM calculation unit array 103 for calculation; the pre-charge module 102 is used to charge the coupling capacitor C1 and the coupling capacitor C2 to a set voltage before the SRAM cell array 103 is counted.
When the weight value of the first weight storage point Q is 1, the weight value of the second weight storage point QB is 0, the weight represents +1, and when the weight value of the first weight storage point Q is 0, the weight value of the second weight storage point QB is 1, and the weight represents-1; when the input at the inverted input terminal is 0, the input 1 (power supply voltage VDD) at the input terminal represents input + 1; when the input at the inverse input terminal is 1, the input at the input terminal is 0, which represents the input-1.
Wherein, the calculation logic circuit is shown in table 1:
TABLE 1 computational logic circuit
When the row selection module 105 selects a set row in the SRAM cell array 103, the coupling capacitor C1 is used to implement the exclusive nor calculation between the input of the reverse input terminal and the weight value corresponding to the first weight storage point Q, and the coupling capacitor C2 is used to implement the exclusive nor calculation between the input of the input terminal and the weight value corresponding to the first weight storage point Q.
Before the exclusive-nor logic calculation starts, the coupling capacitor C1 and the coupling capacitor C2 are precharged to 0.5VDD through RBL _ U and RBL _ D by the precharge module 102.
The following are the following calculations performed in sequence for four cases, where the black lines in fig. 3-7 represent the conducting segments and the grey lines represent the non-conducting segments:
(1) input = +1, weight = +1, input ☉ weight = +1, the circuit effect is as shown in fig. 3:
since the input is +1, (i.e., the input is VDD), the weight is +1, (i.e., Q =1, QB =0), so that the tube T3 and the tube T4 are in the on state, and the tube T1 and the tube T2 are in the off state, the high level of the input can charge the coupling capacitor C2 through RBL _ D, that is, the exclusive nor calculation of the input ☉ weight = +1 is completed.
(2) Input = -1, weight = +1, input ☉ weight =0, the circuit effect is as shown in fig. 4:
since the input is-1, (i.e., the input is 0), and the weight is +1, (i.e., Q =1, QB =0), so that the tube T3 and the tube T4 are in the on state, and the tube T1 and the tube T2 are in the off state, the low level of the input can discharge the coupling capacitor C2 through RBL _ D, i.e., the exclusive nor calculation of the input ☉ weight =0 is completed.
(3) Input = -1, weight = -1, input ☉ weight = +1, circuit effect is as shown in fig. 5:
since the input is-1, (i.e., the inverse input is VDD), and the weight is-1, (i.e., Q =0, QB =1), such that the transistor T1 and the transistor T2 are in the on state, and the transistor T3 and the transistor T4 are in the off state, the high level of the inverse input can charge the coupling capacitor C1 through RBL _ U, i.e., the exclusive nor calculation of the input ☉ weight = +1 is completed.
(4) Input = +1, weight = -1, input ☉ weight =0, the circuit effect is as shown in fig. 6:
since the input is +1, (i.e., the inverse input is 0), and the weight is-1, (i.e., Q =0, QB =1), so that the transistor T1 and the transistor T2 are in the on state, and the transistor T3 and the transistor T4 are in the off state, the low level of the inverse input can discharge the coupling capacitor C1 through RBL _ U, i.e., the exclusive nor calculation of the input ☉ weight =0 is completed.
The above four phases complete the process of voltage accumulation for 256 1-bit inputs in a row with 1-bit weights in the same or logical way. As shown in fig. 7, after the up-down coupling capacitors (C2 and C2) are charged and discharged, the current row selection signal changes from high level to low level, so that the tubes TN1 and TN2 are turned off, and the tubes TP1 and TP2 are turned on to the analog-to-digital converter. And (4) carrying out digital processing on the voltage accumulated on the two coupling capacitors by using an analog-to-digital converter.
The invention has the following technical effects:
the memory calculation unit is a basic unit based on a Static Random Access Memory (SRAM), and has the defect of low integration density compared with a DRAM and a ReRAM, but the memory calculation unit adopts a weight multiplexing design, namely the upper end and the lower end can use the same memory unit for calculation, so that the input is doubled, and the utilization rate of the weight is increased.
The logic calculation circuit of the invention can not only calculate the upper end and the lower end, but also has two MOS tube grids connected to the weighted value when each end is charged and discharged, thus having two advantages: firstly, the weight value is connected to the grid, and the read-write interference of the weight value is avoided when the whole line is calculated and the voltage swing of the read bit line is overlarge; and secondly, because the two MOS tubes charge and discharge the coupling capacitor, compared with the charge and discharge efficiency of a single MOS tube, the charge and discharge efficiency has a double effect, the effect increases the voltage swing of the read bit line, and the analog-to-digital conversion module has enough voltage margin.
The macro unit is a 64-row sub-array, if in practical application, partial sub-arrays can be closed or the same array can be added through configuration, so that the application flexibility is enhanced.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principle and the embodiment of the present invention are explained by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (7)
1. A circuit for integrating the computation of multiplexing weights, comprising: the device comprises an SRAM (static random access memory) calculation unit array, a pre-charging module, a row selection module and an output module;
the SRAM calculation unit array comprises 256 columns and 64 rows of SRAM calculation units and a calculation submodule connected with each row of SRAM calculation units;
each SRAM calculation unit includes a memory cell, a transistor T1, a transistor T2, a transistor T3, and a transistor T4, the calculation submodule includes a transistor TN1, a transistor TN2, a transistor TP1, a transistor TP2, a coupling capacitor C1, and a coupling capacitor C2, a gate of the transistor T1 and a gate of the transistor T3 are both connected to a first weight storage point of the memory cell, a gate of the transistor T2 and a gate of the transistor T4 are both connected to a second weight storage point of the memory cell, a first pole of the transistor T1 and a first pole of the transistor T2 are both connected to an inverted input terminal, a second pole of the transistor T1 and a second pole of the transistor T2 are both connected to one end of a read bit line RBL _ U, the other end of the read bit line RBL _ U is connected to one end of the coupling capacitor C1, the other end of the coupling capacitor C1 is connected to the first pole of the transistor T1 and the first pole of the transistor TP 8, the first pole of the transistor TP1, the output terminal of the transistor TN 4 and the output module 4, the second pole of the tube T3 and the second pole of the tube T4 are both connected to one end of a read bit line RBL _ D, the other end of the read bit line RBL _ D is connected to one end of the coupling capacitor C2, the other end of the coupling capacitor C2 is connected to the first pole of the tube TN2 and the first pole of the tube TP2, the second pole of the tube TP2 is connected to the output module, the second pole of the tube TN1 and the second pole of the tube TN2 are both grounded, and the gates of the tube TP1 and the tube TP2 are both connected to the row selection module; the second pole of the tube T1 and the second pole of the tube T2 of each row of the SRAM calculation units are connected in line, and the second pole of the tube T3 and the second pole of the tube T4 of each row of the SRAM calculation units are connected in line;
the row selection module is used for selecting one row in the SRAM calculation unit array for calculation; the pre-charging module is used for charging a coupling capacitor C1 and a coupling capacitor C2 to a set voltage before the SRAM calculation unit array calculation;
when the weight value of the first weight storage point is 1, the weight value of the second weight storage point is 0, and when the weight value of the first weight storage point is 0, the weight value of the second weight storage point is 1; when the input of the reverse input end is 0, the input of the input end is 1; when the input of the reverse input end is 1, the input of the input end is 0; when the set row in the SRAM computing unit array is selected by the row selection module, the coupling capacitor C1 is used to implement exclusive nor calculation between the reverse input terminal and the weight value corresponding to the first weight storage point, and the coupling capacitor C2 is used to implement exclusive nor calculation between the input terminal and the weight value corresponding to the first weight storage point.
2. The integrated circuit for multiplexing weights of claim 1, further comprising input modules for inputting voltages to the inverting input and the input, respectively.
3. The integrated circuit for multiplexing weight storage according to claim 1, further comprising a timing control module, wherein the timing control module is respectively connected to the SRAM calculation cell array, the precharge module, the row selection module, the input module, and the output module, and the timing control module is configured to send a timing control signal.
4. The integrated circuit for multiplexing weight of claim 1, further comprising a reference voltage module, wherein the reference voltage module is connected to the output module, and the reference voltage module is configured to provide a reference voltage for the output module to perform digital-to-analog conversion on the voltage outputted from the second pole of the tube TP1 and the voltage outputted from the second pole of the tube TP 2.
5. The integrated circuit for multiplexing weight of claim 1, wherein the tube T1, the tube T4, the tube TP1 and the tube TP2 are all PMOS tubes.
6. The integrated circuit for multiplexing weights of claim 1, wherein the tube T2, the tube T3, the tube TN1, and the tube TN2 are all NMOS tubes.
7. The integrated circuit for storing multiplex weights of claim 1 wherein said storage unit is a 6-pipe SRAM.
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| EP3807756A4 (en) * | 2018-06-18 | 2022-03-30 | The Trustees of Princeton University | Configurable in-memory computing engine, platform, bit cells and layouts therefore |
| KR20220157377A (en) * | 2020-02-05 | 2022-11-29 | 더 트러스티즈 오브 프린스턴 유니버시티 | Scalable Array Architecture for In-Memory Computing |
| CN112133348B (en) * | 2020-11-26 | 2021-02-12 | 中科院微电子研究所南京智能技术研究院 | Storage unit, storage array and memory computing device based on 6T unit |
| CN112992223B (en) * | 2021-05-20 | 2021-09-14 | 中科院微电子研究所南京智能技术研究院 | Memory computing unit, memory computing array and memory computing device |
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