CN115701568A

CN115701568A - Low dropout linear voltage stabilizing circuit

Info

Publication number: CN115701568A
Application number: CN202110888805.4A
Authority: CN
Inventors: 袁巍; 王超; 王磊; 葛绘林
Original assignee: Hikstor Technology Co Ltd
Current assignee: Hikstor Technology Co Ltd
Priority date: 2021-08-02
Filing date: 2021-08-02
Publication date: 2023-02-10

Abstract

The invention provides a low dropout linear voltage stabilizing circuit, comprising: the input end of the first current mirror is electrically connected with a bias current source; the input end of the second current mirror is electrically connected with the output end of the first current mirror; the differential circuit comprises a pair of input pair transistors, wherein the source electrodes of the input pair transistors are electrically connected with the output end of the second current mirror; one MOS tube grid of the input pair tube is electrically connected with a reference voltage; the in-phase input end and the reverse-phase input end of the cascode amplifying circuit are respectively electrically connected with the drains of the input pair transistors; and the input end of the output circuit is electrically connected with the output end of the cascode amplifying circuit, the output end of the output circuit is fed back to the grid electrode of the other MOS tube of the input geminate transistor after voltage division through a resistor, and the output end of the output circuit is electrically connected with the in-phase input end of the cascode amplifying circuit. The low dropout linear voltage stabilizing circuit provided by the invention has good load response and temperature drift characteristics.

Description

Low dropout linear voltage stabilizing circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a low dropout linear voltage stabilizing circuit.

Background

MRAM (magnetic Random Access Memory) is a nonvolatile (Non-Volatile) magnetic Random Access Memory. It possesses the high-speed read-write capability of static random access memory SRAM, and the high integration of dynamic random access memory DRAM, and can be written repeatedly, essentially indefinitely. The MRAM has low power consumption, high-speed read-write and other indexes, and from the design point of view, the MRAM has high requirements on the indexes of the read-write power supply, such as wide temperature range, low temperature drift, low power consumption, small area and the like.

In the prior art, the low dropout regulator used in the MRAM read operation generally has higher power consumption and larger temperature drift, which causes the MRAM data current sampling window to be too small, and affects the read performance index.

Disclosure of Invention

The low dropout linear voltage stabilizing circuit provided by the invention has good load response and temperature drift characteristics.

The invention provides a low dropout linear voltage stabilizing circuit, comprising:

the input end of the first current mirror is electrically connected with the bias current source and is used for amplifying the current input by the bias current source into first bias current according to a preset first proportion;

the input end of the second current mirror is electrically connected with the output end of the first current mirror, and the second current mirror is used for amplifying the first bias current into second bias current according to a preset second proportion;

the differential circuit comprises a pair of input pair transistors, wherein the source electrodes of the input pair transistors are electrically connected with the output end of the second current mirror; the grid electrode of one MOS tube of the input pair tubes is electrically connected with a reference voltage;

the in-phase input end and the reverse-phase input end of the cascode amplifying circuit are respectively and electrically connected with the drain electrodes of the input geminate transistors;

and the input end of the output circuit is electrically connected with the output end of the cascode amplifying circuit, the output end of the output circuit is fed back to the grid electrode of the other MOS tube of the input geminate transistor after voltage division through a resistor, and the output end of the output circuit is electrically connected with the in-phase input end of the cascode amplifying circuit.

Optionally, the first current mirror comprises:

the first end of the first resistor is electrically connected with a current source;

the drain end of the first NMOS tube is electrically connected with the second end of the first resistor;

the drain end of the second NMOS tube is electrically connected with the source end of the first NMOS tube, and the source end of the second NMOS tube is grounded;

a source end of the third NMOS tube is grounded, and the third NMOS tube and the second NMOS tube share a gate and are electrically connected with a second end of the first resistor;

and the source end of the fourth NMOS tube is electrically connected with the drain end of the third NMOS tube, the fourth NMOS tube is commonly gated with the first NMOS tube and is electrically connected with the first end of the first resistor, and the drain ends of the fourth NMOS tube are used for outputting a first bias current.

Optionally, the second current mirror comprises:

a first end of the second resistor is electrically connected with the drain ends of the four NMOS tubes;

the drain end of the first PMOS tube is electrically connected with the second end of the second resistor;

the drain end of the second PMOS tube is electrically connected with the source end of the first PMOS tube, and the source end of the second PMOS tube is electrically connected with a voltage source;

a source end of the third PMOS tube is electrically connected with a voltage source, and the third PMOS tube and the second PMOS tube share a gate and are electrically connected with a second end of the second resistor;

and the source end of the fourth PMOS tube is electrically connected with the drain end of the third PMOS tube, the fourth PMOS tube is commonly gated with the first PMOS tube and is electrically connected with the first end of the second resistor, and the drain end of the fourth PMOS tube is used for outputting a second bias current.

Optionally, the differential circuit comprises a pair of input pair transistors, the input pair transistors comprising:

a source end of the fifth PMOS tube is electrically connected with a drain end of the fourth PMOS tube, a drain end of the fifth PMOS tube is electrically connected with a non-inverting input end of the cascode amplifying circuit, and a grid electrode of the fifth PMOS tube is electrically connected with a reference voltage source;

and a source end of the sixth PMOS tube is electrically connected with a drain end of the fourth PMOS tube, the drain end of the sixth PMOS tube is electrically connected with an inverting input end of the cascode amplifying circuit, and a grid electrode of the sixth PMOS tube is used for inputting a signal fed back by the output circuit.

Optionally, the cascode circuit includes:

the source ends of the seventh PMOS tube and the eighth PMOS tube are both electrically connected with a voltage source;

a ninth PMOS transistor and a tenth PMOS transistor which are arranged in a common gate, source ends of the ninth PMOS transistor and the tenth PMOS transistor being electrically connected to drain ends of the seventh PMOS transistor and the eighth PMOS transistor, respectively; the drain end of the ninth PMOS tube is electrically connected with the source ends of the seventh PMOS tube and the eighth PMOS tube; grid ends of the ninth PMOS tube and the tenth PMOS tube are electrically connected with grids of the first PMOS tube and the fourth PMOS tube; the drain end of the tenth PMOS tube is used as the output end of the amplifying circuit;

the drain ends of the fifth NMOS tube and the sixth NMOS tube are respectively and electrically connected with the drain ends of the ninth PMOS tube and the tenth PMOS tube; grid ends of the fifth NMOS tube and the sixth NMOS tube are electrically connected with grids of the first NMOS tube and the fourth NMOS tube; the source end of the fifth NMOS tube is used as a positive phase input end of the amplifying circuit, and the source end of the sixth NMOS tube is used as an inverted phase input end of the amplifying circuit;

and the drain ends of the seventh NMOS tube and the eighth NMOS tube are respectively electrically connected with the source ends of the fifth NMOS tube and the sixth NMOS tube, the source ends of the seventh NMOS tube and the eighth NMOS tube are grounded, and the grid ends of the seventh NMOS tube and the eighth NMOS tube are electrically connected with the grids of the second NMOS tube and the third NMOS tube.

Optionally, the output circuit comprises:

the grid electrode of the driving tube is electrically connected with the output end of the cascode amplifying circuit; one of the source or the drain is electrically connected with the voltage source;

the first end of the adjustable resistor is electrically connected with the other one of the source electrode or the drain electrode of the driving tube; the first end of the adjustable resistor is electrically connected with the source end of the fifth NMOS tube through a first capacitor C1; the first end of the adjustable resistor is used as an output end and is grounded through a second capacitor;

a first end of the third resistor is electrically connected with a second end of the adjustable resistor, and the second end of the third resistor is grounded; and the first end of the third resistor is electrically connected with the grid electrode of the sixth PMOS tube.

Optionally, the size ratio of the second NMOS transistor, the third NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor is 1.

Optionally, the size ratio of the second PMOS transistor to the third PMOS transistor is 1.

Optionally, the size ratio of the seventh PMOS transistor to the eighth PMOS transistor is 1.

Optionally, the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor adopt a width-to-length ratio inverse size, and the first PMOS transistor, the fourth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor adopt a width-to-length ratio inverse size.

In the technical scheme provided by the invention, the first current mirror and the second current mirror are combined to avoid current imbalance in the mirror image process, and the load response and the temperature drift characteristic can be effectively improved and the power supply rejection ratio can be improved at the same time by amplifying the differential current through the cascode amplifying circuit. The technical scheme provided by the invention can be applied to the MRAM reading operation power supply, can be compatible with various process platform designs, and has high reusability; the requirements on indexes such as low power consumption, wide temperature range and low temperature drift are met. The design can reach 6uA of quiescent current, the output Temperature is 3-5 mV within the range of-40 ℃ to +125 ℃, the area is reduced by 12 percent compared with the original design, and the high performance index that VPP is less than 35mV under the whole PVT (Process, voltage) during 5ns reading operation is met.

Drawings

FIG. 1 is a diagram illustrating a low dropout linear voltage regulator circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a low dropout linear voltage regulator circuit according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

An embodiment of the present invention provides a low dropout linear voltage regulator circuit, as shown in fig. 1-2, including:

the input end of the second current mirror is electrically connected with the output end of the first current mirror and is used for amplifying the first bias current into second bias current according to a preset second proportion;

In the technical scheme provided by the embodiment, the first current mirror and the second current mirror are used in a combined mode, current imbalance in the mirror image process is avoided, the load response and the temperature drift characteristic can be effectively improved through amplification of the cascode amplifying circuit on differential current, and meanwhile, the power supply rejection ratio can also be improved. The technical scheme provided by the embodiment can be applied to the MRAM reading operation power supply, can be compatible with various process platform designs, and has high reusability; the requirements on indexes such as low power consumption, wide temperature range and low temperature drift are met. The design can reach the quiescent current of 6uA, the output Temperature is 3-5 mV within the range of-40 ℃ to +125 ℃, the area is reduced by 12 percent compared with the original design, and the high performance index of VPP <35mV under the full PVT (Process, voltage) during 5ns reading operation is met.

As an alternative embodiment, continuing with fig. 1-2, the first current mirror comprises:

the first resistor R1 is electrically connected with a current source at a first end;

a drain terminal of the first NMOS transistor is electrically connected with a second terminal of the first resistor N5;

a drain terminal of the second NMOS tube is electrically connected with a source terminal of the first NMOS tube, and a source terminal of the second NMOS tube is grounded;

a third NMOS tube N2, wherein the source end of the third NMOS tube is grounded, and the third NMOS tube and the second NMOS tube share a gate and are electrically connected with the second end of the first resistor;

and the source end of the fourth NMOS tube is electrically connected with the drain end of the third NMOS tube, the fourth NMOS tube is commonly gated with the first NMOS tube and is electrically connected with the first end of the first resistor, and the drain end of the fourth NMOS tube is used for outputting a first bias current.

In this embodiment, the first resistor R1, the second NMOS transistor N1, the third NMOS transistor N2, the first NMOS transistor N5, and the fourth NMOS transistor N6 form an N-type self-biased low-voltage cascade cascode current mirror, so that the second NMOS transistor N1 and the third NMOS transistor N2 are kept in a saturation region during normal operation, and accurate mirror bias current is ensured.

As an alternative embodiment, continuing with fig. 1-2, the second current mirror comprises:

a first end of the second resistor R4 is electrically connected with the drain ends of the four NMOS tubes;

the drain end of the first PMOS tube P7 is electrically connected with the second end of the second resistor;

a drain end of the second PMOS tube is electrically connected with a source end of the first PMOS tube, and a source end of the second PMOS tube is electrically connected with a voltage source;

a source end of the third PMOS transistor is electrically connected with a voltage source, and the third PMOS transistor and the second PMOS transistor share a gate and are electrically connected with a second end of the second resistor;

In this embodiment, the second resistor R4, the second PMOS transistor P3, the third PMOS transistor P4, the first PMOS transistor P7 and the fourth PMOS transistor P8 form a P-type self-biased low-voltage cascade cascode current mirror, so that the second PMOS transistor P3 and the third PMOS transistor P4 are kept in a saturation region during normal operation, and accurate mirror bias current is ensured.

As an alternative embodiment, and as further shown in fig. 1-2, the differential circuit includes a pair of input pair transistors, the input pair transistors including:

a source end of the fifth PMOS tube P1 is electrically connected with a drain end of the fourth PMOS tube, a drain end of the fifth PMOS tube is electrically connected with a non-inverting input end of the cascode amplifying circuit, and a grid electrode of the fifth PMOS tube is electrically connected with a reference voltage source;

and a source end of the sixth PMOS tube P2 is electrically connected with a drain end of the fourth PMOS tube, a drain end of the sixth PMOS tube is electrically connected with an inverting input end of the cascode amplifying circuit, and a grid electrode of the sixth PMOS tube is used for inputting a signal fed back by the output circuit.

As an alternative embodiment, continuing with fig. 1-2, the cascode circuit includes:

a seventh PMOS tube P5 and an eighth PMOS tube P6 which are arranged in a common grid mode, wherein source ends of the seventh PMOS tube and the eighth PMOS tube are both electrically connected with a voltage source;

a ninth PMOS transistor P9 and a tenth PMOS transistor P10, which are provided with a common gate, and source ends of the ninth PMOS transistor and the tenth PMOS transistor are electrically connected to drain ends of the seventh PMOS transistor and the eighth PMOS transistor, respectively; the drain end of the ninth PMOS tube is electrically connected with the source ends of the seventh PMOS tube and the eighth PMOS tube; grid ends of the ninth PMOS tube and the tenth PMOS tube are electrically connected with grids of the first PMOS tube and the fourth PMOS tube; the drain terminal of the tenth PMOS tube is used as the output terminal of the amplifying circuit;

the drain ends of the fifth NMOS tube and the sixth NMOS tube are respectively and electrically connected with the drain ends of the ninth PMOS tube and the tenth PMOS tube; grid ends of the fifth NMOS tube and the sixth NMOS tube are electrically connected with grids of the first NMOS tube and the fourth NMOS tube; the source end of the fifth NMOS tube is used as a positive phase input end of the amplifying circuit, and the source end of the sixth NMOS tube is used as a negative phase input end of the amplifying circuit;

In this embodiment, the fifth PMOS transistor P1, the sixth PMOS transistor P2, the third PMOS transistor P4, the fourth PMOS transistor P8, the seventh PMOS transistor P5, the eighth PMOS transistor P6, the ninth PMOS transistor P9, the tenth PMOS transistor P10, the seventh NMOS transistor N3, the eighth NMOS transistor N4, the fifth NMOS transistor N7, and the sixth NMOS transistor N8 form a folded cascade cascode structure, and the P-type differential current formed by the fifth PMOS transistor P1 and the sixth PMOS transistor P2 is folded into a P-type current mirror by using a P-type current buffer formed by the ninth PMOS transistor P9 and the tenth PMOS transistor P10 and an N-type current buffer formed by the fifth NMOS transistor N7 and the sixth NMOS transistor N8, wherein the current mirror is formed by the seventh PMOS transistor P5 and the eighth PMOS transistor P6. The mirror bias currents of the seventh NMOS transistor N3 and the eighth NMOS transistor N4 need to provide at least 1.5 times of the current of the third PMOS transistor P4, so as to ensure that the fifth NMOS transistor N7, the sixth NMOS transistor N8, the seventh PMOS transistor P5, the eighth PMOS transistor P6, the ninth PMOS transistor P9, and the tenth PMOS transistor P10 do not enter a linear region due to the undersize bias current of the third PMOS transistor P4, and even if the current of the third PMOS transistor P4 drops to zero, the fifth NMOS transistor N7, the sixth NMOS transistor N8, the seventh PMOS transistor P5, the eighth PMOS transistor P6, the ninth PMOS transistor P9, and the tenth PMOS transistor P10 are not completely turned off, so that the turned-off transistors are prevented from being turned on again to consume extra time. In the above structure, the output end of the folded cascade structure is the drain end Vo of the tenth PMOS transistor P10, and the output voltage swing is:

VDS4+VDS8(SAT)<Vo<VIO-VSD6-VSD10(SAT)，

wherein, VDS4 is the drain terminal and source terminal pressure difference of the eighth NMOS tube N4

VDS8 (SAT) is saturation voltage difference between drain and source of the sixth NMOS transistor N8

Vo is output voltage of VOUT end

VIO being voltage of voltage source

VSD6 is the pressure difference between the source end and the drain end of an eighth PMOS pipe P6

VSD10 (SAT) is the saturation voltage difference between the source end and the drain end of a tenth PMOS pipe P10

As an alternative embodiment, the output circuit includes:

the first end of the adjustable resistor R2 is electrically connected with the other one of the source electrode or the drain electrode of the driving tube; the first end of the adjustable resistor is electrically connected with the source end of the fifth NMOS tube through a first capacitor C1; the first end of the adjustable resistor is used as an output end and is grounded through a second capacitor;

a first end of the third resistor R3 is electrically connected with a second end of the adjustable resistor, and the second end of the third resistor is grounded; and the first end of the third resistor is electrically connected with the grid electrode of the sixth PMOS tube.

In this embodiment, the driving transistor may be an NMOS transistor N9, and may also be a PMOS transistor P11, for a wide power domain chip, two driving structures may be integrated at the same time, and a VIO voltage determination module integrated in the chip determines which kind of driving design architecture to select, when the VIO is high, the NMOS transistor (N9) is selected as the driving transistor design architecture, when the VIO is low, the PMOS transistor P11 is selected as the driving transistor design, the output terminal Vout voltage passes through a resistor R2, R3 voltage division feeds back to the negative terminal P2 gate terminal of the operational amplifier, C1 is a miller compensation capacitor, so as to improve the frequency characteristic and the phase margin performance of the operational amplifier.

As an optional implementation manner, the size ratio of the second NMOS transistor, the third NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor is 1. In the present embodiment, the above-described ratio is adopted to ensure accurate output of the first current mirror with respect to the first bias current. In the present embodiment, the size ratio refers to the ratio of the number of transistors (multiplier) of the second NMOS transistor, the third NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor.

As an alternative embodiment, the size ratio of the second PMOS transistor to the third PMOS transistor is 1. In the present embodiment, the second current mirror is used to ensure amplification of the first bias current and to ensure accurate output of the second bias current in the aforementioned ratio.

As an optional implementation manner, the size ratio of the seventh PMOS transistor to the eighth PMOS transistor is 1. In the present embodiment, to ensure accurate difference of input pair transistors with respect to current, a PMOS transistor with a size ratio of 1.

As an optional implementation manner, the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor adopt an aspect ratio size, and the first PMOS transistor, the fourth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor adopt an aspect ratio size. The inverse ratio size refers to that the width W/length L of the channel of the MOS tube is less than 1, and the inverse ratio size is adopted, so that the devices can work in a saturation region in a direct current state in a power domain range, and meanwhile, the device is beneficial to improving the PSRR (power supply rejection ratio) of the LDO

It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A low dropout linear voltage regulator circuit, comprising:

the input end of the first current mirror is electrically connected with a bias current source and used for amplifying the current input by the bias current source into first bias current according to a preset first proportion;

2. The low dropout linear voltage regulating circuit of claim 1, wherein said first current mirror comprises:

3. The low dropout linear voltage regulator circuit of claim 2, wherein said second current mirror comprises:

4. The low dropout linear voltage regulator circuit of claim 3 wherein said differential circuit comprises a pair of input pair transistors, said input pair transistors comprising:

5. The low dropout linear voltage regulator circuit of claim 4, wherein said cascode amplification circuit comprises:

a seventh PMOS tube and an eighth PMOS tube which are arranged in a common grid mode, wherein source ends of the seventh PMOS tube and the eighth PMOS tube are both electrically connected with a voltage source;

a ninth PMOS transistor and a tenth PMOS transistor which are arranged in a common gate, source ends of the ninth PMOS transistor and the tenth PMOS transistor being electrically connected to drain ends of the seventh PMOS transistor and the eighth PMOS transistor, respectively; the drain terminal of the ninth PMOS tube is electrically connected with the source terminals of the seventh PMOS tube and the eighth PMOS tube; grid ends of the ninth PMOS tube and the tenth PMOS tube are electrically connected with grids of the first PMOS tube and the fourth PMOS tube; the drain terminal of the tenth PMOS tube is used as the output terminal of the amplifying circuit;

6. The low dropout linear voltage regulator circuit of claim 5, wherein said output circuit comprises:

the first end of the adjustable resistor is electrically connected with the other of the source electrode or the drain electrode of the driving tube; a first end of the adjustable resistor is electrically connected with a source end of the fifth NMOS tube through a first capacitor C1; the first end of the adjustable resistor is used as an output end and is grounded through a second capacitor;

7. The low dropout linear voltage regulating circuit according to claims 5-6, wherein the second NMOS transistor, the third NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor have a dimensional ratio of 1.

8. The low dropout linear voltage regulating circuit according to claims 3-6, wherein the second PMOS transistor and the third PMOS transistor have a size ratio of 1.

9. The low dropout linear voltage regulating circuit of claims 5-6, wherein a size ratio of said seventh PMOS transistor to said eighth PMOS transistor is 1.

10. The device of claims 5-6, wherein the first NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are inverse size of width to length ratio, and the first PMOS transistor, the fourth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are inverse size of width to length ratio.