CN111179983A - Sensitive amplifier circuit - Google Patents
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- CN111179983A CN111179983A CN201911258945.2A CN201911258945A CN111179983A CN 111179983 A CN111179983 A CN 111179983A CN 201911258945 A CN201911258945 A CN 201911258945A CN 111179983 A CN111179983 A CN 111179983A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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Abstract
The invention discloses a sensitive amplifier circuit, which comprises a main sensitive amplifying circuit, a pre-charging circuit, a column decoding circuit and a storage circuit, wherein the main sensitive amplifying circuit is connected with the pre-charging circuit; according to the invention, a part of circuits of the sensitive amplifier are changed from MOS tubes needing high voltage resistance to low-voltage MOS tubes, so that the whole area is reduced, and the whole power consumption is also reduced; meanwhile, the novel structure of the invention also simplifies the structure of the differential circuit, reduces the requirements of MOS tubes needing to be matched, improves the response speed of the circuit and supports higher-speed application.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a sensitive amplifier circuit.
Background
As shown in fig. 1, a power supply of an SA circuit is powered by VDD, for a wide-voltage application, a MOS transistor needs to be determined according to a high-voltage range during selection, and the output voltage range of cl0_ int/cl1_ int of the SA circuit is the highest and is close to the VDD power supply, so that MOS transistors in the SA circuit all need high-voltage MOS transistors, and therefore the length of the MOS transistors also needs a large size and the area of the MOS transistors is large. The matching requirement of the differential circuit is high, the switch tube S2 of the existing circuit is turned on during the pre-charging period, the symmetrical node voltages of the differential circuit are basically consistent, and actually, when the transistor N0 and the transistor N1 are mismatched, the mismatched deviation is introduced into the amplification stage of the SA amplification circuit, so that when the output caused by the time deviation is opposite to the actual signal output, a longer time sequence is required for the latch stage to determine the good state, and the speed is influenced.
Disclosure of Invention
The invention aims to provide a sensitive amplifier circuit, which changes partial circuits of a sensitive amplifier from MOS tubes needing high withstand voltage to low-voltage MOS tubes, reduces the whole area and simultaneously reduces the whole power consumption; meanwhile, the novel structure of the invention also simplifies the structure of the differential circuit, reduces the requirements of MOS tubes needing to be matched, improves the response speed of the circuit and supports higher-speed application.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a sense amplifier circuit comprising a main sense amplifying circuit, a precharge circuit, a column decoding circuit, and a memory circuit, the main sense amplifying circuit comprising:
the isolation tube is a depletion type MOS tube, the grid end of the isolation tube generates a clamping voltage VDDR, the clamping voltage VDDR with a certain magnitude is set, and the grid end of the isolation tube is used for clamping the main sensitive amplifying circuit;
a pair of MOS tubes which are mirror images of each other, including a first MOS tube and a second MOS tube, respectively connected with the first row decoding circuit and the second row decoding circuit;
the other pair of transistors which are mirror images each other comprises a third MOS transistor and a fourth MOS transistor, and the third MOS transistor and the fourth MOS transistor are depletion type MOS transistors; the fourth MOS tube, the second MOS tube, the first MOS tube and the third MOS tube are sequentially connected in series, and another fifth MOS tube is connected between the formed series branch and the isolation tube; any one or more of the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube is/are MOS tubes with low breakdown voltage.
Preferably, the clamping voltage VDDR is based on the power supply VDD and is generated by a charge pump or a low dropout linear regulator.
Preferably, the precharge circuit is divided into two-side precharge circuits which are symmetrical to each other, the precharge circuit on each side only comprises one MOS transistor, and the MOS transistors of the precharge circuits on the two sides are respectively and directly connected with the two input ends of the latch.
Preferably, the isolation tube is an NMOS transistor; the first MOS transistor is a first NMOS transistor, and the second MOS transistor is a second NMOS transistor; the third MOS transistor is a third NMOS transistor, and the fourth MOS transistor is a fourth NMOS transistor; the fifth MOS transistor is a fifth PMOS transistor.
Preferably, a source terminal of the isolation tube is connected to a source terminal of a fifth PMOS transistor, and drain terminals of the fifth MOS transistors are connected to a drain terminal of the third NMOS transistor and a drain terminal of the fourth NMOS transistor.
Preferably, the drain terminal of the third NMOS transistor is connected to the drain terminal of the fourth NMOS transistor; the grid end of the third NMOS transistor is connected with the grid end of the fourth NMOS transistor; and the source terminal of the third NMOS transistor and the source terminal of the fourth NMOS transistor are respectively connected with the drain terminal of the first NMOS transistor and the drain terminal of the second NMOS transistor.
Preferably, the gate terminal of the first NMOS transistor and the gate terminal of the second NMOS transistor are connected; a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor are respectively connected with a first terminal of the first switch and a first terminal of the second switch, and a second terminal of the first switch is connected with a second terminal of the second switch; the source terminal of the first NMOS transistor is connected with the first row decoding circuit, and the source terminal of the second NMOS transistor is connected with the second row decoding circuit; one of the first switch and the second switch is open and the other is closed.
Preferably, the MOS transistors in the two-side precharge circuit are a sixth PMOS transistor and a seventh PMOS transistor, respectively; a source terminal of the sixth PMOS transistor and a source terminal of the seventh PMOS transistor are both connected with a source terminal of the fifth PMOS transistor; and the drain terminal of the sixth PMOS transistor and the drain terminal of the seventh PMOS transistor are respectively connected with the first input end and the second input end of the latch.
Preferably, a first terminal of the third switch is connected to a drain terminal of the first NMOS transistor, and a second terminal of the third switch is connected to a drain terminal of the second NMOS transistor; the third switch is closed during the precharge phase and open during the sense amplification phase.
Preferably, when the voltage-sensitive amplifier is in a pre-charging stage, the drain terminal of the sixth PMOS transistor and the drain terminal of the seventh PMOS transistor are pre-charged to a certain voltage point through a pre-charging circuit, and the third switch is turned off to balance the main sensitive amplifier circuit; opening the fifth PMOS transistor before the pre-charging is finished, and enabling the first NMOS transistor and the second NMOS transistor to enter a saturation region; when the pre-charging is finished, the pre-charging circuit is closed, meanwhile, the third switch is opened, and a sensitive amplification stage is started; when the first storage array is read, the first switch is turned on, and the second switch is turned off; when reading the second storage array, the second switch is opened, and the first switch is closed; when the memory array is read, the current of the first NMOS transistor is completely loaded on the third NMOS transistor, and a reference current Iref is loaded on the fourth NMOS transistor; when the current of the memory cell read with the current is larger than the reference current Iref, the output voltage difference of the sensitive amplifier circuit is positive; when the current-free memory cell is read, the current of the first NMOS transistor is smaller than the reference current Iref, and the output voltage difference of the sensitive amplifier circuit is negative; when in the latch stage, the latch latches data according to the voltage relationship of the first input terminal and the second input terminal: when the voltage V at the first input terminalcl0_int>Voltage V at second input terminalcl1_intWhen the output result Dout outputs 0; when the voltage V at the first input terminalcl0_int<Voltage V at second input terminalcl1_intAnd then, the output result Dout outputs 1 to complete the reading function.
Compared with the prior art, the invention has the beneficial effects that: (1) the sensitive amplifier changes a part of circuits from MOS tubes needing high voltage resistance to low-voltage MOS tubes, reduces the whole area and simultaneously reduces the whole power consumption; meanwhile, the differential circuit structure is simplified, the requirements of MOS (metal oxide semiconductor) tubes needing to be matched are reduced, the response speed of the circuit is improved, and higher-speed application is supported; (2) the sense amplifier circuit is used in a reading circuit in the existing memory chip, all the speed data are read in parallel for increasing the speed, all the number of the speed data are increased along with the increase of the capacity, the reduction of the area is obvious to reduce the whole chip, the miniaturization of the existing chip is facilitated, the sense amplifier circuit is more suitable for wearing equipment such as Bluetooth and a bracelet, meanwhile, the reduction of the power consumption also enables the equipment to have longer standby working time, and the quality of the whole product is improved; (3) the detection sensitivity and speed of the sensitive amplifier circuit are optimized, the response speed and precision of the whole product are improved, the product has better interactive response experience, and the product competitiveness is obviously improved.
Drawings
FIG. 1 is a circuit diagram of a prior art sense amplifier;
FIG. 2 is a schematic diagram of a sense amplifier circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, the sense amplifier circuit of the invention for low voltage dual-side amplification is symmetrical and mainly includes a main sense amplifier circuit, a precharge circuit, a column decoding circuit (such as column decoding circuit 0 and column decoding circuit 1 shown in fig. 2) and a memory circuit (such as memory array 0 and memory array 1 shown in fig. 2). The sense amplifier circuit of the present invention is mainly used for reading the memory array 0 or the memory array 1, that is, for detecting whether a selected memory cell in a selected memory array is "0" or "1".
The main sensitive amplifying circuit comprises two NMOS transistors (N-type MOS transistors), which are mirror-image pair transistors, namely a transistor N0 and a transistor N1. The main sensitive amplifying circuit further comprises two depletion type NMOS transistors for differential load, namely a first depletion type transistor Na1(native NMOS transistor) and a second depletion type transistor Na 2.
As shown in fig. 2, the first depletion transistor Na1 and the second depletion transistor Na2 are a mirror pair of transistors, the gate terminal of the first depletion transistor Na1 is connected to the gate terminal of the second depletion transistor Na2, and the drain terminal of the first depletion transistor Na1 is connected to the drain terminal of the second depletion transistor Na 2. The first depletion transistor Na1 and the second depletion transistor Na2 are both NMOS transistors with threshold voltage close to 0V, that is, the first depletion transistor Na1 and the second depletion transistor Na2 are different from ordinary NMOS transistors in that the turn-on voltage is close to 0V, and the application of the NMOS transistor of this type and the method shown in fig. 2 is close to linear resistance.
In this embodiment, the main sensitive amplifying circuit further includes a transistor P2 (P-type MOS transistor) and a third depletion transistor Na0 (also called a clamp transistor, N-type MOS transistor). The drain terminal of the transistor P2 is connected to the source terminal of the second depletion transistor Na2, and the source terminal of the transistor P2 is connected to the source terminal of the third depletion transistor Na 0.
As shown in fig. 2, the drain terminal of the third depletion transistor Na0 is connected to a power supply VDD, and the power supply VDD supplies power to the whole sense amplifier circuit. The gate terminal of the third depletion transistor Na0 generates a clamping voltage VDDR of the sense amplifier circuit, which is generated by the power supply VDD, and which maintains a same output voltage at all times for wide voltage applications, i.e., VDD varies from input voltage to input voltage.
The supply voltage VDDR is generated by a charge pump (pump) or a low dropout regulator (LDO).
In this embodiment, the third depletion transistor Na0 is used as an isolation tube, the voltage VDDR is isolated by the third depletion transistor Na0, and the voltage VDDR is set to a proper value, so that the sense amplifier circuit (SA circuit) can select MOS transistors with low threshold voltages (for example, depletion transistors Na1 and Na2, and transistor N0, transistor N1, and transistor P2) except for the third depletion transistor Na0, and the MOS transistors with low threshold voltages can support lower operating voltages, and the MOS transistors with smaller lengths are used to reduce the overall area, where the value of the low threshold voltage is a relative voltage determined by process characteristics, and the MOS transistors with low threshold voltages are also referred to as MOS transistors with low breakdown voltages. In the invention, a differential mirror image PMOS (such as transistors P0 and P1 and transistors P2 and P3 in FIG. 1) is changed into a native NMOS transistor with low threshold voltage, and a common-mode voltage feedback circuit is not required to be additionally added under the condition of maintaining the original differential structure.
The VDDR current load is modified into the voltage load mainly because the VDDR is usually generated by a pump, the circuit requirement is high under the condition of the current load, the power consumption is large, namely, the voltage resistance problem can be caused mainly by directly using a power supply VDDR to supply power, so that a native tube (a clamping tube Na0) is added to clamp a main circuit of the sensitive amplifier below the VDDR when the native tube is applied at high voltage, and the performance index of the sensitive amplifier circuit can be improved by adopting an MOS tube with low threshold voltage. And in low voltage, the VDDR voltage is far higher than the VDD voltage, and Vgs is far larger than Vth, so that the terminal voltages of a source terminal and a drain terminal of the Native transistor are nearly equal. Therefore, the main circuit of the sensitive amplifier is clamped by the grid of the native tube, only a capacitive load is used, the driving circuit is simple, and the low-power-consumption design can be realized.
As shown in fig. 2, the main sensitive amplifying circuit of the present invention further includes three switches, which are switch S0, switch S1 and switch S3. The switch S0 and the switch S1 are a pair of symmetrical switches. The switch S0 and the switch S1 are connected in series, one end of the switch S0 is connected to one end of the switch S1, the other end of the switch S0 is connected to the source terminal of the transistor N0, and the other end of the switch S1 is connected to the source terminal of the transistor N1. The first terminal and the second terminal of the switch S3 are connected to the drain terminal of the transistor N0 and the drain terminal of the transistor N1, respectively, that is, the first terminal and the second terminal of the switch S3 are connected to the source terminal of the first depletion transistor Na1 and the source terminal of the second depletion transistor Na2, respectively.
In this embodiment, one of the switch S0 and the switch S1 is open, and the other is closed. For example, when reading memory array 0, switch S0 is open and switch S1 is closed; when reading the memory array 1, switch S1 is open and switch S0 is closed. Switch S3 is closed during the precharge phase, but open during the sense amplification phase.
As shown in fig. 2, in a pair of symmetrical precharge circuits, each side of the precharge circuit includes only one PMOS transistor (e.g., the transistor P6 or the transistor P5 in fig. 2). The transistor P6 of one of the precharge circuits is connected to the cl1_ int terminal (one input terminal of the latch), and the transistor P5 of the other precharge circuit is connected to the cl0_ int terminal (the other input terminal of the latch), which is different from the prior art precharge and discharge circuit that connects the source cl1 of the transistor N1 to the source terminal cl0 (shown in fig. 1) of the transistor N0, because the pair of precharge circuits of the present invention eliminates the clamp N2 and the clamp N3 (shown in fig. 1) of the prior art precharge circuit, and compared with the prior art, no switch S2 is provided between the source terminal cl1 of the transistor N1 and the source terminal cl0 of the transistor N0 in the main sense amplifying circuit of the present invention, thereby reducing the influence of mismatch between the transistors N0 and N1.
In this embodiment, the drain terminal of the transistor P6 is connected to the cl1_ int terminal, the source terminal of the transistor P6 is connected to the source terminal of the transistor P2, similarly, the drain terminal of the transistor P5 is connected to the cl0_ int terminal, and the source terminal of the transistor P5 is connected to the source terminal of the transistor P2.
As shown in fig. 2, in a pair of column decoding circuits symmetrical to each other, one of the column decoding circuits 0 is connected to the output terminal cl0 of the transistor N0, and the column decoding circuit 0 is further connected to the memory array 0; another column decoding circuit 1 is connected to the output cl1 of the transistor N1, and the column decoding circuit 1 is also connected to the memory array 1.
The Saenb signals of the gate terminal of the transistor P6, the gate terminal of the transistor P5, and the gate terminal of the transistor P2 of the present embodiment are enable control signals of the sense amplifier circuit, and are active low.
The gate terminal of the transistor N1 and the gate terminal of the transistor N0 of the present embodiment are connected, and the Vlim terminal at which the gate terminal of the transistor N1 and the gate terminal of the transistor N0 are connected is a reference voltage input of the sense amplifier, and cl0 and cl1 voltages of the sense amplifier are clamped and controlled.
The sensitive amplifying circuit of the invention is divided into three working stages, namely a pre-charging stage, a sensitive amplifying stage and a latching stage. The sensitive amplifying circuit of the invention has the following working stages:
when the first node is in the precharge phase, the nodes cl0_ int and cl1_ int are precharged to a certain voltage point through the precharge circuit, and at this time, the switch S3 is closed to make the left and right sides of SA reach balance.
And secondly, before the pre-charging is finished (about 3nS), the transistor P2 is turned on, so that the transistor N0 and the transistor N1 enter a saturation region.
And (III) at the end of the pre-charging, the pre-charging circuit is closed, and the switch S3 is opened at the same time, so that the sensitive amplification stage is entered. When the storage array 0 is read, the switch S0 is opened, and the switch S1 is closed; when reading the memory array 1, switch S1 is open and switch S0 is closed.
(1) Taking the read memory array 0 as an example, when reading the memory cell, the current of the transistor N0 is fully loaded on the clamp tube Na1, and the current Iref is fully loaded on the second depletion transistor Na2, because the first depletion transistor Na1 and the second depletion transistor Na2 are mirror pair transistors, the drain terminals are connected, assuming that the transconductance of Na1/Na2 is gnaThen the output voltage difference of the sense amplifier is Vcl1_int-Vcl0_int＝gna*(IN0-Iref)；
When the current of the memory cell read with the current is larger than Iref, so that the voltage drop of the first depletion transistor Na1 is larger than that of the second depletion transistor Na2, the voltage difference (V) of the output of the sense amplifier is largercl1_int-Vcl0_int) Is positive;
when reading a non-current memory cell, the current of transistor N0 is less than the Iref current, (V)cl1_int-Vcl0_int)＝gna*(IN0Iref) is negative, the sense amplifier output differential is negative.
(IV) when in the latch stage, the latch latches the data according to the voltage relationship of cl0_ int and cl1_ int, and when the voltage V is in the latch stagecl0_int>Voltage Vcl1_intWhen V is greater than V, the output result Dout outputs "0cl0_int<Vcl1_intWhile, Dout outputs "1"; the read function is completed.
In summary, the present invention optimizes the conventional Sense Amplifier (SA) circuit, so that a low-voltage MOS transistor with a low threshold can be used, a lower operating voltage can be supported, and the influence of mismatch between the transistor N0 and the transistor N1 in the differential circuit can be reduced.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (10)
1. A sense amplifier circuit includes a main sense amplifier circuit, a precharge circuit, a column decode circuit, and a memory circuit,
the main sensitive amplifying circuit comprises:
an isolation tube (Na0) connected with a power supply VDD, wherein the isolation tube is a depletion type MOS tube, the grid end of the depletion type MOS tube generates a clamping voltage VDDR, the clamping voltage VDDR is set to a certain magnitude, and the grid end of the isolation tube is used for clamping the main sensitive amplifying circuit;
a pair of MOS transistors which are mirror images of each other, including a first MOS transistor (N0) and a second MOS transistor (N1), which are respectively connected with the first row decoding circuit and the second row decoding circuit;
the other pair of transistors which are mirror images comprises a third MOS transistor (Na1) and a fourth MOS transistor (Na2), wherein the third MOS transistor (Na1) and the fourth MOS transistor (Na2) are depletion type MOS transistors; a fourth MOS tube (Na2), a second MOS tube (N1), a first MOS tube (N0) and a third MOS tube (Na1) are connected in series, and another fifth MOS tube (P2) is connected between the formed series branch and the isolation tube (Na 0); any one or more of the first MOS transistor (N0), the second MOS transistor (N1), the third MOS transistor (Na1), the fourth MOS transistor (Na2) and the fifth MOS transistor (P2) are MOS transistors with low breakdown voltage.
2. The sense amplifier circuit of claim 1,
the clamping voltage VDDR is based on the supply voltage VDD and is generated by a charge pump or a low dropout linear regulator.
3. The sense amplifier circuit of claim 1 or 2,
the pre-charging circuit is divided into two symmetrical pre-charging circuits at two sides, the pre-charging circuit at each side only comprises one MOS tube, and the MOS tubes of the pre-charging circuits at two sides are respectively and directly connected with two input ends of the latch.
4. The sense amplifier circuit of claim 3,
the isolation tube (Na0) is an NMOS transistor;
the first MOS transistor (N0) is a first NMOS transistor, and the second MOS transistor (N1) is a second NMOS transistor;
the third MOS transistor (Na1) is a third NMOS transistor, and the fourth MOS transistor (Na2) is a fourth NMOS transistor;
the fifth MOS transistor (P2) is a fifth PMOS transistor.
5. The sense amplifier circuit of claim 4,
the drain electrode of the isolation tube (Na0) is connected with the power supply, and the source terminal of the isolation tube (Na0) is connected with the source terminal of a fifth PMOS transistor (P2);
the drain end of the fifth MOS transistor (P2) is connected with the drain end of the third NMOS transistor (Na1) and the drain end of the fourth NMOS transistor (Na 2).
6. The sense amplifier circuit of claim 5,
the drain terminal of the third NMOS transistor (Na1) is connected with the drain terminal of a fourth NMOS transistor (Na 2);
the gate terminal of the third NMOS transistor (Na1) is connected with the gate terminal of the fourth NMOS transistor (Na 2);
the source terminal of the third NMOS transistor (Na1) and the source terminal of the fourth NMOS transistor (Na2) are respectively connected with the drain terminal of the first NMOS transistor (N0) and the drain terminal of the second NMOS transistor (N1).
7. The sense amplifier circuit of claim 6,
the gate terminal of the first NMOS transistor (N0) and the gate terminal of the second NMOS transistor (N1) are connected;
a source terminal of a first NMOS transistor (N0) and a source terminal of the second NMOS transistor (N1) are connected with a first terminal of a first switch (S0) and a first terminal of a second switch (S1), respectively, and a second terminal of the first switch (S0) and a second terminal of the second switch (S1);
the source terminal of the first NMOS transistor (N0) is connected to the first column decode circuit, and the source terminal of the second NMOS transistor (N1) is connected to the second column decode circuit;
one of the first switch (S0) and the second switch (S1) is open and the other is closed.
8. The sense amplifier circuit of claim 4,
MOS transistors in the two-side pre-charging circuit are respectively a sixth PMOS transistor (P5) and a seventh PMOS transistor (P6);
a source terminal of the sixth PMOS transistor (P5) and a source terminal of the seventh PMOS transistor (P6) are both connected with a source terminal of the fifth PMOS transistor (P2);
a drain terminal of the sixth PMOS transistor (P5) and a drain terminal of the seventh PMOS transistor (P6) are connected to a first input terminal (cl0_ int) and a second input terminal (cl1_ int) of the latch, respectively.
9. The sense amplifier circuit of claim 7,
a first terminal of the third switch (S3) is connected to a drain terminal of a first NMOS transistor (N0),
a second terminal of the third switch (S3) is connected to a drain terminal of a second NMOS transistor (N1);
the third switch (S3) is closed during the precharge phase and open during the sense amplification phase.
10. The sense amplifier circuit of claim 8,
when in a pre-charge phase, the drain terminal of the sixth PMOS transistor (P5) and the drain terminal of the seventh PMOS transistor (P6) are pre-charged to a certain voltage point through a pre-charge circuit, and the third switch (S3) is closed to balance the main sensitive amplifying circuit;
turning on the fifth PMOS transistor (P2) before the end of the pre-charging to enable the first NMOS transistor (N0) and the second NMOS transistor (N1) to enter a saturation region;
when the pre-charging is finished, the pre-charging circuit is closed, meanwhile, the third switch is switched off, and a sensitive amplification stage is started; when the first storage array is read, the first switch is switched off, and the second switch is switched on; when reading the second storage array, the second switch is opened, and the first switch is closed;
when reading the memory array, the first NMOS transistor (N0) is loaded with the current on the third NMOS transistor (Na1) and the reference current Iref is loaded on the fourth NMOS transistor (Na 2);
when the current of the memory cell read with the current is larger than the reference current Iref, the output voltage difference of the sensitive amplifier circuit is positive;
when reading the currentless memory cell, the current of the first NMOS transistor (N0) is smaller than the reference current Iref, and the output voltage difference of the sensitive amplifier circuit is negative;
when in the latch phase, the latch latches data according to the voltage relationship of the first input terminal (cl0_ int) and the second input terminal (cl1_ int): when the voltage V at the first input terminalcl0_int>Voltage V at second input terminalcl1_intWhen the output result Dout outputs 0; when the voltage V at the first input terminalcl0_int<Voltage V at second input terminalcl1_intAnd then, the output result Dout outputs 1 to complete the reading function.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113555042A (en) * | 2021-08-03 | 2021-10-26 | 北京紫光青藤微系统有限公司 | Sensitive amplifier circuit and memory |
| WO2023123667A1 (en) * | 2021-12-31 | 2023-07-06 | 长鑫存储技术有限公司 | Control amplification circuit, sense amplifier and semiconductor memory |
| US11894048B2 (en) | 2021-12-31 | 2024-02-06 | Changxin Memory Technologies, Inc. | Control amplifying circuit, sense amplifier and semiconductor memory |
| US12033689B2 (en) | 2021-12-31 | 2024-07-09 | Changxin Memory Technologies, Inc. | Amplification control method and circuit, sensitive amplifier and semiconductor memory |
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| US20120243325A1 (en) * | 2011-03-24 | 2012-09-27 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US20130100740A1 (en) * | 2011-10-20 | 2013-04-25 | Min She | Compact Sense Amplifier for Non-Volatile Memory Suitable for Quick Pass Write |
| CN105895139A (en) * | 2016-03-30 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | Sense amplifier |
| CN107527639A (en) * | 2016-06-22 | 2017-12-29 | 中芯国际集成电路制造（天津）有限公司 | Memory reading circuitry and its read method |
| CN107464581A (en) * | 2017-08-09 | 2017-12-12 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifier circuit |
| CN108282153A (en) * | 2017-12-15 | 2018-07-13 | 普冉半导体（上海）有限公司 | A kind of sensitive amplifier circuit of the bilateral amplification of low-voltage |
| CN110244095A (en) * | 2019-07-19 | 2019-09-17 | 电子科技大学 | A kind of high speed current sampling circuit of super low-power consumption |
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| CN113555042A (en) * | 2021-08-03 | 2021-10-26 | 北京紫光青藤微系统有限公司 | Sensitive amplifier circuit and memory |
| CN113555042B (en) * | 2021-08-03 | 2023-12-19 | 北京紫光青藤微系统有限公司 | Sense amplifier circuit and memory |
| WO2023123667A1 (en) * | 2021-12-31 | 2023-07-06 | 长鑫存储技术有限公司 | Control amplification circuit, sense amplifier and semiconductor memory |
| US11894048B2 (en) | 2021-12-31 | 2024-02-06 | Changxin Memory Technologies, Inc. | Control amplifying circuit, sense amplifier and semiconductor memory |
| US12033689B2 (en) | 2021-12-31 | 2024-07-09 | Changxin Memory Technologies, Inc. | Amplification control method and circuit, sensitive amplifier and semiconductor memory |
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Address after: Room 504, 560 Shengxia Road, Pudong New Area, Shanghai 200000 Applicant after: Praran semiconductor (Shanghai) Co.,Ltd. Address before: Room 503-504, No. 560, shengxia Road, Pudong New Area, Shanghai 201210 Applicant before: PUYA SEMICONDUCTOR (SHANGHAI) Co.,Ltd. |
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Application publication date: 20200519 |