CN115699294A - 设备沟道轮廓结构 - Google Patents

设备沟道轮廓结构 Download PDF

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CN115699294A
CN115699294A CN202180037914.3A CN202180037914A CN115699294A CN 115699294 A CN115699294 A CN 115699294A CN 202180037914 A CN202180037914 A CN 202180037914A CN 115699294 A CN115699294 A CN 115699294A
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width
fin
transistor
transistor circuit
fins
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杨海宁
C·郭
鲍军静
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Qualcomm Inc
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Qualcomm Inc
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Abstract

可以改进晶体管沟道轮廓结构以提供更好的晶体管电路性能。在一个示例中，晶体管电路可以针对NMOS晶体管和PMOS晶体管包括不同的鳍轮廓，诸如NMOS鳍(150)比PMOS鳍(120)厚，或者NMOS鳍具有直的垂直表面并且PMOS鳍在鳍底部区域处具有凹口。在又一示例中，晶体管电路可以针对NMOS GAA器件和PMOS GAA器件包括不同的纳米片轮廓，其中NMOS纳米片比PMOS纳米片厚。这种配置优化了NMOS晶体管和PMOS晶体管，其中NMOS具有低沟道电阻，而PMOS具有较低的短沟道效应。

Description

设备沟道轮廓结构
相关申请的交叉引用
本专利申请要求2020年06月30日提交的、题目为“DEVICE CHANNEL PROFILESTRUCTURE”的美国非临时申请号16/917451的权益，其被转让给本申请的受让人，并且通过引用以其整体明确并入本文。
技术领域
本公开总体上涉及晶体管，并且更具体地但不排他地涉及晶体管沟道轮廓。
背景技术
基于晶体管(诸如，互补金属氧化物半导体(CMOS)晶体管、鳍式场效应晶体管(finfet)和非片状全环绕栅极(GAA)晶体管)的设备变得越来越普遍，这驱动了对更好和更小的晶体管的需求。CMOS晶体管正在从平面晶体管缩放到finfet，并且正在迁移到纳米片全环绕栅极(GAA)器件。随着制造技术缩放到5nm节点，制造工艺变得更加复杂，并且器件性能变得难以进一步改进。Finfet和GAA设备缩放受限于短沟道效应和高沟道电阻。例如，鳍轮廓(顶部厚度和底部厚度)和GAA纳米片厚度对于finfet和GAA器件的短沟道效应(泄漏)和驱动电流性能至关重要。此外，由于NMOS finfet和PMOS finfet对不同的沟道轮廓具有不同的响应，因此问题复杂性增加。例如，n沟道金属氧化物半导体(NMOS)晶体管需要较低的沟道电阻以获得高性能，而P沟道金属氧化物半导体(PMOS)晶体管需要较薄的沟道来控制短沟道效应。
因此，需要克服常规方法(包括据此提供的方法、系统和装置)的缺陷的系统、装置和方法。
发明内容
以下呈现与一个或多个方面和/或示例有关的简化概述，该一个或多个方面和/或示例与本文公开的装置和方法相关联。如此，以下概述不应当被视为与所有预期的方面和/或示例有关的详尽概览，也不应当被认为标识与所有预期的方面和/或示例有关的关键或重要元素，或描绘与任何特定方面和/或示例相关联的范围。相应地，以下概述具有如下唯一目的：在下面呈现的详细描述之前，以简化形式呈现与关于本文公开的装置和方法的一个或多个方面和/或示例有关的某些概念。
在一个方面，一种晶体管电路包括：第一鳍式场效应晶体管，包括具有第一宽度的第一鳍；以及第二鳍式场效应晶体管，包括具有第二宽度的第二鳍，其中第一宽度小于第二宽度。
在另一个方面，一种晶体管电路包括：用于放大和切换的第一部件，包括具有第一宽度的第一鳍；以及用于放大和切换的第二部件，包括具有第二宽度的第二鳍，其中第一宽度小于第二宽度。
在又一个方面，一种晶体管电路包括：第一全环绕栅极(GAA)晶体管，包括具有第一厚度的第一沟道；以及第二GAA晶体管，包括具有第二厚度的第二沟道，其中第一厚度大于第二厚度。
在又一个方面，一种用于制造晶体管电路的方法包括：提供硅衬底；在硅衬底上形成第一鳍式场效应晶体管的第一鳍；在硅衬底上靠近第一鳍形成第二鳍式场效应晶体管的第二鳍；修整第一鳍的第一宽度，经修整的第一宽度小于第二鳍的第二宽度；以及在第一鳍和第二鳍上形成栅极。
基于附图和详细描述，与本文公开的装置和方法相关联的其他特征和优点对于本领域技术人员将是明显的。
附图说明
对本公开的方面及其许多伴随优点的更完整理解将因其在结合附图考虑时参考以下详细描述变得更好理解而易于获得，附图仅出于图示目的被呈现，而不是对本公开的限制，其中：
图1A-图1B图示了根据本公开的一些示例的具有不同的鳍宽度的示例性晶体管电路；
图2A-图2B图示了根据本公开的一些示例的具有鳍凹口的示例性晶体管电路；
图3A-图3B图示了根据本公开的一些示例的具有不同的纳米片厚度的示例性晶体管电路；
图4A-图4I图示了根据本公开的一些示例的用于制造具有不同的鳍宽度的晶体管电路的示例性部分方法；
图5A-图5C图示了根据本公开的一些示例的用于制造具有鳍凹口的晶体管电路的示例性部分方法；
图6A-图6C图示了根据本公开的一些示例的用于制造具有不同的纳米片厚度的晶体管电路的示例性部分方法；
图7图示了根据本公开的一些示例的用于制造晶体管电路的示例性部分方法；
图8图示了根据本公开的一些示例的示例性移动设备；以及
图9图示了根据本公开的一些示例的可以与上述方法、设备、半导体设备、集成电路、裸片、中介层、封装或层叠封装(PoP)中的任何集成的各种电子设备。
按照惯例，附图所描绘的特征可以未按比例绘制。因此，为了清楚起见，可以任意扩大或缩小所描绘特征的尺寸。按照惯例，为了清楚起见，附图中的一些附图被简化。因此，附图可以未描绘特定装置或方法的所有组件。此外，贯穿说明书和附图，相同的附图标记表示相同的特征。
具体实施方式
本文公开的示例性方法、装置和系统减轻了常规方法、装置和系统的缺点，以及其他先前未标识的需求。本文的示例包括用于改进晶体管电路的沟道性能的轮廓结构。在一个示例中，晶体管电路由针对NMOS晶体管和PMOS晶体管的不同的鳍轮廓组成，其中NMOS鳍比PMOS鳍厚(在鳍的顶部和底部两者处)。在另一个示例中，晶体管电路由分别针对NMOS晶体管和PMOS晶体管的不同的鳍轮廓组成，其中NMOS鳍具有直的垂直表面，并且PMOS鳍在鳍底部区域处具有凹口(notch)。在又一个示例中，晶体管电路由针对NMOS GAA器件和PMOSGAA器件的不同的纳米片轮廓组成，其中NMOS纳米片比PMOS纳米片厚。在这种示例中，NMOS晶体管和PMOS晶体管两者被优化，其中NMOS具有低沟道电阻(因此具有较高的驱动电流)，而PMOS具有较低的短沟道效应(因此具有较低的泄漏)。
图1A-图1B图示了根据本公开的一些示例的具有不同的鳍宽度的示例性晶体管电路。如图1A中所示，晶体管电路100可以包括具有第一鳍120和第一衬底130(例如硅、硅锗或类似材料)的第一晶体管110(例如P型finfet)、具有第二鳍150和第二衬底160的第二晶体管140(例如，N型finfet)，以及共享栅极170。虽然第一晶体管110和第二晶体管140被示为具有两个鳍、单独的衬底和共享栅极，但应当理解，每个晶体管可以具有更多或更少的鳍，鳍的数目在第一晶体管110与第二晶体管140之间可以不同，可以使用公共衬底来代替单独的衬底，并且可以使用单独的栅极来代替公共或共享的栅极。
图1B示出了沿图1A中的切割线的侧视图。如图1A的俯视图中所示，每个第一鳍120具有第一长度122和第一宽度124，并且每个第二鳍150具有第二长度152和第二宽度154。如图1B中所示，第一宽度124包括第一顶部宽度126和第一底部宽度128，并且第一顶部宽度126小于第一底部宽度128。第一底部宽度128比第一顶部宽度126更靠近第一衬底130。如图1B中所示，第二宽度154包括第二顶部宽度156和第二底部宽度158，并且第二顶部宽度156小于第二底部宽度158。第二底部宽度158比第二顶部宽度156更靠近第二衬底160。此外，第一顶部宽度126小于或少于第二顶部宽度156，并且第一底部宽度128小于或少于第二底部宽度158。鳍轮廓中较长或较大的宽度会减小电阻，并且使鳍不太容易受到短沟道效应的影响(对n型finfet有利)。相比之下，鳍轮廓中较短或较小的宽度可以增加电阻，但会使鳍更容易受到短沟道效应的影响，这又使短沟道效应(高泄漏电流)更可控(对p型finfet有利)。
图2A-图2B图示了根据本公开的一些示例的具有鳍凹口的示例性晶体管电路。如图2A中所示，晶体管电路200(例如晶体管电路100)可以包括具有第一鳍220和第一衬底230(例如硅、硅锗或类似材料)的第一晶体管210(例如P型finfet)、具有第二鳍250和第二衬底260的第二晶体管240(例如N型finfet)以及共享栅极270。虽然第一晶体管210和第二晶体管240被示为具有两个鳍、单独的衬底和共享栅极，但应当理解，每个晶体管可以具有更多或更少的鳍，鳍的数目在第一晶体管210与第二晶体管240之间可以不同，可以使用公共衬底来代替单独的衬底，并且可以使用单独的栅极来代替公共或共享的栅极。
图2B示出了沿图2A中的切割线的侧视图。如图2A的俯视图中所示，每个第一鳍220具有第一长度222和第一宽度224，并且每个第二鳍250具有第二长度252和第二宽度254。如图2B中所示，第一宽度224包括第一顶部宽度226、第一凹口宽度229和第一底部宽度228。第一顶部宽度226小于第一底部宽度228，并且第一凹口宽度229小于第一底部宽度228。第一凹口宽度229可以与第一顶部宽度226相同、比第一顶部宽度226大或比第一顶部宽度226小。在靠近底部的凹口位置处的较短或较小的宽度可以增加电阻，但会使鳍更容易受到短沟道效应的影响，这反过来又使短沟道效应(高泄漏电流)更可控(对p型finfet有利)。
图3A-图3B图示了根据本公开的一些示例的具有不同纳米片厚度的示例性晶体管电路。如图3A中所示，晶体管电路300可以包括具有第一衬底330(例如硅、硅锗或类似材料)的第一晶体管310(例如，P型GAA器件)、具有第二衬底360的第二晶体管340(例如，N型GAA器件)，以及共享栅极370。虽然第一晶体管310和第二晶体管340被示为具有单独的衬底和共享的栅极，但是应当理解，可以使用公共衬底来代替单独的衬底，并且可以使用单独的栅极来代替公共或共享的栅极。
图3B示出了沿图3A中的切割线的侧视图。如图3B中所示，第一晶体管310包括具有第一厚度324的第一沟道320，第二晶体管340包括具有第二厚度354的第二沟道350，并且第一厚度324小于或少于第二厚度354。沟道轮廓中的较小厚度可以增加电阻，但会使鳍更容易受到短沟道效应的影响，这又反过来使短沟道效应(高泄漏电流)更可控(对p型GAA器件有利)。
图4A-图4I图示了根据本公开的一些示例的用于制造具有不同的鳍宽度的晶体管电路的示例性部分方法。如图4A中所示，用于制造晶体管电路(例如，晶体管电路100)的部分方法400可以开始于提供公共衬底430，形成用于第一晶体管410的多个第一鳍420，形成用于第二晶体管440的多个第二鳍450，以及将掩模480(例如，诸如SiN的硬掩模)施加到每个第一鳍420和第二鳍450的顶部。此外，可以在该阶段处形成伪栅极(dummy gate)。部分方法400可以在图4B中继续，其中填充浅沟槽隔离氧化物482并将其平坦化以平整顶部部分。部分方法400可以在图4C中继续，其中去除氧化物482的一部分以露出第一鳍420。
部分方法400可以在图4D中继续，其中修整第一鳍420以减小鳍宽度或轮廓。如所示的，修整可以包括氧化和从鳍表面去除氧化物。部分方法400可以在图4E中继续，其中掩蔽第一鳍420(例如，光致抗蚀剂膜或掩模)并且去除氧化物以露出第二鳍450。部分方法400可以在图4F中继续，其中去除各种掩模并且在第一鳍420和第二鳍450周围形成公共栅极470。
备选地，部分方法400可以包括将第一鳍420与第二鳍450分开地形成，如图4G-图4I中所示。如图4G中所示，部分方法400可以包括提供衬底430，将掩模480施加到将成为第一鳍420和第二鳍450的位置。如图4H中所示，部分方法400可以包括将掩模484施加到第二鳍450位置，并且在第一鳍420位置处修整掩模480，使得第一鳍420的第一宽度将少于或小于第二鳍450的第二宽度。如图4I中所示，部分方法400可以包括露出第一鳍420，随后露出第二鳍450(未示出)。
图5A-图5C图示了根据本公开的一些示例的用于制造具有鳍凹口的晶体管电路的示例性部分方法。如图5A中所示，用于制造晶体管电路(例如，晶体管电路200)的部分方法500可以如图4A-图4D或图4G-图4I中所示那样开始，并且包括提供公共衬底530，形成用于第一晶体管510的多个第一鳍520，形成用于第二晶体管540的多个第二鳍550，以及在使氧化物部分地凹陷以露出第一鳍520之后，在第一鳍520中的每个第一鳍上在靠近顶部部分形成第一鳍间隔物586。第一鳍间隔物586可以通过沉积SiN层并且蚀刻来形成，以形成第一鳍间隔物586。部分方法500可以在图5B中继续，其中去除第一鳍间隔物586下方的氧化物和氧化物482以露出第一鳍420的部分。部分方法500可以在图5C中继续，其中修整第一鳍间隔物586下方的第一鳍420以将鳍宽度或轮廓减小到第一凹口宽度529。如所示的，修整可以包括氧化和从鳍表面去除氧化物。
图6A-图6C图示了根据本公开的一些示例的用于制造具有不同的纳米片厚度的晶体管电路的示例性部分方法。如图6A中所示，用于制造晶体管电路(例如，晶体管电路300)的部分方法500可以包括提供公共衬底630，形成用于第一晶体管610的多个第一沟道620，以及形成用于第二晶体管640的多个第二沟道650。沟道形成可以包括形成多层Si和SiGe以形成伪多晶硅栅极，并且使第一晶体管610区域中的伪多晶硅凹陷。部分方法600可以在图6B中继续，其中从第一晶体管610区域选择性地去除SiGe。部分方法600可以在图6C中继续，其中修整第一沟道620纳米片以将沟道宽度(即，垂直方向上的厚度与水平方向上的宽度)或轮廓减小到小于第二沟道650的宽度(厚度)。
图7图示了根据本公开的一些示例的用于制造晶体管电路的示例性部分方法。如图7中所示，部分方法700可以在框702中以提供硅衬底开始。部分方法700可以在框704中继续，其中在硅衬底上形成第一finfet晶体管的第一鳍。部分方法700可以在框706中继续，其中在硅衬底上靠近第一鳍形成第二finfet晶体管的第二鳍。部分方法700可以在框708中继续，其中修整第一鳍的第一宽度，经修整的第一宽度小于第二鳍的第二宽度。部分方法700可以在框710中结束，其中在第一鳍和第二鳍上形成栅极。备选地，部分方法700可以包括将晶体管电路并入到选自由以下项构成的组的设备中：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器和机动交通工具中的设备。
图8图示了根据本公开的一些示例的示例性移动设备。现在参考图8，描绘了根据示例性方面配置的移动设备的框图，并且通常被指定为800。在一些方面中，移动设备800可以被配置为无线通信设备。如所示的，移动设备800包括处理器801，处理器801可以被配置为实现本文在一些方面中描述的方法。处理器801被示为包括指令管线812，缓冲处理单元(BPU)808、分支指令队列(BIQ)811，以及本领域公知的节流阀810。为了清楚起见，从处理器801的该视图中省略了这些块的其他公知细节(例如，计数器、条目、置信度字段、加权和、比较器等)。
处理器801可以通过链路通信地耦合到存储器832，该链路可以是裸片到裸片或芯片到芯片链路。移动设备800还包括显示器828和显示控制器826，其中显示控制器826耦合到处理器801和显示器828。
在一些方面中，图8可以包括耦合到处理器801的编码器/解码器(CODEC)834(例如，音频和/或语音CODEC)；耦合到CODEC 834的扬声器836和麦克风838；以及耦合到无线天线842和处理器801的无线控制器840(其可以包括调制解调器)。
在特定方面中，在存在上述块中的一个或多个块的情况下，处理器801、显示控制器826、存储器832、CODEC 834和无线控制器840可以被包括在系统级封装或片上系统设备822中。输入设备830(例如，物理或虚拟键盘)、电源844(例如电池)、显示器828、输入设备830、扬声器836、麦克风838、无线天线842和电源844可以在片上系统设备822外部并且可以耦合到片上系统设备822的组件，诸如接口或控制器。
应当注意，尽管图8描绘了移动设备，但处理器801和存储器832也可以被集成到机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、个人数字助理(PDA)、固定位置数据单元、计算机、膝上型计算机、平板计算机、通信设备、移动电话或其他类似设备中。
图9图示了根据本公开的一些示例的可以与前述集成设备、半导体设备、集成电路、裸片、中介层、封装或层叠封装(PoP)中的任何集成的各种电子设备。例如，移动电话设备902、膝上型计算机设备904和固定位置终端设备906可以包括如本文所述的集成设备900。集成设备900可以例如是本文描述的集成电路、裸片、集成设备、集成设备封装、集成电路设备、设备封装、集成电路(IC)封装、层叠封装设备中的任一种。图9中图示的设备902、904、906仅是示例性的。其他电子设备也可以以集成设备900为特征，包括但不限于一组设备(例如电子设备)，该组设备包括：移动设备、手持个人通信系统(PCS)单元、诸如个人数字助理的便携式数据单元、启用全球定位系统(GPS)的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、诸如读表装备的固定位置数据单元、通信设备、智能电话、平板计算机、计算机、可穿戴设备、服务器、路由器、在机动交通工具(例如，自动交通工具)中实现的电子设备，或存储或取回数据或计算机指令的任何其他设备，或其任何组合。
应当理解，本文公开的各个方面可以被描述为本领域技术人员描述和/或认识的结构、材料和/或设备的功能等同物。还应当注意，在描述或权利要求中公开的方法、系统和装置可以由包括用于执行该方法的相应动作的部件的设备来实现。例如，在一个方面，晶体管电路可以包括：用于放大和切换的第一部件(例如，CMOS晶体管、finfet晶体管、GAA晶体管等)，包括具有第一宽度的第一鳍；以及用于放大和切换的第二部件，包括具有第二宽度的第二鳍，其中第一宽度小于第二宽度。应当理解，前述方面仅作为示例被提供，并且要求保护的各个方面不限于作为示例引用的特定参考和/或说明。
图1-图9中图示的组件、过程、特征和/或功能中的一者或多者可以被重新布置和/或被组合成单个组件、过程、特征或功能，或者被并入在数个组件、过程、或功能中。在不脱离本公开的情况下，还可以添加附加的元件、组件、过程和/或功能。还应当注意，本公开中的图1-图9及其对应的描述不限于裸片和/或IC。在一些实施方式中，图1-图9及其对应的描述可以用于制造、创建、提供和/或生产集成设备。在一些实施方式中，设备可以包括裸片、集成设备、裸片封装、集成电路(IC)、设备封装、集成电路(IC)封装、晶圆、半导体设备、层叠封装(PoP)设备和/或中介层。设备的有源侧(诸如裸片)是设备的一部分，其包含设备的有源组件(例如晶体管、电阻器、电容器、电感器等)，有源组件执行设备的操作或功能。设备的背面是设备的与有源侧相对的一侧。
如本文所使用的，术语“用户装备”(或“UE”)、“用户设备”、“用户终端”、“客户端设备”、“通信设备”、“无线设备”、“无线通信设备”、“手持式设备”、“移动设备”、“移动终端”、“移动站”、“手机”、“接入终端”、“订户设备”、“订户终端”、“订户站”、“终端”以及其变型可以互换地指代可以接收无线通信和/或导航信号的任何适当的移动或固定设备。这些术语包括但不限于音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、智能手机、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器、机动交通工具中的机动设备，和/或通常由人携带和/或具有通信能力(例如，无线、蜂窝、红外、短范围无线电等)的其他类型的便携式电子设备。这些术语还旨在包括与另一设备通信的设备，该另一设备可以诸如通过短距离无线、红外、有线连接或其他连接来接收无线通信和/或导航信号，无论是在该设备处还是在其他设备处出现卫星信号接收、辅助数据接收，和/或与位置有关的处理。此外，这些术语旨在包括所有设备，包括无线和有线通信设备，它们能够经由无线电接入网络(RAN)与核心网络进行通信，并且通过核心网络，UE可以与诸如因特网的外部网络连接，以及与其他UE连接。当然，对于UE来说，连接到核心网络和/或因特网的其他机制也是可能的，诸如通过有线接入网络、无线局域网(WLAN)(例如，基于IEEE 802.11等)，等等。UE可以由多种类型的设备中的任何一种来实施，包括但不限于印刷电路(PC)卡、紧凑型闪存设备、外部或内部调制解调器、无线或有线电话、智能手机、平板、追踪设备、资产标签等等。UE通过其向RAN发送信号的通信链路被称为上行信道(例如，反向流量信道、反向控制信道、接入信道等)。RAN可以通过其向UE发送信号的通信链路被称为下行链路或前向链路信道(例如，寻呼信道、控制信道、广播信道、前向流量信道等)。如本文所使用的，术语流量信道(TCH)可以指代上行链路/反向或下行链路/前向流量信道。
电子设备之间的无线通信可以是基于不同的技术，诸如码分多址(CDMA)、W-CDMA、时分多址(TDMA)、频分多址(FDMA))、正交频分复用(OFDM)、全球移动通信系统(GSM)、3GPP长期演进(LTE)、蓝牙(BT)、蓝牙低功耗(BLE)、IEEE 802.11(WiFi)和IEEE 802.15.4(Zigbee/Thread)或可以用于无线通信网络或数据通信网络的其他协议。蓝牙低功耗(也被称为蓝牙LE、BLE和蓝牙智能)是一种由蓝牙特别兴趣小组设计和销售的无线个人区域网络技术，旨在在维持类似通信范围的同时，显著降低功耗和成本。在2010年，随着蓝牙核心规范版本4.0的采用和蓝牙5的更新，BLE被合并到主要的蓝牙标准中(两者以其整体明确并入本文)。
词语“示例性”在本文中用于表示“用作示例、实例或说明”。本文描述为“示例性”的任何细节不应当被解释为优于其他示例。同样，术语“示例”不意味着所有示例都包括所讨论的特征、优势或操作模式。此外，特定特征和/或结构可以与一个或多个其他特征和/或结构组合。此外，在此描述的装置的至少一部分可以被配置为执行在此描述的方法的至少一部分。
本文使用的术语是出于描述特定示例的目的，并且不旨在限制本公开的示例。如本文所使用的，单数形式“一”、“一个”和“该”旨在也包括复数形式，除非上下文另有明确指示。还应当理解，术语“包括”、“具有”、“含有”和/或“包含”在本文中使用时，指定了所述特征、整数、动作、操作、元件和/或组件的存在，但不排除一个或多个其他特征、整数、动作、操作、元件、组件和/或它们的组的存在或添加。
应当注意，术语“连接”、“耦合”或其任何变型意指元件之间的任何直接或间接的连接或耦合，并且可以涵盖中间元件在两个元件之间的存在(该两个元件经由中间元件“连接”或“耦合”在一起)。
本文对使用诸如“第一”、“第二”等名称的元件的任何引用不限制这些元件的数量和/或顺序。相反，这些名称被用作区分两个或两个以上元件和/或元件实例的便利方法。此外，除非另有说明，元件的集合可以包括一个或多个元件。
本申请中的任何陈述或图示都不旨在将任何组件、动作、特征、利益、优势或等同物奉献给公众，无论该组件、动作、特征、利益、优势或等同物是否被记载在权利要求书中。
此外，本领域技术人员应当理解，结合本文公开的示例描述的各种说明性逻辑块、模块、电路和算法动作可以被实现为电子硬件、计算机软件或两者的组合。为了清楚地说明硬件和软件的这种可互换性，各种说明性组件、块、模块、电路和动作在上面根据其功能被一般化描述。这种功能性被实现为硬件还是软件取决于特定应用和施加在整体系统上的设计约束。技术人员可以针对每个特定应用以不同方式实现所描述的功能，但是这种实现决策不应当被解释为导致偏离本公开的范围。
结合本文公开的示例描述的方法、序列和/或算法可以被直接包含在硬件中、在由处理器执行的软件模块中，或在两者的组合中。软件模块可以驻存在RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动磁盘、CD-ROM或本领域已知的任何其他形式的存储介质中，包括非暂态类型的存储器或存储介质。示例性存储介质耦合到处理器，使得处理器可以从存储介质读取信息，并且可以将信息写入到存储介质。在备选方案中，存储介质可以是与处理器成一体。
虽然已经结合设备描述了一些方面，但是不用说，这些方面也构成了对对应方法的描述，因此设备的块或组件也应当被理解为对应的方法动作，或者被理解为方法动作的特征。与之类似地，结合方法动作或作为方法动作描述的方面也构成对对应设备的对应块或细节或特征的描述。方法动作中的一些或所有方法动作可以由硬件装置(或使用硬件装置)执行，例如，诸如微处理器、可编程计算机或电子电路。在一些示例中，最重要方法动作中的一些或多个最重要方法动作可以由这种装置执行。
在上面的详细描述中可以看出，不同的特征在示例中被组合在一起。这种公开方式不应当被理解为所要求保护的示例具有比相应权利要求中明确提及的特征更多的特征的意图。相反，本公开可以包括少于所公开的个体示例的所有特征。因此，所附权利要求应当视为被包含在描述中，其中每个权利要求本身可以作为单独示例。虽然每个权利要求本身可以作为单独示例，但应当注意，尽管权利要求中的从属权利要求可以引用具有一个或多个权利要求的具体组合，但其他示例也可以涵盖或包括所述从属权利要求与任何其他从属权利要求的主题内容的组合，或任何特征与其他从属和独立权利要求的组合。这种组合在本文被提出，除非明确表达不想要特定的组合。此外，还旨在使权利要求的特征可以被包括在任何其他独立权利要求中，即使所述权利要求不直接从属于该独立权利要求。
此外，在一些示例中，单个动作可以被细分为多个子动作或包含多个子动作。这种子动作可以被包含在单个动作的公开中，并且是单个动作的公开的一部分。
虽然前述公开示出了本公开的说明性示例，但是应当注意，在不脱离如由所附权利要求限定的本公开的范围的情况下，可以在本文中进行各种改变和修改。根据本文描述的公开的示例的方法权利要求的功能和/或动作不需要以任何特定顺序被执行。此外，公知的元件将不被详细描述或可以被省略，以免混淆本文公开的方面和示例的相关细节。此外，尽管可能以单数形式描述或要求保护本公开的元件，但除非明确声明限制为单数，否则复数形式被预期。

Claims (30)

1.一种晶体管电路，包括：
第一鳍式场效应晶体管，包括具有第一宽度的第一鳍；以及
第二鳍式场效应晶体管，包括具有第二宽度的第二鳍，其中所述第一宽度小于所述第二宽度。
2.根据权利要求1所述的晶体管电路，其中所述第一鳍式场效应晶体管被配置为p型鳍式场效应晶体管。
3.根据权利要求2所述的晶体管电路，其中所述第二鳍式场效应晶体管被配置为n型鳍式场效应晶体管。
4.根据权利要求1所述的晶体管电路，其中所述第二鳍式场效应晶体管被配置为n型鳍式场效应晶体管。
5.根据权利要求1所述的晶体管电路，其中所述第一宽度包括第一顶部宽度和第一底部宽度，并且所述第一顶部宽度小于所述第一底部宽度。
6.根据权利要求5所述的晶体管电路，其中所述第一宽度还包括在所述第一顶部宽度与所述第一底部宽度之间的第一凹口宽度，并且所述第一凹口宽度小于所述第一底部宽度。
7.根据权利要求1所述的晶体管电路，其中所述第一鳍式场效应晶体管包括多个鳍，所述第二鳍式场效应晶体管包括多个鳍，并且所述第一鳍式场效应晶体管的所述多个鳍中的每个鳍具有比所述第二鳍式场效应晶体管的所述多个鳍中的每个鳍更小的宽度。
8.根据权利要求1所述的晶体管电路，其中所述晶体管电路被并入到设备中，所述设备选自由以下项组成的组：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器和机动交通工具中的设备。
9.一种晶体管电路，包括：
用于放大和切换的第一部件，包括具有第一宽度的第一鳍；以及
用于放大和切换的第二部件，包括具有第二宽度的第二鳍，其中所述第一宽度小于所述第二宽度。
10.根据权利要求9所述的晶体管电路，其中用于放大和切换的所述第一部件被配置为p型鳍式场效应晶体管。
11.根据权利要求10所述的晶体管电路，其中用于放大和切换的所述第二部件被配置为n型鳍式场效应晶体管。
12.根据权利要求9所述的晶体管电路，其中用于放大和切换的所述第二部件被配置为n型鳍式场效应晶体管。
13.根据权利要求9所述的晶体管电路，其中所述第一宽度包括第一顶部宽度和第一底部宽度，并且所述第一顶部宽度小于所述第一底部宽度。
14.根据权利要求13所述的晶体管电路，其中所述第一宽度还包括在所述第一顶部宽度与所述第一底部宽度之间的第一凹口宽度，并且所述第一凹口宽度小于所述第一底部宽度。
15.根据权利要求9所述的晶体管电路，其中用于放大和切换的所述第一部件包括多个鳍，用于放大和切换的所述第二部件包括多个鳍，并且用于放大和切换的所述第一部件的所述多个鳍中的每个鳍具有比用于放大和切换的所述第二部件的所述多个鳍中的每个鳍更小的宽度。
16.根据权利要求9所述的晶体管电路，其中所述晶体管电路被并入到设备中，所述设备选自由以下项组成的组：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器和机动交通工具中的设备。
17.一种晶体管电路，包括：
第一全环绕栅极(GAA)晶体管，包括具有第一厚度的第一沟道；以及
第二GAA晶体管，包括具有第二厚度的第二沟道，其中所述第一厚度大于所述第二厚度。
18.根据权利要求17所述的晶体管电路，其中所述第一GAA晶体管被配置为p型GAA器件。
19.根据权利要求18所述的晶体管电路，其中所述第二GAA晶体管被配置为n型GAA器件。
20.根据权利要求17所述的晶体管电路，其中所述第二GAA晶体管被配置为n型GAA器件。
21.根据权利要求17所述的晶体管电路，其中所述第一GAA晶体管包括多个沟道，所述第二GAA晶体管包括多个沟道，并且所述第一GAA晶体管的所述多个沟道中的每个沟道具有比所述第二GAA晶体管的所述多个沟道中的每个沟道更大的厚度。
22.根据权利要求17所述的晶体管电路，其中所述晶体管电路被并入到设备中，所述设备选自由以下项组成的组：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器和机动交通工具中的设备。
23.一种用于制造晶体管电路的方法，所述方法包括：
提供硅衬底；
在所述硅衬底上形成第一鳍式场效应晶体管的第一鳍；
在所述硅衬底上靠近所述第一鳍形成第二鳍式场效应晶体管的第二鳍；
修整所述第一鳍的第一宽度，经修整的所述第一宽度小于所述第二鳍的第二宽度；以及
在所述第一鳍和所述第二鳍上形成栅极。
24.根据权利要求23所述的方法，其中所述第一鳍式场效应晶体管被配置为p型鳍式场效应晶体管。
25.根据权利要求24所述的方法，其中所述第二鳍式场效应晶体管被配置为n型鳍式场效应晶体管。
26.根据权利要求23所述的方法，其中所述第二鳍式场效应晶体管被配置为n型鳍式场效应晶体管。
27.根据权利要求23所述的方法，其中所述第一宽度包括第一顶部宽度和第一底部宽度，并且所述第一顶部宽度小于所述第一底部宽度。
28.根据权利要求27所述的方法，其中所述第一宽度还包括在所述第一顶部宽度与所述第一底部宽度之间的第一凹口宽度，并且所述第一凹口宽度小于所述第一底部宽度。
29.根据权利要求23所述的方法，还包括形成多个第一鳍以及形成多个第二鳍，其中所述第一鳍式场效应晶体管的所述多个第一鳍中的每个第一鳍具有比所述第二鳍式场效应晶体管的所述多个第二鳍中的每个第二鳍更小的宽度。
30.根据权利要求23所述的方法，还包括将所述晶体管电路并入到设备中，所述设备选自由以下项组成的组：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器和机动交通工具中的设备。
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