US20160126240A1 - Methods and apparatuses for forming multiple radio frequency (rf) components associated with different rf bands on a chip - Google Patents
Methods and apparatuses for forming multiple radio frequency (rf) components associated with different rf bands on a chip Download PDFInfo
- Publication number
- US20160126240A1 US20160126240A1 US14/991,868 US201614991868A US2016126240A1 US 20160126240 A1 US20160126240 A1 US 20160126240A1 US 201614991868 A US201614991868 A US 201614991868A US 2016126240 A1 US2016126240 A1 US 2016126240A1
- Authority
- US
- United States
- Prior art keywords
- region
- component
- characteristic
- band
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims description 97
- 125000001475 halogen functional group Chemical group 0.000 claims description 58
- 239000002019 doping agent Substances 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 39
- 238000012545 processing Methods 0.000 claims description 36
- 125000006850 spacer group Chemical group 0.000 claims description 25
- 230000000295 complement effect Effects 0.000 claims description 12
- 235000012431 wafers Nutrition 0.000 description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 36
- 229910052710 silicon Inorganic materials 0.000 description 36
- 239000010703 silicon Substances 0.000 description 36
- 239000012212 insulator Substances 0.000 description 34
- 238000013461 design Methods 0.000 description 29
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000007943 implant Substances 0.000 description 12
- 238000004891 communication Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000002800 charge carrier Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 238000012358 sourcing Methods 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 230000000704 physical effect Effects 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- -1 contacts Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/429—Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/432—Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7209—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched from a first band to a second band
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7236—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
Definitions
- the present disclosure is generally related methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip.
- RF radio frequency
- wireless computing devices such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users.
- portable wireless telephones such as cellular telephones and internet protocol (IP) telephones
- IP internet protocol
- wireless telephones can communicate voice and data packets over wireless networks.
- many such wireless telephones include other types of devices that are incorporated therein.
- a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player.
- such wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.
- LTE Long-term evolution
- RF radio frequency
- GHz gigahertz
- devices in North America will use 700/800 megahertz (MHz) frequency bands and 1,700/1,900 MHz frequency bands
- devices in Europe will use 800 MHz, 1,800 MHz, and 2,600 MHz frequency bands.
- the wireless device must operate at each of the frequency bands.
- the wireless device should be backwards compatible with prior standards (e.g., global system for mobile communication (GSM) standards, universal mobile telecommunications system (UMTS) standards, and wireless local area network (WLAN) standards).
- GSM global system for mobile communication
- UMTS universal mobile telecommunications system
- WLAN wireless local area network
- the wireless device includes multiple RF components that are each configured to operate (meet performance and reliability criteria) at a corresponding frequency band of the multiple frequency bands.
- the wireless device includes a first power amplifier (PA) configured to operate in the 800 MHz frequency band, a second PA configured to operate in the 1,800 MHz frequency band, and a third PA configured to operate in the 2,600 MHz frequency band.
- PA power amplifier
- Each RF component for a particular frequency band is typically provided on a single chip, such as a chip formed using gallium arsenide (GaAs) or indium gallium phosphide (InGaP) chips. Accordingly, the wireless device includes multiple chips, each with different frequency-band-specific devices, to operate at multiple frequency bands. The use of multiple chips is expensive, requires a large footprint (e.g., printed circuit (PC) board area), and increases a size of the wireless device.
- PC printed circuit
- the present disclosure provides methods of performing a complementary metal-oxide-semiconductor (CMOS) process on a wafer (e.g., a die) to form multiple radio frequency (RF) circuits (e.g., a first RF circuit and a second RF circuit) that each operate at different RF bands.
- the wafer may include a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer.
- Each of the RF circuits may include a receiver, a transmitter, or a combination thereof.
- a first RF circuit may be designed to operate at a first RF band
- a second RF circuit may be designed to operate at a second RF band.
- the CMOS process may include forming, on the first RF circuit, a first RF device having a first device type and a first characteristic and forming a second RF device having a second device type and a second characteristic on the second RF circuit.
- the first RF device and the second RF device are the same type of device (i.e., have a same device type), such as a power amplifier, an antenna switch, or a low noise amplifier.
- the first characteristic and the second characteristic are the same type of characteristic (i.e., same characteristic type), such as an oxide thickness, a lightly doped region profile, or a halo profile. However, a value of the first characteristic is different than a value of the second characteristic.
- a first oxide thickness of the first device may be thicker than a second oxide thickness of the second device.
- the value of the first characteristic may be determined to enable the first RF circuit to operate at the first RF band
- the value of the second characteristic may be determined to enable the second RF circuit to operate at the second RF band.
- a method in a particular embodiment, includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band, and the second device corresponds to a second RF band that is different from the first RF band.
- RF radio frequency
- a device in a particular embodiment, includes a first radio frequency (RF) component and a second RF component on a die.
- the first RF component corresponds to a first RF band
- the second RF component corresponds to a second RF band that is different from the first RF band.
- the first RF component includes a first gate oxide having a first thickness
- the second RF component includes a second gate oxide having a second thickness that is different from the first thickness.
- an apparatus in a further particular embodiment, includes a first radio frequency (RF) component corresponding to a first RF band, and a second RF component corresponding to a second RF band that is different from the first RF band.
- the first RF component includes first means for gating a first channel. The first channel is positioned between first means for sourcing first current to the first channel and first means for draining the first current from the first channel. The means for gating the channel is isolated from first semiconductor means for conducting first charge carriers by a first insulator.
- the second RF component includes second means for gating a second channel. The second channel is positioned between second means for sourcing second current to the second channel and second means for draining the second current from the second channel. The second means for gating the second channel is isolated from second semiconductor means for conducting second charge carriers by a second insulator. A first thickness of the first insulator is different than a second thickness of the second insulator.
- a non-transitory computer-readable medium includes instructions that, when executed by a processor, cause the processor to initiate formation of a complementary metal-oxide-semiconductor (CMOS) device.
- the formation of the CMOS device includes forming a first gate oxide in a first region and in a second region of a wafer.
- the CMOS device is further formed by performing first processing to form a second gate oxide in the second region.
- the second gate oxide has a different thickness than the first gate oxide.
- the formation of the CMOS device also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region.
- the first device corresponds to a first radio frequency (RF) band
- the second device corresponds to a second RF band that is different from the first RF band.
- RF radio frequency
- a device in another particular embodiment, includes a first radio frequency (RF) component and a second RF component on a die.
- the first RF component corresponds to a first RF band
- the second RF component corresponds to a second RF band that is different from the first RF band.
- the first RF component includes a first lightly doped region having a first value of a characteristic
- the second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value.
- a device in another particular embodiment, includes a first radio frequency (RF) component and a second RF component on a die.
- the first RF component corresponds to a first RF band
- the second RF component corresponds to a second RF band that is different from the first RF band.
- the first RF component includes a first halo region having a first value of a characteristic
- the second RF component includes a second halo region having a second value of the characteristic that is different from the first value.
- a method in another particular embodiment, includes a first step for forming a first gate oxide in a first region and in a second region of a wafer. The method further includes a second step for performing first processing to form a second gate oxide in the second region, the second gate oxide having a different thickness than the first gate oxide. The method also includes a third step for forming first gate material of a first device in the first region and forming second gate material of a second device in the second region.
- the first device corresponds to a first radio frequency (RF) band
- the second device corresponds to a second RF band that is different from the first RF band.
- RF radio frequency
- a method in another particular embodiment, includes performing, on a wafer, a complementary metal-oxide-semiconductor (CMOS) process to form a first radio frequency (RF) circuit and a second RF circuit.
- the first RF circuit is designed to operate at a first RF band and the second RF circuit is designed to operate at a second RF band.
- Performing the CMOS process includes forming a first RF device of the first RF circuit and forming a second RF device of the second RF circuit.
- the first RF device has a first device type and a first value of a characteristic
- the second RF device has a second device type and a second value of the characteristic.
- the first device type and the second device type are a same device type, and the first value of the characteristic is different from the second value of the characteristic.
- a method in another particular embodiment, includes receiving design information representing at least one physical property of a semiconductor device.
- the semiconductor device includes a first radio frequency (RF) component and a second RF component on a die.
- the first RF component corresponds to a first RF band
- the second RF component corresponds to a second RF band that is different from the first RF band.
- the first RF component includes a first gate oxide having a first thickness
- the second RF component includes a second gate oxide having a second thickness that is different from the first thickness.
- the method further includes transforming the design information to comply with a file format and generating a data file including the transformed design information.
- a single die may advantageously include multiple RF band circuits that are each designed for performance and reliability at a corresponding frequency band.
- the die may have a smaller form factor and may be produced at a reduced cost as compared to including a RF circuit on a separate chip for each frequency band.
- FIG. 1 is a block diagram of a first illustrative embodiment of a device having a die that accommodates multiple radio frequency (RF) bands;
- RF radio frequency
- FIGS. 2A-B are block diagrams of illustrative embodiments of complementary metal-oxide-semiconductor (CMOS) devices that accommodate multiple RF bands;
- CMOS complementary metal-oxide-semiconductor
- FIG. 3 is a flow diagram of an illustrative embodiment of a first method to form a die that accommodates multiple RF bands;
- FIG. 4 is a flow diagram of an illustrative embodiment of a second method to form a die that accommodates multiple RF bands;
- FIG. 5 is a flow diagram of an illustrative embodiment of a third method to form a die that accommodates multiple RF bands;
- FIG. 6 is a block diagram of a device including the die of FIG. 1 ;
- FIG. 7 is a data flow diagram of an illustrative embodiment of a manufacturing process including the die of FIG. 1 .
- a device 100 (e.g., a communication device) that accommodates multiple radio frequency (RF) bands is shown.
- the device 100 includes a die 102 having multiple RF circuits, such as a first RF band circuit 110 , a second RF band circuit 120 , an Nth RF band circuit 130 , and additional circuitry 140 .
- the die 102 may be packaged in (e.g., incorporated in) a chip, such as a semiconductor chip. Although the die 102 is shown as including the additional circuitry 140 , the additional circuitry 140 may be coupled to the die 102 but not be included in the die 102 .
- the device 100 may include a communication device, such as a portable communication device) configured for RF communication.
- the device 100 may include one or more additional components or circuits (not shown), such as a processor (e.g., a digital signal processor), a wireless transceiver, a memory, an antenna, one or more other components, or a combination thereof.
- a processor e.g
- the multiple RF circuits 110 , 120 , 130 , the additional circuitry 140 , or a combination thereof, may be formed by a front end process, such as a front end complementary metal-oxide-semiconductor (CMOS) process.
- CMOS complementary metal-oxide-semiconductor
- the front end process may be performed with respect to a wafer (e.g., from which the die 102 is created), as described further herein.
- the die 102 includes multiple RF circuits (e.g., the first RF band circuit 110 , the second RF band circuit 120 , the Nth RF band circuit 130 ), and the additional circuitry 140 (e.g., control circuitry).
- the die 102 shows three different RF band circuits 110 , 120 , 130
- the die 102 may include two RF band circuits or more than three RF band circuits.
- Each of the RF band circuits 110 , 120 , 130 may include one or more components.
- the first RF band circuit 110 may include a first device 112
- the second RF band circuit 120 may include a second device 122
- the Nth RF band circuit 130 may include an Nth device 132 .
- Each of the first device 112 , the second device 122 , and the Nth device may be a same device type, such as a power amplifier, an antenna switch, or a low noise amplifier and may be constructed during a single front end process flow.
- Each of the RF band circuits 110 , 120 , 130 may correspond to a different RF band.
- each of the RF band circuits 110 , 120 , 130 may be designed to operate at a different RF band and within a corresponding electrical domain of operation as compared to the others of the RF band circuits 110 , 120 , and 130 .
- the first RF band circuit 110 may be designed to operate at a lower RF band than the second RF band circuit 120 .
- each of the devices 112 , 122 , 132 may be designed (e.g., optimized) to operate at the RF band, the electrical domain of operation, or a combination thereof, corresponding to the RF band circuit 110 , 120 , 130 that includes the device 112 , 122 , or 132 .
- Each of the devices 112 , 122 , 132 may be configured with a different value of a same characteristic (e.g., a characteristic type), such as described further with reference to FIGS. 2A-B .
- the devices 112 , 122 , 132 may have different values of an oxide thickness (e.g., a gate oxide thickness), different values associated with a lightly doped region profile, different values associated with a halo profile, or a combination thereof.
- the first device 112 may have a first oxide thickness
- the second device 122 may have a second oxide thickness different from the first oxide thickness
- the Nth device 132 may have a third oxide thickness that is different from the first oxide thickness and the second oxide thickness.
- the additional circuitry 140 may be coupled to each of the RF band circuits 110 , 120 , 130 .
- the additional circuitry 140 may be configured to operate the device 100 in different modes, such as different combinations of frequency bands.
- the additional circuitry 140 may be configured to select one or more of the RF band circuits 110 , 120 , 130 of the device 100 for operation based on particular circumstances.
- the additional circuitry 140 may determine or receive an indication (e.g., from a processor or positioning system of the device 100 ) of the geographic location in which the device 100 is located. Based on the geographic location, the additional circuitry 140 may selectively activate (e.g., enable to operate) or deactivate one or more of the RF band circuits 110 , 120 , 130 . Alternatively, one or more of the RF band circuits 110 , 120 , 130 may be selected for operation based on other criteria, such as programmable settings.
- the additional circuitry 140 may determine that the device 100 is located in North America, which uses 700/800 MHz frequency bands and 1,700/1,900 MHz frequency bands. Based on the device 100 being located in North America, the additional circuitry 140 may selectively activate, deactivate, or a combination thereof, one or more of the RF band circuits 110 , 120 , 130 to enable the device 100 to operate at the 700/800 MHz frequency bands and the 1,700/1,900 MHz frequency bands. After the device 100 is configured to operate in North America, the additional circuitry 140 may determine that the device is located in Europe (e.g., if a user of a wireless phone travels from North America to Europe), which uses 800 MHz, 1,800 MHz, and 2,600 MHz frequency bands.
- Europe e.g., if a user of a wireless phone travels from North America to Europe
- the additional circuitry 140 may selectively activate, deactivate, or a combination thereof, one or more of the RF band circuits 110 , 120 , 130 to enable the device 100 to operate at the 800 MHz, 1,800 MHz, and 2,600 MHz frequency bands.
- the die 102 of device 100 may advantageously include multiple RF band circuits 110 , 120 , 130 that are each designed for performance and reliability at a corresponding frequency band.
- the device 100 may have a smaller form factor and may be produced at a reduced cost as compared to using multiple RF circuits that are constructed on multiple dies.
- CMOS complementary metal-oxide-semiconductor
- the CMOS devices may include a silicon on insulator (SOI) CMOS device, a silicon on silicon (SOS) CMOS device, or a bulk silicon CMOS device.
- FIG. 2A illustrates a first CMOS device 200 that is a silicon on insulator (SOI) CMOS device.
- FIG. 2B illustrates a second CMOS device 290 that is a bulk silicon CMOS device.
- One or more dies, such as the die 102 of FIG. 1 may be created from the first CMOS device 200 or the second CMOS device 290 .
- the first CMOS device 200 includes a wafer 202 onto which a first device 240 and a second device 260 are formed.
- the first device 240 may be associated with a first radio frequency (RF) band and the second device 260 may be associated with a second RF band.
- the first device 240 and the second device 260 may each correspond to a different one of the devices 112 , 122 , 132 of FIG. 1 .
- each of the first device 240 and the second device 260 is illustrated as a single transistor for ease of explanation, the first device 240 and the second device 260 are not limited to a single transistor.
- each of the first device 240 and the second device 260 may be a same device type, such as a power amplifier, an antenna switch, or a low noise amplifier, and may be constructed during a single front end process flow.
- Each of the first device 240 and the second device 260 may be designed to operate at a different RF band and within a corresponding electrical domain of operation.
- a dashed line 224 illustrates a representative logical division of the first CMOS device 200 into a first portion and a second portion.
- the first CMOS device 200 depicts two devices 240 , 260 , the first CMOS device 200 may include more than two devices.
- the first CMOS device 200 may include a substrate 204 , an insulator material 206 (e.g., a dielectric insulator), and a semiconducting layer 208 (e.g., a semiconductor layer, such as a silicon (Si) layer).
- the substrate 204 includes silicon (Si)
- the insulator material 206 may include a buried oxide (BOX)
- the semiconducting layer 208 may include silicon (Si).
- the substrate 204 , the insulator material 206 , and the semiconducting layer 208 are included in the wafer 202 .
- the insulator material 206 , the semiconducting layer 208 , or a combination thereof, may include a first region 241 corresponding to the first device 240 and a second region 261 corresponding to the second device 260 .
- the insulator material 206 of the first region 241 may have a first insulator material thickness t I1 and the insulator material 206 of the second region 261 may have a second insulator material thickness t I2 .
- the first insulator material thickness t I1 and the second insulator material thickness t I2 may be the same thickness or different thicknesses.
- the semiconducting layer 208 of the first region 241 may have a first semiconducting layer thickness t Si1 and the semiconducting layer 208 of the second region 261 may have a second semiconducting layer thickness t Si2 .
- the first semiconducting layer thickness t Si1 and the second semiconducting layer thickness t Si2 may be the same thickness or different thicknesses.
- the first region 241 and the second region 261 may be separated by a shallow trench isolation (STI) region 222 .
- Each of the first region 241 and the second region 261 may include source/drain (S/D) implants 210 and a well region 212 .
- S/D implant 210 of the first device 240 and either S/D implant 210 of the second device 260 may be associated with a source or associated with a drain of the corresponding transistor, as long as the first device 240 has a source and a drain and the second device 260 has a source and a drain.
- the first device 240 may include a first gate 242 and a first gate oxide 244 .
- the first gate 242 and the first gate oxide 244 may be positioned above a first channel region of the semiconducting layer 208 of the first region 241 .
- the first gate 242 may define a first channel length L g1 , and the first gate oxide 244 may have a height h 1 (e.g., a first gate oxide thickness).
- the first gate 242 , the first gate oxide 244 , or a combination thereof, may have first spacers 250 attached thereto.
- the first spacers 250 may be formed on the first gate 242 .
- the first spacers 250 may have a first spacer thickness t S1 and a first spacer profile (e.g., a volume, a cross sectional area, or a cross sectional shape).
- the first device 240 may further include a first lightly doped region 246 (e.g., a lightly doped implant) and a first halo region 248 (e.g., a halo implant).
- the first lightly doped region 246 and the first halo region 248 may be included within the well region 212 of the first region 241 .
- the first lightly doped region 246 may include a first lightly doped characteristic.
- the first lightly doped characteristic may include a first lightly doped profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the first lightly doped region 246 ), a first lightly doped dopant type, a first lightly doped dopant concentration, or a combination thereof.
- the first halo region 248 may include a first halo characteristic.
- the first halo characteristic may include a first halo profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the first halo region 248 ), a first halo dopant type, a first halo dopant concentration, or a combination thereof.
- the second device 260 may include a second gate 262 and a second gate oxide 264 .
- the second gate 262 and the second gate oxide 264 may be positioned above a second channel region of the semiconducting layer 208 of the second region 261 .
- the second gate 262 may define a second channel length L g2 , and the second gate oxide 264 may have a height h 2 (e.g., a second gate oxide thickness).
- the second gate 262 , the second gate oxide 264 , or a combination thereof, may have second spacers 270 attached thereto.
- the second spacers 270 may be formed on the second gate 262 .
- the second spacers 270 may have a second spacer thickness t S2 and a second spacer profile (e.g., a volume, a cross sectional area, or a cross sectional shape).
- the second device 260 may further include a second lightly doped region 266 and a second halo region 268 .
- the second lightly doped region 266 and the second halo region 268 may be included within the well region 212 of the second region 261 .
- the second lightly doped region 266 may include a second lightly doped characteristic.
- the second lightly doped characteristic may include a second lightly doped profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the second lightly doped region 266 ), a second lightly doped dopant type, a second lightly doped dopant concentration, or a combination thereof.
- the second halo region 268 may include a second halo characteristic.
- the second halo characteristic may include a second halo profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the second halo region 268 ), a second halo dopant type, a second halo dopant concentration, or a combination thereof.
- Values of one or more characteristics of the first device 240 and the second device 260 may differ based on the corresponding frequency band of the first device 240 and the second device 260 .
- the first channel length L g1 of the first gate 242 may be the same length or a different length than the second channel length L g2 of the second gate 262 .
- the height h 1 of the first gate oxide 244 may be the same height or a different height as the height h 2 of the second gate oxide 264 .
- the first spacer thickness t S1 of the first spacers 250 may be the same thickness or a different thickness than the second spacer thickness t S2 of the second spacers 270 .
- a value of the first lightly doped characteristic of the first lightly doped region 246 may be the same as or different than a corresponding value of the second lightly doped characteristic of the second lightly doped region 266 .
- a value of the first halo characteristic of the first halo region 248 may be the same as or different than a corresponding value of the second halo characteristic of the second halo region 268 .
- the second CMOS device 290 includes a wafer 292 onto which the first device 240 and the second device 260 are formed.
- the wafer 292 may include a substrate 294 , such as silicon.
- the substrate 294 may include a first region 241 corresponding to the first device 240 and a second region 261 corresponding to the second device 260 .
- the substrate 294 may include the STI regions 222 , the S/D implants 210 , the first lightly doped region 246 , the first halo region 248 , the second lightly doped regions 266 , and the second halo region 268 .
- the first device 240 and the second device 260 are a same device type, and each of first device 240 and the second device 260 is designed to operate at a different RF band and within a different corresponding electrical domain of operation.
- the first device 240 may be designed to operate at a lower RF band than the second device 260 .
- the first device 240 may be referred to as a low band device
- the second device 260 may be referred to as a high band device.
- the first device 240 is a low band power amplifier
- the second device 260 is a high band power amplifier.
- one or more attributes e.g., one or more characteristic values
- the first insulator material thickness t I1 may be thicker than the second insulator material thickness t I2 .
- the first semiconducting layer thickness t Si1 may be thicker than the second semiconducting layer thickness t Si12 .
- the first channel length L g1 of the first gate 242 may be longer than the second channel length L g2 of the second gate 262 .
- the height h 1 of the first gate oxide 244 may be larger (e.g., thicker) than the height h 2 of the second gate oxide 264 .
- the first spacer thickness t S1 of the first spacers 250 may be thicker than the second spacer thickness t S2 of the second spacers 270 .
- a first cross sectional area of the first spacer profile of the first spacers 250 may be larger than a second cross sectional area of the second spacer profile of the second spacers 270 .
- a first cross sectional area of the first lightly doped profile of the first lightly doped region 246 may be larger than a second cross sectional area of the second lightly doped profile of the second lightly doped region 266 .
- the first lightly doped dopant type of the first lightly doped region 246 may be a first lightly doped dopant having a larger molecular mass (e.g., molecular weight) than a second lightly doped dopant of the second lightly doped dopant type of the second lightly doped region 266 .
- the first lightly doped dopant concentration of the first lightly doped region 246 may be a greater dopant concentration (e.g., a doping concentration) than the second lightly doped dopant concentration of the second lightly doped region 266 .
- a first cross sectional area of the first halo profile of the first halo region 248 may be larger than a second cross sectional area of the second halo profile of the second halo region 268 .
- the first halo dopant type of the first halo region 248 may be a first halo dopant having a larger molecular mass (e.g., molecular weight) than a second halo dopant of the second halo dopant type of the second halo region 268 .
- the first halo dopant concentration (e.g., a doping concentration) of the first halo region 248 may be a greater dopant concentration than the second halo dopant concentration of the second halo region 268 .
- One or more of the examples described above may be incorporated in or otherwise utilized by the first CMOS device 200 of FIG. 2A or the second CMOS device 290 of FIG. 2B based on the RF bands for the first region 241 and the second region 261 .
- a single die of the first CMOS device 200 of FIG. 2A or the second CMOS device 290 of FIG. 2B may advantageously include multiple RF devices that are each designed for performance and reliability at a corresponding frequency band.
- the first CMOS device 200 of FIG. 2A or the second CMOS device 290 of FIG. 2B may have a smaller form factor and may be produced at a reduced cost as compared to RF circuits that are constructed on separate wafers or separate chips. Examples of forming/fabricating a semiconductor device, such as the first CMOS device 200 of FIG. 2A or the second CMOS device 290 of FIG. 2B , are described with reference to FIGS. 3-5 .
- the single die may be formed by a complementary metal-oxide-semiconductor (CMOS) process performed on a wafer.
- CMOS complementary metal-oxide-semiconductor
- the single die may include the die 102 of FIG. 1 , a die of the first CMOS device 200 of FIG. 2A , or a die of the second CMOS device 290 of FIG. 2B .
- a first radio frequency (RF) device of a first RF circuit is formed, at 302 .
- the first RF device has a first device type (e.g., first component type) and a first value of a characteristic.
- the first RF circuit is designed to operate at a first RF band.
- the first RF device may correspond to or be associated with one of the devices 112 , 122 , 132 of FIG. 1 or one of the first device 240 or the second device 260 of FIGS. 2A-B .
- a second RF device of a second RF circuit is formed, at 304 .
- the second RF device has a second device type (e.g., a second component type) and a second value of the characteristic.
- the second RF device may correspond to or be associated with one of the devices 112 , 122 , 132 of FIG. 1 or one of the first device 240 or the second device 260 of FIGS. 2A-B .
- the second RF circuit is designed to operate at a second RF band.
- the first device type and the second device type are a same device type (e.g., a same component type).
- the first value of the characteristic is different than the second value of the characteristic.
- the first RF circuit and the second RF circuit are formed by a complementary metal-oxide-semiconductor (CMOS) process performed on a wafer, such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer.
- CMOS complementary metal-oxide-semiconductor
- the first device and the second device are designed to operate at different RF bands.
- the first device may be designed to operate at a first frequency band
- the second device may be designed to operate at a second frequency band.
- the first frequency band is a lower frequency band than the second frequency band.
- Each device may be configured based on a corresponding frequency band by adjusting one or more parameters (e.g., one or more characteristic values) of the device, such as a channel length, a gate oxide thickness, a lightly doped region profile volume or cross sectional area, a halo region profile volume or cross sectional area, a silicon layer thickness, a buried oxide layer thickness, or a spacer thickness during the CMOS process, as described further with reference to FIGS. 4 and 5 .
- one or more parameters e.g., one or more characteristic values
- the single die may include the die 102 of FIG. 1 , a die of the first CMOS device 200 of FIG. 2A , or a die of the second CMOS device 290 of FIG. 2B .
- First processing is performed on a first region and a second region, at 402 .
- the first processing may be configured to construct (e.g., fabricate) a first device to operate at a first RF band and to construct a second device to operate at a second RF band.
- the first device and the second device may each be associated with a different one of the devices 112 , 122 , 132 of FIG. 1 or the first device 240 and the second device 260 of FIGS. 2A-B .
- the first processing may include forming a first gate oxide on the die, at 404 , and the first processing may include performing second processing to form a second gate oxide on the second region, at 406 .
- the first gate oxide may be formed on the first region (e.g., the first region 241 of FIGS. 2A-B ) and on the second region (e.g., the second region 261 of FIGS. 2A-B ).
- the second processing may include performing thin gate lithography to cover (e.g., protect) the first gate oxide in the first region and to expose (e.g., leave uncovered) the first gate oxide on the second region, removing the first gate oxide from the second region, and forming the second gate oxide on the second region (e.g., the second gate oxide 264 in the second region 261 ).
- the second gate oxide may have a different thickness than the first gate oxide.
- the first gate oxide may be thicker than the second gate oxide.
- the second processing may include performing thin gate lithography to cover (e.g., protect) the first gate oxide in the first region and to expose (e.g., leave uncovered) the first gate oxide on the second region and forming the second gate oxide on the second region by adding additional gate oxide material to the first gate oxide in the first region.
- First gate material of a first device may be formed on the first region, and second gate material of a second device may be formed on the second region, at 408 .
- polysilicon may be formed over the gate oxide in both regions in a common depositing/lithography/etching process.
- the first device may correspond to one of the first device 112 , the second device 122 , and the Nth device 132 of FIG. 1 , or the first device 240 and the second device 260 of FIGS. 2A-B
- the second device may correspond to another one of the first device 112 , the second device 122 , and the Nth device 132 of FIG. 1 , or the first device 240 and the second device 260 of FIGS. 2A-B .
- the first device and the second device may each be designed to operate at different radio frequency bands.
- the first device may correspond to a first radio frequency (RF) band
- the second device may correspond to a second RF band that is different from the first RF band.
- the first device is a first power amplifier and the second device is a second power amplifier.
- a third illustrative embodiment of a method to form a single die that accommodates multiple RF bands is illustrated and designated 500 .
- the single die may include the die 102 of FIG. 1 .
- the method may include a complementary metal-oxide-semiconductor (CMOS) process.
- CMOS complementary metal-oxide-semiconductor
- the wafer such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer, may include a first region and a second region, such as the first region 241 and the second region 261 of FIGS. 2A-B .
- the first region may be associated with a first device designed to operate at a first RF band
- the second region may be associated with a second device designed to operate at a second RF band.
- the first device may correspond to one of the first device 112 , the second device 122 , and the Nth device 132 , of FIG.
- the first device and the second device may each be designed to operate at different radio frequency bands.
- the first device is a first power amplifier
- the second device is a second power amplifier.
- the wafer may include the wafer 202 of FIG.
- the common processing may include forming shallow trench isolation regions, p well regions, n well regions, one or more other semiconductor process components, or a combination thereof.
- Wafer processing may be performed on the wafer prior to performing the common processing.
- the wafer processing may include configuring a first thickness of the silicon layer of the first region to be thicker than a second thickness of the silicon layer of the second region when the first device is designed to operate at a lower RF band than the second device.
- the wafer processing may include configuring a first thickness of the buried oxide layer of the first region to be thicker than a second thickness of the buried oxide layer of the second region.
- a first gate oxide may be formed on the first region, and a second gate oxide may be formed on the second region, at 504 .
- the first gate oxide and the second gate oxide may have a same or a different thickness.
- the first oxide e.g., a thickness of the first oxide
- the second oxide e.g., a thickness of the second oxide
- the first gate oxide and the second gate oxide may be formed according to at least a portion of the method 400 of FIG. 4 .
- First gate material of the first device may be formed on the first region, and second gate material of the second device may be formed on the second region, at 508 .
- first gate material and the second gate material may be formed during a common gate formation process performed on the first region and the second region.
- Processing is performed on a first region and a second region, at 510 .
- the processing may construct (e.g., fabricate) the first device to operate at the first RF band and to construct the second device to operate at the second RF band.
- the processing may include performing first processing on the first region, at 512 , and performing second processing on the second region, at 514 .
- the first processing and the second processing may correspond to a same characteristic type of the first device and the second device.
- the characteristic type may include a channel length, a gate oxide thickness, a lightly doped region characteristic, a halo region characteristic, or a combination thereof.
- a first value of the characteristic type of the first device may be different than a second value of the characteristic type of the second device.
- a first channel length of the first device may be longer than a second channel length of the second device
- a first gate oxide thickness of the first device may be thicker than a second gate oxide thickness of the second device
- a first lightly doped region characteristic e.g., a profile volume, a profile cross sectional area, a profile cross sectional shape, a dopant concentration, or a dopant type
- a first halo region characteristic e.g., a profile volume, a profile cross sectional area, a profile cross sectional shape, a dopant concentration, or a dopant type
- Second common processing may be performed on the first region and the second region, at 516 .
- the second common processing may include forming spacers, forming n source/drain implants, p source/drain implants, silicides, contacts, metal 1 layers, vias, metal 2 layers, or a combination thereof.
- the method 300 of FIG. 3 , the method 400 of FIG. 4 , the method 500 of FIG. 5 , or any combination thereof, may be initiated or controlled by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit, such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, a firmware device, or any combination thereof.
- FPGA field-programmable gate array
- ASIC application-specific integrated circuit
- processing unit such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, a firmware device, or any combination thereof.
- the method 300 of FIG. 3 , the method 400 of FIG. 4 , or the method 500 of FIG. 5 can be initiated or controlled by one or more processors, operating systems, or controllers.
- FIG. 6 a block diagram of a particular illustrative embodiment of a wireless communication device 600 is depicted.
- the device 600 may include, or have incorporated therein, the die 102 of FIG. 1 .
- the device 600 includes a processor 610 , such as a digital signal processor (DSP), coupled to a memory 632 .
- the memory 632 includes instructions 668 (e.g., executable instructions) such as computer-readable instructions that are readable by the processor 610 .
- the instructions 668 may include one or more instructions that are executable by a computer, such as the processor 610 .
- FIG. 6 also shows a display controller 626 that is coupled to the processor 610 and to a display 628 .
- a coder/decoder (CODEC) 634 can also be coupled to the processor 610 .
- a speaker 636 and a microphone 638 can be coupled to the CODEC 634 .
- FIG. 6 also indicates that a wireless interface 640 can be coupled to the processor 610 and to an antenna 642 .
- the wireless interface 640 may include a wireless controller, a wireless transceiver, such as a receiver circuit, a transmitter circuit, or a combination thereof.
- the wireless interface 640 may include a device 664 , such as the die 102 of FIG. 1 .
- the device 664 may include a first radio frequency (RF) component and a second RF component, such as the first device 112 and the second device 122 of FIG. 1 .
- the first RF component and the second RF component may each include a power amplifier, an antenna switch, a low noise amplifier, or one or more transistors.
- the first RF component and the second RF component may be included in a receiver circuit, a transmitter circuit, or a combination thereof.
- the device 664 may be a chip (e.g., a single chip) configured to accommodate multiple radio frequency (RF) bands.
- the device 664 may be located in one or more components of the device 600 other than in the wireless interface 640 .
- the processor 610 , the display controller 626 , the memory 632 , the CODEC 634 , and the wireless interface 640 are included in a system-in-package or system-on-chip device 622 .
- an input device 630 and a power supply 644 are coupled to the system-on-chip device 622 .
- the display 628 , the input device 630 , the speaker 636 , the microphone 638 , the wireless antenna 642 , and the power supply 644 are external to the system-on-chip device 622 .
- each of the display 628 , the input device 630 , the speaker 636 , the microphone 638 , the antenna 642 , and the power supply 644 can be coupled to a component of the system-on-chip device 622 , such as an interface or a controller.
- One or more of the disclosed embodiments may be implemented in a system or an apparatus, such as the device 600 , that may include a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a satellite phone, a computer, a tablet, a portable computer, or a desktop computer.
- the device 600 may include a set top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, a portable digital video player, any other device that stores or retrieves data or computer instructions, or a combination thereof.
- PDA personal digital assistant
- DVD digital video disc
- the system or the apparatus may include remote units, such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
- remote units such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
- FIG. 7 depicts a particular illustrative embodiment of an electronic device manufacturing process 700 .
- Physical device information 702 is received at the manufacturing process 700 , such as at a research computer 706 .
- the physical device information 702 may include design information representing at least one physical property of a semiconductor device, such as a semiconductor device including the die 102 of FIG. 1 .
- the physical device information 702 may include physical parameters, material characteristics, and structure information that is entered via a user interface 704 coupled to the research computer 706 .
- the research computer 706 includes a processor 708 , such as one or more processing cores, coupled to a computer-readable medium such as a memory 710 .
- the memory 710 may store computer-readable instructions that are executable to cause the processor 708 to transform the physical device information 702 to comply with a file format and to generate a library file 712 .
- the library file 712 includes at least one data file including the transformed design information.
- the library file 712 may include a library of semiconductor devices including a device that includes the die 102 of FIG. 1 , that is provided to use with an electronic design automation (EDA) tool 720 .
- EDA electronic design automation
- the library file 712 may be used in conjunction with the EDA tool 720 at a design computer 714 including a processor 716 , such as one or more processing cores, coupled to a memory 718 .
- the EDA tool 720 may be stored as processor-executable instructions at the memory 718 to enable a user of the design computer 714 to design a circuit including the die 102 of FIG. 1 , of the library file 712 .
- a user of the design computer 714 may enter circuit design information 722 via a user interface 724 coupled to the design computer 714 .
- the circuit design information 722 may include design information representing at least one physical property of a semiconductor device, such as a semiconductor device that includes the die 102 of FIG. 1 .
- the circuit design property may include identification of particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a semiconductor device.
- the design computer 714 may be configured to transform the design information, including the circuit design information 722 , to comply with a file format.
- the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format (e.g., a GDSII format).
- the design computer 714 may be configured to generate a data file including the transformed design information, such as a GDSII file 726 that includes information describing the die 102 of FIG. 1 , in addition to other circuits or information.
- the data file may include information corresponding to a system-on-chip (SOC) that includes the die 102 of FIG. 1 , and that may also include additional electronic circuits and components within the SOC.
- SOC system-on-chip
- the GDSII file 726 may be received at a fabrication process 728 to manufacture a wafer including the die 102 of FIG. 1 , according to transformed information in the GDSII file 726 .
- a device manufacture process may include providing the GDSII file 726 to a mask manufacturer 730 to create one or more masks, such as masks to be used with photolithography processing, illustrated as a representative mask 732 .
- the mask 732 may be used during the fabrication process to generate one or more wafers 734 , such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer.
- the wafers 734 may correspond to the wafer 202 of FIG. 2A or the wafer 292 of FIG. 2B , which may be tested and separated into dies, such as a representative die 736 .
- the die 736 may include or correspond to the die 102 of FIG. 1 .
- the fabrication process 728 is implemented by a computer including a processor 731 and a memory 733 .
- the memory 733 e.g., a non-transitory computer-readable medium
- the computer-executable instructions may be executable to cause the processor 731 to initiate formation of a complementary metal-oxide-semiconductor (CMOS) device.
- CMOS complementary metal-oxide-semiconductor
- the formation of the CMOS device includes forming a first gate oxide in a first region and in a second region of a wafer, such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer.
- the CMOS device is further formed by performing first processing to form a second gate oxide in the second region.
- the second gate oxide has a different thickness than the first gate oxide.
- the formation of the CMOS device also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region.
- the first device corresponds to (e.g., is configured to operate in) a first radio frequency (RF) band
- the second device corresponds to (e.g., is configured to operate in) a second RF band that is different from the first RF band.
- RF radio frequency
- the computer-executable instructions may be executable to cause the processor 731 to initiate performing a complementary metal-oxide-semiconductor (CMOS) process to form a first radio frequency (RF) circuit and a second RF circuit.
- CMOS complementary metal-oxide-semiconductor
- the first RF circuit is designed to operate at a first RF band
- the second RF circuit is designed to operate at a second RF band that is different from the first RF band.
- the CMOS process includes forming a first RF device of the first RF circuit and forming a second RF device of the second RF circuit.
- the first RF device has a first device type and a first value of a characteristic
- the second RF device has a second device type and a second value of the characteristic.
- the first device type and the second device type are a same device type, and the first value of the characteristic is different from the second value of the characteristic.
- the die 736 may be provided to a packaging process 738 where the die 736 is incorporated into a representative package 740 .
- the package 740 may include the single die 736 or multiple dies, such as a system-in-package (SiP) arrangement.
- the package 740 may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.
- JEDEC Joint Electron Device Engineering Council
- Information regarding the package 740 may be distributed to various product designers, such as via a component library stored at a computer 746 .
- the computer 746 may include a processor 748 , such as one or more processing cores, coupled to a memory 750 .
- a printed circuit board (PCB) tool may be stored as processor-executable instructions at the memory 750 to process PCB design information 742 received from a user of the computer 746 via a user interface 744 .
- the PCB design information 742 may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to the package 740 including the die 102 of FIG. 1 .
- the computer 746 may be configured to transform the PCB design information 742 to generate a data file, such as a GERBER file 752 with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package 740 including the die 102 of FIG. 1 .
- a data file such as a GERBER file 752 with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package 740 including the die 102 of FIG. 1 .
- the data file generated by the transformed PCB design information may have a format other than a GERBER format.
- the GERBER file 752 may be received at a board assembly process 754 and used to create PCBs, such as a representative PCB 756 , manufactured in accordance with the design information stored within the GERBER file 752 .
- the GERBER file 752 may be uploaded to one or more machines to perform various steps of a PCB production process.
- the PCB 756 may be populated with electronic components including the package 740 to form a representative printed circuit assembly (PCA) 758 .
- PCA printed circuit assembly
- the PCA 758 may be received at a product manufacture process 760 and integrated into one or more electronic devices, such as a first representative electronic device 762 and a second representative electronic device 764 .
- the first representative electronic device 762 , the second representative electronic device 764 , or both may be selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the die 102 of FIG. 1 is integrated.
- PDA personal digital assistant
- one or more of the electronic devices 762 and 764 may be remote units such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
- PCS personal communication systems
- GPS global positioning system
- FIG. 7 illustrates remote units according to teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units.
- Embodiments of the disclosure may be suitably employed in any device which includes active integrated circuitry including memory and on-chip circuitry.
- a device that includes the die 102 of FIG. 1 may be fabricated, processed, and incorporated into an electronic device, as described in the illustrative process 700 .
- One or more aspects of the embodiments disclosed with respect to FIGS. 1-6 may be included at various processing stages, such as within the library file 712 , the GDSII file 726 , and the GERBER file 752 , as well as stored at the memory 710 of the research computer 706 , the memory 718 of the design computer 714 , the memory 733 of a computer associated with the fabrication process 728 , the memory 750 of the computer 746 , the memory of one or more other computers or processors (not shown) used at the various stages, such as at the board assembly process 754 , and also incorporated into one or more other physical embodiments such as the mask 732 , the die 736 , the package 740 , the PCA 758 , other products such as prototype circuits or devices (not shown), or any combination thereof.
- process 700 may be performed by a single entity or by one or more entities performing various stages of the process 700 .
- an apparatus may include a first radio frequency (RF) component corresponding to (e.g., configured to operate in) a first RF band, and a second RF component corresponding to (e.g., configured to operate in) a second RF band that is different from the first RF band.
- the first RF component may include first means for gating a first channel.
- the first means for gating may correspond to the first gate 242 or the second gate 262 of FIGS. 2A-B , one or more other devices or circuits configured to gate the first channel, or any combination thereof.
- the first channel may be positioned between first means for sourcing first current to the first channel and first means for draining the first current from the first channel.
- the first means for sourcing may correspond to one of the S/D implants 210 of FIGS. 2A-B , one or more other devices or circuits configured to source the first current to the first channel, or any combination thereof.
- the first means for draining may correspond to another of the S/D implants 210 of FIGS. 2A-B , one or more other devices or circuits configured to drain the first current from the first channel, or any combination thereof.
- the first means for gating the first channel is insulated from first semiconductor means for conducting first charge carriers by a first insulator.
- the first semiconductor means for conducting may correspond to the semiconducting layer 208 of FIG. 2A , the substrate 294 of FIG. 2B , one or more other devices or circuits configured to conduct the first charge carriers, or any combination thereof.
- the first insulator may correspond to the insulator material 206 of FIG. 2A , one or more other materials configured to insulate the first means for gating from the first semiconductor means for conducting, or any combination thereof.
- the second RF component of the apparatus may include second means for gating a second channel.
- the second means for gating may correspond to the first gate 242 or the second gate 262 of FIGS. 2A-B , one or more other devices or circuits configured to gate the second channel, or any combination thereof.
- the second channel may be positioned between second means for sourcing second current to the second channel and second means for draining the second current from the second channel.
- the second means for sourcing may correspond to the S/D implants 210 of FIGS. 2A-B , one or more other devices or circuits configured to source the second current to the second channel, or any combination thereof.
- the second means for draining may correspond to the S/D implants 210 of FIGS.
- the second means for gating the second channel is insulated from the second semiconductor means for conducting first charge carriers by a second insulator.
- the second semiconductor means for conducting may correspond to the semiconducting layer 208 of FIG. 2A , the substrate 294 of FIG. 2B , one or more other devices or circuits configured to conduct the second charge carriers, or any combination thereof.
- the second insulator may correspond to the insulator material 206 of FIG. 2A , one or more other materials circuits configured to insulate the second means for gating from the second semiconductor means for conducting, or any combination thereof.
- a first thickness of the first insulator is different than a second thickness of the second insulator.
- a method may include a step for forming a first gate oxide in a first region and in a second region of a wafer, such as described in the method 300 of FIG. 3 at 302 , the method 400 of FIG. 4 at 402 , 404 , described in the method 500 of FIG. 5 at 504 , a deposition process, a lithography process, an etch process, one or more other processes configured to form the first gate oxide in the first region and in the second region of the wafer, or any combination thereof.
- the method may also include a step for performing first processing to form a second gate oxide in the second region, such as described in the method 300 of FIG. 3 at 304 , the method 400 of FIG.
- the method may also include a step forming first gate material of a first device in the first region and forming second gate material of a second device in the second region, such as the as described in the method 300 of FIG. 3 at 302 , 304 , the method 400 of FIG. 4 at 408 , described in the method 500 of FIG.
- the first device corresponds to a first radio frequency (RF) band
- the second device corresponds to a second RF band that is different from the first RF band.
- RF radio frequency
- FIGS. 1-7 may illustrate systems, apparatuses, and/or methods according to the teachings of the disclosure, the disclosure is not limited to these illustrated systems, apparatuses, and/or methods.
- Embodiments of the disclosure may be suitably employed in any device that includes integrated circuitry including memory, a processor, and on-chip circuitry.
- a software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transient storage medium known in the art.
- An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
- the storage medium may be integral to the processor.
- the processor and the storage medium may reside in an application-specific integrated circuit (ASIC).
- ASIC application-specific integrated circuit
- the ASIC may reside in a computing device or a user terminal.
- the processor and the storage medium may reside as discrete components in a computing device or user terminal.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A device includes a first radio frequency (RF) component on a die. The first RF component includes a first lightly doped region having a first value of a characteristic, and the first RF component is configured to operate in a first RF band associated with a first frequency. The device further includes a second RF component on the die. The second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value. The second RF component is configured to operate in a second RF band associated with a second frequency that is different from the first frequency.
Description
- The present application claims priority from and is a divisional application of U.S. patent application Ser. No. 13/958,646 filed Aug. 5, 2013, entitled “METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIO FREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS ON A CHIP,” the content of which is incorporated by reference herein in its entirety.
- The present disclosure is generally related methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip.
- Advances in technology have resulted in smaller and apparatuses more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and internet protocol (IP) telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.
- Long-term evolution (LTE) (e.g., 4G LTE) is a standard for wireless communication for high-speed data. The LTE standard specifies multiple frequency bands (e.g., multiple radio frequency (RF) bands) ranging from 0.7 gigahertz (GHz) to 2.6 GHz based on geographic region. For example, devices in North America will use 700/800 megahertz (MHz) frequency bands and 1,700/1,900 MHz frequency bands, and devices in Europe will use 800 MHz, 1,800 MHz, and 2,600 MHz frequency bands. Accordingly, for a wireless device to be compatible with multiple geographic regions, the wireless device must operate at each of the frequency bands. Additionally, the wireless device should be backwards compatible with prior standards (e.g., global system for mobile communication (GSM) standards, universal mobile telecommunications system (UMTS) standards, and wireless local area network (WLAN) standards).
- To operate at multiple frequency bands, the wireless device includes multiple RF components that are each configured to operate (meet performance and reliability criteria) at a corresponding frequency band of the multiple frequency bands. For example, to operate in Europe, the wireless device includes a first power amplifier (PA) configured to operate in the 800 MHz frequency band, a second PA configured to operate in the 1,800 MHz frequency band, and a third PA configured to operate in the 2,600 MHz frequency band.
- Each RF component for a particular frequency band is typically provided on a single chip, such as a chip formed using gallium arsenide (GaAs) or indium gallium phosphide (InGaP) chips. Accordingly, the wireless device includes multiple chips, each with different frequency-band-specific devices, to operate at multiple frequency bands. The use of multiple chips is expensive, requires a large footprint (e.g., printed circuit (PC) board area), and increases a size of the wireless device.
- The present disclosure provides methods of performing a complementary metal-oxide-semiconductor (CMOS) process on a wafer (e.g., a die) to form multiple radio frequency (RF) circuits (e.g., a first RF circuit and a second RF circuit) that each operate at different RF bands. For example, the wafer may include a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer. Each of the RF circuits may include a receiver, a transmitter, or a combination thereof. For example, a first RF circuit may be designed to operate at a first RF band, and a second RF circuit may be designed to operate at a second RF band. The CMOS process may include forming, on the first RF circuit, a first RF device having a first device type and a first characteristic and forming a second RF device having a second device type and a second characteristic on the second RF circuit. The first RF device and the second RF device are the same type of device (i.e., have a same device type), such as a power amplifier, an antenna switch, or a low noise amplifier. Additionally, the first characteristic and the second characteristic are the same type of characteristic (i.e., same characteristic type), such as an oxide thickness, a lightly doped region profile, or a halo profile. However, a value of the first characteristic is different than a value of the second characteristic. For example, when the characteristic type is an oxide thickness, a first oxide thickness of the first device may be thicker than a second oxide thickness of the second device. The value of the first characteristic may be determined to enable the first RF circuit to operate at the first RF band, and the value of the second characteristic may be determined to enable the second RF circuit to operate at the second RF band.
- In a particular embodiment, a method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band, and the second device corresponds to a second RF band that is different from the first RF band.
- In a particular embodiment, a device includes a first radio frequency (RF) component and a second RF component on a die. The first RF component corresponds to a first RF band, and the second RF component corresponds to a second RF band that is different from the first RF band. The first RF component includes a first gate oxide having a first thickness, and the second RF component includes a second gate oxide having a second thickness that is different from the first thickness.
- In a further particular embodiment, an apparatus includes a first radio frequency (RF) component corresponding to a first RF band, and a second RF component corresponding to a second RF band that is different from the first RF band. The first RF component includes first means for gating a first channel. The first channel is positioned between first means for sourcing first current to the first channel and first means for draining the first current from the first channel. The means for gating the channel is isolated from first semiconductor means for conducting first charge carriers by a first insulator. The second RF component includes second means for gating a second channel. The second channel is positioned between second means for sourcing second current to the second channel and second means for draining the second current from the second channel. The second means for gating the second channel is isolated from second semiconductor means for conducting second charge carriers by a second insulator. A first thickness of the first insulator is different than a second thickness of the second insulator.
- In another particular embodiment, a non-transitory computer-readable medium includes instructions that, when executed by a processor, cause the processor to initiate formation of a complementary metal-oxide-semiconductor (CMOS) device. The formation of the CMOS device includes forming a first gate oxide in a first region and in a second region of a wafer. The CMOS device is further formed by performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The formation of the CMOS device also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band, and the second device corresponds to a second RF band that is different from the first RF band.
- In another particular embodiment, a device includes a first radio frequency (RF) component and a second RF component on a die. The first RF component corresponds to a first RF band, and the second RF component corresponds to a second RF band that is different from the first RF band. The first RF component includes a first lightly doped region having a first value of a characteristic, and the second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value.
- In another particular embodiment, a device includes a first radio frequency (RF) component and a second RF component on a die. The first RF component corresponds to a first RF band, and the second RF component corresponds to a second RF band that is different from the first RF band. The first RF component includes a first halo region having a first value of a characteristic, and the second RF component includes a second halo region having a second value of the characteristic that is different from the first value.
- In another particular embodiment, a method includes a first step for forming a first gate oxide in a first region and in a second region of a wafer. The method further includes a second step for performing first processing to form a second gate oxide in the second region, the second gate oxide having a different thickness than the first gate oxide. The method also includes a third step for forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band, and the second device corresponds to a second RF band that is different from the first RF band.
- In another particular embodiment, a method includes performing, on a wafer, a complementary metal-oxide-semiconductor (CMOS) process to form a first radio frequency (RF) circuit and a second RF circuit. The first RF circuit is designed to operate at a first RF band and the second RF circuit is designed to operate at a second RF band. Performing the CMOS process includes forming a first RF device of the first RF circuit and forming a second RF device of the second RF circuit. The first RF device has a first device type and a first value of a characteristic, and the second RF device has a second device type and a second value of the characteristic. The first device type and the second device type are a same device type, and the first value of the characteristic is different from the second value of the characteristic.
- In another particular embodiment, a method includes receiving design information representing at least one physical property of a semiconductor device. The semiconductor device includes a first radio frequency (RF) component and a second RF component on a die. The first RF component corresponds to a first RF band, and the second RF component corresponds to a second RF band that is different from the first RF band. The first RF component includes a first gate oxide having a first thickness, and the second RF component includes a second gate oxide having a second thickness that is different from the first thickness. The method further includes transforming the design information to comply with a file format and generating a data file including the transformed design information.
- One particular advantage provided by at least one of the disclosed embodiments is that a single die may advantageously include multiple RF band circuits that are each designed for performance and reliability at a corresponding frequency band. The die may have a smaller form factor and may be produced at a reduced cost as compared to including a RF circuit on a separate chip for each frequency band.
- Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.
-
FIG. 1 is a block diagram of a first illustrative embodiment of a device having a die that accommodates multiple radio frequency (RF) bands; -
FIGS. 2A-B are block diagrams of illustrative embodiments of complementary metal-oxide-semiconductor (CMOS) devices that accommodate multiple RF bands; -
FIG. 3 is a flow diagram of an illustrative embodiment of a first method to form a die that accommodates multiple RF bands; -
FIG. 4 is a flow diagram of an illustrative embodiment of a second method to form a die that accommodates multiple RF bands; -
FIG. 5 is a flow diagram of an illustrative embodiment of a third method to form a die that accommodates multiple RF bands; -
FIG. 6 is a block diagram of a device including the die ofFIG. 1 ; and -
FIG. 7 is a data flow diagram of an illustrative embodiment of a manufacturing process including the die ofFIG. 1 . - Particular embodiments of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers throughout the drawings.
- Referring to
FIG. 1 , a device 100 (e.g., a communication device) that accommodates multiple radio frequency (RF) bands is shown. Thedevice 100 includes adie 102 having multiple RF circuits, such as a firstRF band circuit 110, a secondRF band circuit 120, an NthRF band circuit 130, andadditional circuitry 140. Thedie 102 may be packaged in (e.g., incorporated in) a chip, such as a semiconductor chip. Although thedie 102 is shown as including theadditional circuitry 140, theadditional circuitry 140 may be coupled to the die 102 but not be included in thedie 102. Thedevice 100 may include a communication device, such as a portable communication device) configured for RF communication. Thedevice 100 may include one or more additional components or circuits (not shown), such as a processor (e.g., a digital signal processor), a wireless transceiver, a memory, an antenna, one or more other components, or a combination thereof. - The
multiple RF circuits additional circuitry 140, or a combination thereof, may be formed by a front end process, such as a front end complementary metal-oxide-semiconductor (CMOS) process. The front end process may be performed with respect to a wafer (e.g., from which thedie 102 is created), as described further herein. As a result of the front end process, thedie 102 includes multiple RF circuits (e.g., the firstRF band circuit 110, the secondRF band circuit 120, the Nth RF band circuit 130), and the additional circuitry 140 (e.g., control circuitry). Although thedie 102 shows three differentRF band circuits die 102 may include two RF band circuits or more than three RF band circuits. - Each of the
RF band circuits RF band circuit 110 may include afirst device 112, the secondRF band circuit 120 may include asecond device 122, and the NthRF band circuit 130 may include anNth device 132. Each of thefirst device 112, thesecond device 122, and the Nth device may be a same device type, such as a power amplifier, an antenna switch, or a low noise amplifier and may be constructed during a single front end process flow. Each of theRF band circuits RF band circuits RF band circuits RF band circuit 110 may be designed to operate at a lower RF band than the secondRF band circuit 120. Accordingly, each of thedevices RF band circuit device devices FIGS. 2A-B . For example, thedevices first device 112 may have a first oxide thickness, thesecond device 122 may have a second oxide thickness different from the first oxide thickness, and theNth device 132 may have a third oxide thickness that is different from the first oxide thickness and the second oxide thickness. - The
additional circuitry 140 may be coupled to each of theRF band circuits additional circuitry 140 may be configured to operate thedevice 100 in different modes, such as different combinations of frequency bands. For example, theadditional circuitry 140 may be configured to select one or more of theRF band circuits device 100 for operation based on particular circumstances. - For example, during operation of the
device 100, theadditional circuitry 140 may determine or receive an indication (e.g., from a processor or positioning system of the device 100) of the geographic location in which thedevice 100 is located. Based on the geographic location, theadditional circuitry 140 may selectively activate (e.g., enable to operate) or deactivate one or more of theRF band circuits RF band circuits - During operation, the
additional circuitry 140 may determine that thedevice 100 is located in North America, which uses 700/800 MHz frequency bands and 1,700/1,900 MHz frequency bands. Based on thedevice 100 being located in North America, theadditional circuitry 140 may selectively activate, deactivate, or a combination thereof, one or more of theRF band circuits device 100 to operate at the 700/800 MHz frequency bands and the 1,700/1,900 MHz frequency bands. After thedevice 100 is configured to operate in North America, theadditional circuitry 140 may determine that the device is located in Europe (e.g., if a user of a wireless phone travels from North America to Europe), which uses 800 MHz, 1,800 MHz, and 2,600 MHz frequency bands. Based on thedevice 100 being located in Europe, theadditional circuitry 140 may selectively activate, deactivate, or a combination thereof, one or more of theRF band circuits device 100 to operate at the 800 MHz, 1,800 MHz, and 2,600 MHz frequency bands. - The die 102 of
device 100 may advantageously include multipleRF band circuits device 100 may have a smaller form factor and may be produced at a reduced cost as compared to using multiple RF circuits that are constructed on multiple dies. - Referring to
FIGS. 2A-B , illustrative embodiments of complementary metal-oxide-semiconductor (CMOS) devices that accommodate multiple RF bands are disclosed. The CMOS devices may include a silicon on insulator (SOI) CMOS device, a silicon on silicon (SOS) CMOS device, or a bulk silicon CMOS device.FIG. 2A illustrates afirst CMOS device 200 that is a silicon on insulator (SOI) CMOS device.FIG. 2B illustrates asecond CMOS device 290 that is a bulk silicon CMOS device. One or more dies, such as thedie 102 ofFIG. 1 , may be created from thefirst CMOS device 200 or thesecond CMOS device 290. - Referring to
FIG. 2A , thefirst CMOS device 200 includes awafer 202 onto which afirst device 240 and asecond device 260 are formed. Thefirst device 240 may be associated with a first radio frequency (RF) band and thesecond device 260 may be associated with a second RF band. For example, thefirst device 240 and thesecond device 260 may each correspond to a different one of thedevices FIG. 1 . Although each of thefirst device 240 and thesecond device 260 is illustrated as a single transistor for ease of explanation, thefirst device 240 and thesecond device 260 are not limited to a single transistor. For example, each of thefirst device 240 and thesecond device 260 may be a same device type, such as a power amplifier, an antenna switch, or a low noise amplifier, and may be constructed during a single front end process flow. Each of thefirst device 240 and thesecond device 260 may be designed to operate at a different RF band and within a corresponding electrical domain of operation. A dashedline 224 illustrates a representative logical division of thefirst CMOS device 200 into a first portion and a second portion. One of skill in the art will appreciate that although thefirst CMOS device 200 depicts twodevices first CMOS device 200 may include more than two devices. - The
first CMOS device 200 may include asubstrate 204, an insulator material 206 (e.g., a dielectric insulator), and a semiconducting layer 208 (e.g., a semiconductor layer, such as a silicon (Si) layer). In a particular embodiment, thesubstrate 204 includes silicon (Si), theinsulator material 206 may include a buried oxide (BOX), and thesemiconducting layer 208 may include silicon (Si). In a particular embodiment, thesubstrate 204, theinsulator material 206, and thesemiconducting layer 208 are included in thewafer 202. - The
insulator material 206, thesemiconducting layer 208, or a combination thereof, may include afirst region 241 corresponding to thefirst device 240 and asecond region 261 corresponding to thesecond device 260. Theinsulator material 206 of thefirst region 241 may have a first insulator material thickness tI1 and theinsulator material 206 of thesecond region 261 may have a second insulator material thickness tI2. The first insulator material thickness tI1 and the second insulator material thickness tI2 may be the same thickness or different thicknesses. Thesemiconducting layer 208 of thefirst region 241 may have a first semiconducting layer thickness tSi1 and thesemiconducting layer 208 of thesecond region 261 may have a second semiconducting layer thickness tSi2. The first semiconducting layer thickness tSi1 and the second semiconducting layer thickness tSi2 may be the same thickness or different thicknesses. - The
first region 241 and thesecond region 261 may be separated by a shallow trench isolation (STI)region 222. Each of thefirst region 241 and thesecond region 261 may include source/drain (S/D)implants 210 and awell region 212. Either S/D implant 210 of thefirst device 240 and either S/D implant 210 of thesecond device 260 may be associated with a source or associated with a drain of the corresponding transistor, as long as thefirst device 240 has a source and a drain and thesecond device 260 has a source and a drain. - The
first device 240 may include afirst gate 242 and afirst gate oxide 244. Thefirst gate 242 and thefirst gate oxide 244 may be positioned above a first channel region of thesemiconducting layer 208 of thefirst region 241. Thefirst gate 242 may define a first channel length Lg1, and thefirst gate oxide 244 may have a height h1 (e.g., a first gate oxide thickness). Thefirst gate 242, thefirst gate oxide 244, or a combination thereof, may havefirst spacers 250 attached thereto. For example, thefirst spacers 250 may be formed on thefirst gate 242. Thefirst spacers 250 may have a first spacer thickness tS1 and a first spacer profile (e.g., a volume, a cross sectional area, or a cross sectional shape). Thefirst device 240 may further include a first lightly doped region 246 (e.g., a lightly doped implant) and a first halo region 248 (e.g., a halo implant). The first lightly dopedregion 246 and thefirst halo region 248 may be included within thewell region 212 of thefirst region 241. The first lightly dopedregion 246 may include a first lightly doped characteristic. The first lightly doped characteristic may include a first lightly doped profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the first lightly doped region 246), a first lightly doped dopant type, a first lightly doped dopant concentration, or a combination thereof. Thefirst halo region 248 may include a first halo characteristic. The first halo characteristic may include a first halo profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the first halo region 248), a first halo dopant type, a first halo dopant concentration, or a combination thereof. - The
second device 260 may include asecond gate 262 and asecond gate oxide 264. Thesecond gate 262 and thesecond gate oxide 264 may be positioned above a second channel region of thesemiconducting layer 208 of thesecond region 261. Thesecond gate 262 may define a second channel length Lg2, and thesecond gate oxide 264 may have a height h2 (e.g., a second gate oxide thickness). Thesecond gate 262, thesecond gate oxide 264, or a combination thereof, may havesecond spacers 270 attached thereto. For example, thesecond spacers 270 may be formed on thesecond gate 262. Thesecond spacers 270 may have a second spacer thickness tS2 and a second spacer profile (e.g., a volume, a cross sectional area, or a cross sectional shape). Thesecond device 260 may further include a second lightly dopedregion 266 and asecond halo region 268. The second lightly dopedregion 266 and thesecond halo region 268 may be included within thewell region 212 of thesecond region 261. The second lightly dopedregion 266 may include a second lightly doped characteristic. The second lightly doped characteristic may include a second lightly doped profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the second lightly doped region 266), a second lightly doped dopant type, a second lightly doped dopant concentration, or a combination thereof. Thesecond halo region 268 may include a second halo characteristic. The second halo characteristic may include a second halo profile (e.g., a volume, a cross sectional area, or a cross sectional shape of the second halo region 268), a second halo dopant type, a second halo dopant concentration, or a combination thereof. - Values of one or more characteristics of the
first device 240 and thesecond device 260 may differ based on the corresponding frequency band of thefirst device 240 and thesecond device 260. For example, the first channel length Lg1 of thefirst gate 242 may be the same length or a different length than the second channel length Lg2 of thesecond gate 262. The height h1 of thefirst gate oxide 244 may be the same height or a different height as the height h2 of thesecond gate oxide 264. The first spacer thickness tS1 of thefirst spacers 250 may be the same thickness or a different thickness than the second spacer thickness tS2 of thesecond spacers 270. A value of the first lightly doped characteristic of the first lightly dopedregion 246 may be the same as or different than a corresponding value of the second lightly doped characteristic of the second lightly dopedregion 266. A value of the first halo characteristic of thefirst halo region 248 may be the same as or different than a corresponding value of the second halo characteristic of thesecond halo region 268. - Referring to
FIG. 2B , thesecond CMOS device 290 includes awafer 292 onto which thefirst device 240 and thesecond device 260 are formed. Thewafer 292 may include asubstrate 294, such as silicon. Thesubstrate 294 may include afirst region 241 corresponding to thefirst device 240 and asecond region 261 corresponding to thesecond device 260. Thesubstrate 294 may include theSTI regions 222, the S/D implants 210, the first lightly dopedregion 246, thefirst halo region 248, the second lightly dopedregions 266, and thesecond halo region 268. - Referring to
FIGS. 2A-B , thefirst device 240 and thesecond device 260 are a same device type, and each offirst device 240 and thesecond device 260 is designed to operate at a different RF band and within a different corresponding electrical domain of operation. For example, thefirst device 240 may be designed to operate at a lower RF band than thesecond device 260. Accordingly, thefirst device 240 may be referred to as a low band device, and thesecond device 260 may be referred to as a high band device. In a particular embodiment, thefirst device 240 is a low band power amplifier, and thesecond device 260 is a high band power amplifier. - When the
first device 240 is the low band device and thesecond device 260 is the high band device, one or more attributes (e.g., one or more characteristic values) of thefirst device 240 and thesecond device 260 may be determined based on the frequency band in which each device is designed to operate. As a first example, the first insulator material thickness tI1 may be thicker than the second insulator material thickness tI2. As a second example, the first semiconducting layer thickness tSi1 may be thicker than the second semiconducting layer thickness tSi12. As a third example, the first channel length Lg1 of thefirst gate 242 may be longer than the second channel length Lg2 of thesecond gate 262. As a fourth example, the height h1 of thefirst gate oxide 244 may be larger (e.g., thicker) than the height h2 of thesecond gate oxide 264. As a fifth example, the first spacer thickness tS1 of thefirst spacers 250 may be thicker than the second spacer thickness tS2 of thesecond spacers 270. As a sixth example, a first cross sectional area of the first spacer profile of thefirst spacers 250 may be larger than a second cross sectional area of the second spacer profile of thesecond spacers 270. - As a seventh example, a first cross sectional area of the first lightly doped profile of the first lightly doped
region 246 may be larger than a second cross sectional area of the second lightly doped profile of the second lightly dopedregion 266. As an eighth example, the first lightly doped dopant type of the first lightly dopedregion 246 may be a first lightly doped dopant having a larger molecular mass (e.g., molecular weight) than a second lightly doped dopant of the second lightly doped dopant type of the second lightly dopedregion 266. As a ninth example, the first lightly doped dopant concentration of the first lightly dopedregion 246 may be a greater dopant concentration (e.g., a doping concentration) than the second lightly doped dopant concentration of the second lightly dopedregion 266. - As a tenth example, a first cross sectional area of the first halo profile of the
first halo region 248 may be larger than a second cross sectional area of the second halo profile of thesecond halo region 268. As an eleventh example, the first halo dopant type of thefirst halo region 248 may be a first halo dopant having a larger molecular mass (e.g., molecular weight) than a second halo dopant of the second halo dopant type of thesecond halo region 268. As a twelfth example, the first halo dopant concentration (e.g., a doping concentration) of thefirst halo region 248 may be a greater dopant concentration than the second halo dopant concentration of thesecond halo region 268. - One or more of the examples described above may be incorporated in or otherwise utilized by the
first CMOS device 200 ofFIG. 2A or thesecond CMOS device 290 ofFIG. 2B based on the RF bands for thefirst region 241 and thesecond region 261. Thus, a single die of thefirst CMOS device 200 ofFIG. 2A or thesecond CMOS device 290 ofFIG. 2B may advantageously include multiple RF devices that are each designed for performance and reliability at a corresponding frequency band. Thefirst CMOS device 200 ofFIG. 2A or thesecond CMOS device 290 ofFIG. 2B may have a smaller form factor and may be produced at a reduced cost as compared to RF circuits that are constructed on separate wafers or separate chips. Examples of forming/fabricating a semiconductor device, such as thefirst CMOS device 200 ofFIG. 2A or thesecond CMOS device 290 ofFIG. 2B , are described with reference toFIGS. 3-5 . - Referring to
FIG. 3 , a first illustrative embodiment of amethod 300 to form a single die that accommodates multiple RF bands is illustrated. The single die may be formed by a complementary metal-oxide-semiconductor (CMOS) process performed on a wafer. For example, the single die may include thedie 102 ofFIG. 1 , a die of thefirst CMOS device 200 ofFIG. 2A , or a die of thesecond CMOS device 290 ofFIG. 2B . - A first radio frequency (RF) device of a first RF circuit is formed, at 302. The first RF device has a first device type (e.g., first component type) and a first value of a characteristic. The first RF circuit is designed to operate at a first RF band. For example, the first RF device may correspond to or be associated with one of the
devices FIG. 1 or one of thefirst device 240 or thesecond device 260 ofFIGS. 2A-B . - A second RF device of a second RF circuit is formed, at 304. The second RF device has a second device type (e.g., a second component type) and a second value of the characteristic. For example, the second RF device may correspond to or be associated with one of the
devices FIG. 1 or one of thefirst device 240 or thesecond device 260 ofFIGS. 2A-B . The second RF circuit is designed to operate at a second RF band. The first device type and the second device type are a same device type (e.g., a same component type). The first value of the characteristic is different than the second value of the characteristic. The first RF circuit and the second RF circuit are formed by a complementary metal-oxide-semiconductor (CMOS) process performed on a wafer, such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer. - Thus, a method of forming a single chip that accommodates multiple RF bands has been described. The first device and the second device are designed to operate at different RF bands. For example, the first device may be designed to operate at a first frequency band, and the second device may be designed to operate at a second frequency band. In a particular embodiment, the first frequency band is a lower frequency band than the second frequency band. Each device may be configured based on a corresponding frequency band by adjusting one or more parameters (e.g., one or more characteristic values) of the device, such as a channel length, a gate oxide thickness, a lightly doped region profile volume or cross sectional area, a halo region profile volume or cross sectional area, a silicon layer thickness, a buried oxide layer thickness, or a spacer thickness during the CMOS process, as described further with reference to
FIGS. 4 and 5 . - Referring to
FIG. 4 , a second illustrative embodiment of a method to form a single die that accommodates multiple RF bands is illustrated and designated 400. For example, the single die may include thedie 102 ofFIG. 1 , a die of thefirst CMOS device 200 ofFIG. 2A , or a die of thesecond CMOS device 290 ofFIG. 2B . - First processing is performed on a first region and a second region, at 402. The first processing may be configured to construct (e.g., fabricate) a first device to operate at a first RF band and to construct a second device to operate at a second RF band. For example, the first device and the second device may each be associated with a different one of the
devices FIG. 1 or thefirst device 240 and thesecond device 260 ofFIGS. 2A-B . - The first processing may include forming a first gate oxide on the die, at 404, and the first processing may include performing second processing to form a second gate oxide on the second region, at 406. The first gate oxide may be formed on the first region (e.g., the
first region 241 ofFIGS. 2A-B ) and on the second region (e.g., thesecond region 261 ofFIGS. 2A-B ). The second processing may include performing thin gate lithography to cover (e.g., protect) the first gate oxide in the first region and to expose (e.g., leave uncovered) the first gate oxide on the second region, removing the first gate oxide from the second region, and forming the second gate oxide on the second region (e.g., thesecond gate oxide 264 in the second region 261). Accordingly, the second gate oxide may have a different thickness than the first gate oxide. For example, when the first device is configured to operate at a lower frequency than the second device, the first gate oxide may be thicker than the second gate oxide. Alternatively, the second processing may include performing thin gate lithography to cover (e.g., protect) the first gate oxide in the first region and to expose (e.g., leave uncovered) the first gate oxide on the second region and forming the second gate oxide on the second region by adding additional gate oxide material to the first gate oxide in the first region. - First gate material of a first device may be formed on the first region, and second gate material of a second device may be formed on the second region, at 408. To illustrate, polysilicon may be formed over the gate oxide in both regions in a common depositing/lithography/etching process. For example, the first device may correspond to one of the
first device 112, thesecond device 122, and theNth device 132 ofFIG. 1 , or thefirst device 240 and thesecond device 260 ofFIGS. 2A-B , and the second device may correspond to another one of thefirst device 112, thesecond device 122, and theNth device 132 ofFIG. 1 , or thefirst device 240 and thesecond device 260 ofFIGS. 2A-B . The first device and the second device may each be designed to operate at different radio frequency bands. For example, the first device may correspond to a first radio frequency (RF) band, and the second device may correspond to a second RF band that is different from the first RF band. In a particular embodiment, the first device is a first power amplifier and the second device is a second power amplifier. - Referring to
FIG. 5 , a third illustrative embodiment of a method to form a single die that accommodates multiple RF bands is illustrated and designated 500. For example, the single die may include thedie 102 ofFIG. 1 . The method may include a complementary metal-oxide-semiconductor (CMOS) process. - Common processing steps may be performed on a wafer, at 502. The wafer, such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer, may include a first region and a second region, such as the
first region 241 and thesecond region 261 ofFIGS. 2A-B . The first region may be associated with a first device designed to operate at a first RF band, and the second region may be associated with a second device designed to operate at a second RF band. For example, the first device may correspond to one of thefirst device 112, thesecond device 122, and theNth device 132, ofFIG. 1 , or thefirst device 240 and thesecond device 260 ofFIGS. 2A-B , and the second device may correspond to another one of thefirst device 112, thesecond device 122, and theNth device 132, ofFIG. 1 , or thefirst device 240 and thesecond device 260 ofFIGS. 2A-B . The first device and the second device may each be designed to operate at different radio frequency bands. In a particular embodiment, the first device is a first power amplifier, and the second device is a second power amplifier. The wafer may include thewafer 202 ofFIG. 2A , such as a silicon on insulator wafer having a substrate layer, an insulator material layer, and a semiconducting layer (e.g., a silicon layer) or may include thewafer 292 ofFIG. 2B , such as a bulk silicon wafer. The common processing may include forming shallow trench isolation regions, p well regions, n well regions, one or more other semiconductor process components, or a combination thereof. - Wafer processing may be performed on the wafer prior to performing the common processing. For example, the wafer processing may include configuring a first thickness of the silicon layer of the first region to be thicker than a second thickness of the silicon layer of the second region when the first device is designed to operate at a lower RF band than the second device. As another example, when the first device is designed to operate at a lower RF band than the second device, the wafer processing may include configuring a first thickness of the buried oxide layer of the first region to be thicker than a second thickness of the buried oxide layer of the second region.
- A first gate oxide may be formed on the first region, and a second gate oxide may be formed on the second region, at 504. The first gate oxide and the second gate oxide may have a same or a different thickness. The first oxide (e.g., a thickness of the first oxide) may be configured to enable the first device to operate in a first electrical domain of operation corresponding to a first RF band, and the second oxide (e.g., a thickness of the second oxide) may be configured to enable the second device to operate in a second electrical domain of operation corresponding to a second RF band. For example, the first gate oxide and the second gate oxide may be formed according to at least a portion of the
method 400 ofFIG. 4 . - First gate material of the first device may be formed on the first region, and second gate material of the second device may be formed on the second region, at 508. For example, the first gate material and the second gate material may be formed during a common gate formation process performed on the first region and the second region.
- Processing is performed on a first region and a second region, at 510. The processing may construct (e.g., fabricate) the first device to operate at the first RF band and to construct the second device to operate at the second RF band. The processing may include performing first processing on the first region, at 512, and performing second processing on the second region, at 514. The first processing and the second processing may correspond to a same characteristic type of the first device and the second device. For example, the characteristic type may include a channel length, a gate oxide thickness, a lightly doped region characteristic, a halo region characteristic, or a combination thereof. A first value of the characteristic type of the first device may be different than a second value of the characteristic type of the second device. For example, when the first device is designed to operate at a lower RF band than the second device, a first channel length of the first device may be longer than a second channel length of the second device, a first gate oxide thickness of the first device may be thicker than a second gate oxide thickness of the second device, a first lightly doped region characteristic (e.g., a profile volume, a profile cross sectional area, a profile cross sectional shape, a dopant concentration, or a dopant type) of the first device may be different than a second lightly doped region characteristic of the second device, a first halo region characteristic (e.g., a profile volume, a profile cross sectional area, a profile cross sectional shape, a dopant concentration, or a dopant type) of the first device may be greater than a second halo region characteristic of the second device, or a combination thereof.
- Second common processing may be performed on the first region and the second region, at 516. The second common processing may include forming spacers, forming n source/drain implants, p source/drain implants, silicides, contacts,
metal 1 layers, vias,metal 2 layers, or a combination thereof. - The
method 300 ofFIG. 3 , themethod 400 ofFIG. 4 , themethod 500 ofFIG. 5 , or any combination thereof, may be initiated or controlled by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit, such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, a firmware device, or any combination thereof. As an example, themethod 300 ofFIG. 3 , themethod 400 ofFIG. 4 , or themethod 500 ofFIG. 5 can be initiated or controlled by one or more processors, operating systems, or controllers. - Referring to
FIG. 6 , a block diagram of a particular illustrative embodiment of awireless communication device 600 is depicted. Thedevice 600 may include, or have incorporated therein, thedie 102 ofFIG. 1 . - The
device 600 includes aprocessor 610, such as a digital signal processor (DSP), coupled to amemory 632. Thememory 632 includes instructions 668 (e.g., executable instructions) such as computer-readable instructions that are readable by theprocessor 610. Theinstructions 668 may include one or more instructions that are executable by a computer, such as theprocessor 610. -
FIG. 6 also shows adisplay controller 626 that is coupled to theprocessor 610 and to adisplay 628. A coder/decoder (CODEC) 634 can also be coupled to theprocessor 610. Aspeaker 636 and amicrophone 638 can be coupled to theCODEC 634. -
FIG. 6 also indicates that awireless interface 640 can be coupled to theprocessor 610 and to anantenna 642. Thewireless interface 640 may include a wireless controller, a wireless transceiver, such as a receiver circuit, a transmitter circuit, or a combination thereof. Thewireless interface 640 may include adevice 664, such as thedie 102 ofFIG. 1 . For example, thedevice 664 may include a first radio frequency (RF) component and a second RF component, such as thefirst device 112 and thesecond device 122 ofFIG. 1 . For example, the first RF component and the second RF component may each include a power amplifier, an antenna switch, a low noise amplifier, or one or more transistors. Accordingly, the first RF component and the second RF component may be included in a receiver circuit, a transmitter circuit, or a combination thereof. Thedevice 664 may be a chip (e.g., a single chip) configured to accommodate multiple radio frequency (RF) bands. In an alternative embodiment, thedevice 664 may be located in one or more components of thedevice 600 other than in thewireless interface 640. - In a particular embodiment, the
processor 610, thedisplay controller 626, thememory 632, theCODEC 634, and thewireless interface 640 are included in a system-in-package or system-on-chip device 622. In a particular embodiment, aninput device 630 and apower supply 644 are coupled to the system-on-chip device 622. Moreover, in a particular embodiment, as illustrated inFIG. 6 , thedisplay 628, theinput device 630, thespeaker 636, themicrophone 638, thewireless antenna 642, and thepower supply 644 are external to the system-on-chip device 622. However, each of thedisplay 628, theinput device 630, thespeaker 636, themicrophone 638, theantenna 642, and thepower supply 644 can be coupled to a component of the system-on-chip device 622, such as an interface or a controller. - One or more of the disclosed embodiments may be implemented in a system or an apparatus, such as the
device 600, that may include a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a satellite phone, a computer, a tablet, a portable computer, or a desktop computer. Additionally, thedevice 600 may include a set top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, a portable digital video player, any other device that stores or retrieves data or computer instructions, or a combination thereof. As another illustrative, non-limiting example, the system or the apparatus may include remote units, such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. - The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described above.
FIG. 7 depicts a particular illustrative embodiment of an electronicdevice manufacturing process 700. -
Physical device information 702 is received at themanufacturing process 700, such as at aresearch computer 706. Thephysical device information 702 may include design information representing at least one physical property of a semiconductor device, such as a semiconductor device including thedie 102 ofFIG. 1 . For example, thephysical device information 702 may include physical parameters, material characteristics, and structure information that is entered via auser interface 704 coupled to theresearch computer 706. Theresearch computer 706 includes aprocessor 708, such as one or more processing cores, coupled to a computer-readable medium such as amemory 710. Thememory 710 may store computer-readable instructions that are executable to cause theprocessor 708 to transform thephysical device information 702 to comply with a file format and to generate alibrary file 712. - In a particular embodiment, the
library file 712 includes at least one data file including the transformed design information. For example, thelibrary file 712 may include a library of semiconductor devices including a device that includes thedie 102 ofFIG. 1 , that is provided to use with an electronic design automation (EDA)tool 720. - The
library file 712 may be used in conjunction with theEDA tool 720 at adesign computer 714 including aprocessor 716, such as one or more processing cores, coupled to amemory 718. TheEDA tool 720 may be stored as processor-executable instructions at thememory 718 to enable a user of thedesign computer 714 to design a circuit including thedie 102 ofFIG. 1 , of thelibrary file 712. For example, a user of thedesign computer 714 may entercircuit design information 722 via auser interface 724 coupled to thedesign computer 714. Thecircuit design information 722 may include design information representing at least one physical property of a semiconductor device, such as a semiconductor device that includes thedie 102 ofFIG. 1 . To illustrate, the circuit design property may include identification of particular circuits and relationships to other elements in a circuit design, positioning information, feature size information, interconnection information, or other information representing a physical property of a semiconductor device. - The
design computer 714 may be configured to transform the design information, including thecircuit design information 722, to comply with a file format. To illustrate, the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format (e.g., a GDSII format). Thedesign computer 714 may be configured to generate a data file including the transformed design information, such as aGDSII file 726 that includes information describing thedie 102 ofFIG. 1 , in addition to other circuits or information. To illustrate, the data file may include information corresponding to a system-on-chip (SOC) that includes thedie 102 ofFIG. 1 , and that may also include additional electronic circuits and components within the SOC. - The
GDSII file 726 may be received at afabrication process 728 to manufacture a wafer including thedie 102 ofFIG. 1 , according to transformed information in theGDSII file 726. For example, a device manufacture process may include providing the GDSII file 726 to amask manufacturer 730 to create one or more masks, such as masks to be used with photolithography processing, illustrated as arepresentative mask 732. Themask 732 may be used during the fabrication process to generate one ormore wafers 734, such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer. For example, thewafers 734 may correspond to thewafer 202 ofFIG. 2A or thewafer 292 ofFIG. 2B , which may be tested and separated into dies, such as arepresentative die 736. Thedie 736 may include or correspond to the die 102 ofFIG. 1 . - In a particular embodiment, the
fabrication process 728 is implemented by a computer including aprocessor 731 and amemory 733. The memory 733 (e.g., a non-transitory computer-readable medium) may include instructions that are executable by theprocessor 731 to cause theprocessor 731 to operate in accordance with at least a portion of any of themethod 300 ofFIG. 3 , themethod 400 ofFIG. 4 , themethod 500 ofFIG. 5 , or any combination thereof. For example, the computer-executable instructions may be executable to cause theprocessor 731 to initiate formation of a complementary metal-oxide-semiconductor (CMOS) device. The formation of the CMOS device includes forming a first gate oxide in a first region and in a second region of a wafer, such as a silicon on insulator (SOI) wafer, a silicon on silicon (SOS) wafer, or a bulk silicon wafer. The CMOS device is further formed by performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The formation of the CMOS device also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to (e.g., is configured to operate in) a first radio frequency (RF) band, and the second device corresponds to (e.g., is configured to operate in) a second RF band that is different from the first RF band. - As another example, the computer-executable instructions may be executable to cause the
processor 731 to initiate performing a complementary metal-oxide-semiconductor (CMOS) process to form a first radio frequency (RF) circuit and a second RF circuit. The first RF circuit is designed to operate at a first RF band, and the second RF circuit is designed to operate at a second RF band that is different from the first RF band. The CMOS process includes forming a first RF device of the first RF circuit and forming a second RF device of the second RF circuit. The first RF device has a first device type and a first value of a characteristic, and the second RF device has a second device type and a second value of the characteristic. The first device type and the second device type are a same device type, and the first value of the characteristic is different from the second value of the characteristic. - The
die 736 may be provided to apackaging process 738 where thedie 736 is incorporated into arepresentative package 740. For example, thepackage 740 may include thesingle die 736 or multiple dies, such as a system-in-package (SiP) arrangement. Thepackage 740 may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards. - Information regarding the
package 740 may be distributed to various product designers, such as via a component library stored at acomputer 746. Thecomputer 746 may include aprocessor 748, such as one or more processing cores, coupled to amemory 750. A printed circuit board (PCB) tool may be stored as processor-executable instructions at thememory 750 to processPCB design information 742 received from a user of thecomputer 746 via auser interface 744. ThePCB design information 742 may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to thepackage 740 including thedie 102 ofFIG. 1 . - The
computer 746 may be configured to transform thePCB design information 742 to generate a data file, such as a GERBER file 752 with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to thepackage 740 including thedie 102 ofFIG. 1 . In other embodiments, the data file generated by the transformed PCB design information may have a format other than a GERBER format. - The
GERBER file 752 may be received at aboard assembly process 754 and used to create PCBs, such as arepresentative PCB 756, manufactured in accordance with the design information stored within theGERBER file 752. For example, the GERBER file 752 may be uploaded to one or more machines to perform various steps of a PCB production process. ThePCB 756 may be populated with electronic components including thepackage 740 to form a representative printed circuit assembly (PCA) 758. - The
PCA 758 may be received at aproduct manufacture process 760 and integrated into one or more electronic devices, such as a first representativeelectronic device 762 and a second representativeelectronic device 764. As an illustrative, non-limiting example, the first representativeelectronic device 762, the second representativeelectronic device 764, or both, may be selected from the group of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which thedie 102 ofFIG. 1 is integrated. As another illustrative, non-limiting example, one or more of theelectronic devices FIG. 7 illustrates remote units according to teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Embodiments of the disclosure may be suitably employed in any device which includes active integrated circuitry including memory and on-chip circuitry. - A device that includes the
die 102 ofFIG. 1 , may be fabricated, processed, and incorporated into an electronic device, as described in theillustrative process 700. One or more aspects of the embodiments disclosed with respect toFIGS. 1-6 may be included at various processing stages, such as within thelibrary file 712, theGDSII file 726, and the GERBER file 752, as well as stored at thememory 710 of theresearch computer 706, thememory 718 of thedesign computer 714, thememory 733 of a computer associated with thefabrication process 728, thememory 750 of thecomputer 746, the memory of one or more other computers or processors (not shown) used at the various stages, such as at theboard assembly process 754, and also incorporated into one or more other physical embodiments such as themask 732, thedie 736, thepackage 740, thePCA 758, other products such as prototype circuits or devices (not shown), or any combination thereof. Although various representative stages of production from a physical device design to a final product are depicted, in other embodiments fewer stages may be used or additional stages may be included. Similarly, theprocess 700 may be performed by a single entity or by one or more entities performing various stages of theprocess 700. - In conjunction with one or more of the described embodiments, an apparatus is disclosed that may include a first radio frequency (RF) component corresponding to (e.g., configured to operate in) a first RF band, and a second RF component corresponding to (e.g., configured to operate in) a second RF band that is different from the first RF band. The first RF component may include first means for gating a first channel. The first means for gating may correspond to the
first gate 242 or thesecond gate 262 ofFIGS. 2A-B , one or more other devices or circuits configured to gate the first channel, or any combination thereof. The first channel may be positioned between first means for sourcing first current to the first channel and first means for draining the first current from the first channel. The first means for sourcing may correspond to one of the S/D implants 210 ofFIGS. 2A-B , one or more other devices or circuits configured to source the first current to the first channel, or any combination thereof. The first means for draining may correspond to another of the S/D implants 210 ofFIGS. 2A-B , one or more other devices or circuits configured to drain the first current from the first channel, or any combination thereof. The first means for gating the first channel is insulated from first semiconductor means for conducting first charge carriers by a first insulator. The first semiconductor means for conducting may correspond to thesemiconducting layer 208 ofFIG. 2A , thesubstrate 294 ofFIG. 2B , one or more other devices or circuits configured to conduct the first charge carriers, or any combination thereof. The first insulator may correspond to theinsulator material 206 ofFIG. 2A , one or more other materials configured to insulate the first means for gating from the first semiconductor means for conducting, or any combination thereof. - The second RF component of the apparatus may include second means for gating a second channel. The second means for gating may correspond to the
first gate 242 or thesecond gate 262 ofFIGS. 2A-B , one or more other devices or circuits configured to gate the second channel, or any combination thereof. The second channel may be positioned between second means for sourcing second current to the second channel and second means for draining the second current from the second channel. The second means for sourcing may correspond to the S/D implants 210 ofFIGS. 2A-B , one or more other devices or circuits configured to source the second current to the second channel, or any combination thereof. The second means for draining may correspond to the S/D implants 210 ofFIGS. 2A-B , one or more other devices or circuits configured to drain the second current from the second channel, or any combination thereof. The second means for gating the second channel is insulated from the second semiconductor means for conducting first charge carriers by a second insulator. The second semiconductor means for conducting may correspond to thesemiconducting layer 208 ofFIG. 2A , thesubstrate 294 ofFIG. 2B , one or more other devices or circuits configured to conduct the second charge carriers, or any combination thereof. The second insulator may correspond to theinsulator material 206 ofFIG. 2A , one or more other materials circuits configured to insulate the second means for gating from the second semiconductor means for conducting, or any combination thereof. A first thickness of the first insulator is different than a second thickness of the second insulator. - In conjunction with the described embodiments, a method is disclosed that may include a step for forming a first gate oxide in a first region and in a second region of a wafer, such as described in the
method 300 ofFIG. 3 at 302, themethod 400 ofFIG. 4 at 402, 404, described in themethod 500 ofFIG. 5 at 504, a deposition process, a lithography process, an etch process, one or more other processes configured to form the first gate oxide in the first region and in the second region of the wafer, or any combination thereof. The method may also include a step for performing first processing to form a second gate oxide in the second region, such as described in themethod 300 ofFIG. 3 at 304, themethod 400 ofFIG. 4 at 402, 406, described in themethod 500 ofFIG. 5 at 504, a deposition process, a lithography process, an etch process, one or more other processes configured to perform the first processing to for the second gate oxide in the second region, or any combination thereof. The method may also include a step forming first gate material of a first device in the first region and forming second gate material of a second device in the second region, such as the as described in themethod 300 ofFIG. 3 at 302, 304, themethod 400 ofFIG. 4 at 408, described in themethod 500 ofFIG. 5 at 508, a deposition process, a lithography process, an etch process, one or more other processes configured to form the first gate material of the first device in the first region and form the second gate material of the second device in the second region, or any combination thereof. The first device corresponds to a first radio frequency (RF) band, and the second device corresponds to a second RF band that is different from the first RF band. - Although one or more of
FIGS. 1-7 may illustrate systems, apparatuses, and/or methods according to the teachings of the disclosure, the disclosure is not limited to these illustrated systems, apparatuses, and/or methods. Embodiments of the disclosure may be suitably employed in any device that includes integrated circuitry including memory, a processor, and on-chip circuitry. - Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or processor-executable instructions depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
- The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transient storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.
- The previous description of the disclosed embodiments is provided to enable a person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.
Claims (20)
1. A device comprising:
a first radio frequency (RF) component on a die, wherein the first RF component includes a first lightly doped region having a first value of a characteristic, the first RF component configured to operate in a first RF band associated with a first frequency; and
a second RF component on the die, wherein the second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value, the second RF component configured to operate in a second RF band associated with a second frequency that is different from the first frequency.
2. The device of claim 1 , wherein the characteristic includes a profile, a dopant type, or a dopant concentration.
3. The device of claim 1 , wherein the first lightly doped region has a larger profile than the second lightly doped region.
4. The device of claim 1 , wherein a first molecular weight of a first dopant in the first lightly doped region is greater than a second molecular weight of a second dopant in the second lightly doped region.
5. The device of claim 1 , wherein a first dopant concentration of a first dopant in the first lightly doped region is greater than a second dopant concentration of a second dopant in the second lightly doped region.
6. The device of claim 1 , wherein the second RF component is fabricated by a process that includes forming a layer of a first gate oxide, removing a portion of the first gate oxide from a region of the die, and forming a layer of a second gate oxide in the region.
7. The device of claim 1 , wherein the first RF component and the second RF component comprise semiconductor devices that are integrated in the die.
8. The device of claim 1 , wherein the first RF component includes a first halo region having a third value of a second characteristic, and the second RF component includes a second halo region having a fourth value of the second characteristic that is different from the third value.
9. A device comprising:
a first radio frequency (RF) component on a die, wherein the first RF component includes a first halo region having a first value of a characteristic, the first RF component configured to operate in a first RF band associated with a first frequency; and
a second RF component on the die, wherein the second RF component includes a second halo region having a second value of the characteristic, wherein the second value is different from the first value and the second RF component is configured to operate in a second RF band associated with a second frequency that is different from the first frequency.
10. The device of claim 9 , wherein the characteristic includes a profile, a dopant type, or a dopant concentration.
11. The device of claim 9 , wherein the first halo region has a larger profile than the second halo region.
12. The device of claim 9 , wherein a first molecular weight of a first dopant in the first halo region is greater than a second molecular weight of a second dopant in the second halo region.
13. The device of claim 9 , wherein a first dopant concentration of a first dopant in the first halo region is greater than a second dopant concentration of a second dopant in the second halo region.
14. The device of claim 9 , wherein the second RF component is fabricated by a process that includes forming a layer of a first gate oxide, removing a portion of the first gate oxide on a region of the die, and forming a layer of a second gate oxide on the region.
15. The device of claim 9 , wherein the first RF component and the second RF component comprise semiconductor devices that are integrated in the die.
16. A method comprising:
performing, on a wafer, a complementary metal-oxide-semiconductor (CMOS) process to form a first radio frequency (RF) circuit and a second RF circuit, the first RF circuit configured to operate in a first RF band associated with a first frequency, the second RF circuit configured to operate in a second RF band associated with a second frequency that is greater than the first frequency, wherein performing the CMOS process comprises:
forming a first RF device of the first RF circuit, the first RF device having a first device type and a first value of a characteristic; and
forming a second RF device of the second RF circuit, the second RF device having a second device type and a second value of the characteristic, wherein the first device type and the second device type are a same device type, and wherein the first value of the characteristic is different from the second value of the characteristic.
17. The method of claim 16 , wherein the device type is one of a power amplifier, a switch, or a low noise amplifier, and wherein the characteristic is associated with an oxide thickness, a channel length, a spacer profile, a halo profile, or a lightly doped profile.
18. The method of claim 16 , wherein performing the CMOS process is initiated by a processor integrated into an electronic device.
19. The method of claim 16 , wherein forming the first RF device comprises:
forming a first gate oxide in a first region and in a second region of a wafer, the first gate oxide having a first thickness; and
forming first gate material in the first region.
20. The method of claim 19 , wherein forming the second RF device comprises:
performing first processing to form a second gate oxide in the second region, the second gate oxide having a second thickness that is less than the first thickness; and
forming second gate material of in the second region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/991,868 US20160126240A1 (en) | 2013-08-05 | 2016-01-08 | Methods and apparatuses for forming multiple radio frequency (rf) components associated with different rf bands on a chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/958,646 US9252147B2 (en) | 2013-08-05 | 2013-08-05 | Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip |
US14/991,868 US20160126240A1 (en) | 2013-08-05 | 2016-01-08 | Methods and apparatuses for forming multiple radio frequency (rf) components associated with different rf bands on a chip |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/958,646 Division US9252147B2 (en) | 2013-08-05 | 2013-08-05 | Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160126240A1 true US20160126240A1 (en) | 2016-05-05 |
Family
ID=51300871
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/958,646 Expired - Fee Related US9252147B2 (en) | 2013-08-05 | 2013-08-05 | Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip |
US14/991,868 Abandoned US20160126240A1 (en) | 2013-08-05 | 2016-01-08 | Methods and apparatuses for forming multiple radio frequency (rf) components associated with different rf bands on a chip |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/958,646 Expired - Fee Related US9252147B2 (en) | 2013-08-05 | 2013-08-05 | Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip |
Country Status (2)
Country | Link |
---|---|
US (2) | US9252147B2 (en) |
WO (1) | WO2015020786A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10347545B2 (en) | 2016-05-20 | 2019-07-09 | Commissariat A L'energie Atomioue Et Aux Energies Alternatives | Method for producing on the same transistors substrate having different characteristics |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9882020B2 (en) * | 2015-07-24 | 2018-01-30 | Semiconductor Components Industries, Llc | Cascode configured semiconductor component |
US9768109B2 (en) | 2015-09-22 | 2017-09-19 | Qualcomm Incorporated | Integrated circuits (ICS) on a glass substrate |
US20170287855A1 (en) * | 2016-03-31 | 2017-10-05 | Skyworks Solutions, Inc. | Variable handle wafer resistivity for silicon-on-insulator devices |
US10886382B2 (en) * | 2017-02-15 | 2021-01-05 | Skyworks Solutions, Inc. | Cascode amplifier optimization |
US10340289B2 (en) * | 2017-04-28 | 2019-07-02 | Qualcomm Incorporated | Cascode radio frequency (RF) power amplifier on single diffusion |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6009023A (en) | 1998-05-26 | 1999-12-28 | Etron Technology, Inc. | High performance DRAM structure employing multiple thickness gate oxide |
US6214675B1 (en) | 1999-02-08 | 2001-04-10 | Lucent Technologies Inc. | Method for fabricating a merged integrated circuit device |
SE522892C2 (en) | 1999-09-28 | 2004-03-16 | Ericsson Telefon Ab L M | An amplifier circuit for amplifying signals |
US6396107B1 (en) | 2000-11-20 | 2002-05-28 | International Business Machines Corporation | Trench-defined silicon germanium ESD diode network |
US6436845B1 (en) | 2000-11-28 | 2002-08-20 | Lsi Logic Corporation | Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit |
US20020155686A1 (en) | 2001-04-24 | 2002-10-24 | Hung-Sui Lin | Fabrication method for suppressing a hot carrier effect and leakage currents of I/O devices |
DE10123594B4 (en) | 2001-05-15 | 2006-04-20 | Infineon Technologies Ag | Integrated semiconductor circuit with differently frequently connected transistors |
US6500739B1 (en) | 2001-06-14 | 2002-12-31 | Taiwan Semiconductor Manufacturing Company | Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect |
US7382023B2 (en) | 2004-04-28 | 2008-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully depleted SOI multiple threshold voltage application |
DE102008035805B4 (en) * | 2008-07-31 | 2013-01-31 | Advanced Micro Devices, Inc. | Production of gate dielectrics into PMOS and NMOS transistors |
KR101101512B1 (en) * | 2010-07-29 | 2012-01-03 | 삼성전기주식회사 | Cmos power amplifier |
US8377772B2 (en) | 2010-08-17 | 2013-02-19 | Texas Instruments Incorporated | CMOS integration method for optimal IO transistor VT |
JP2012084636A (en) | 2010-10-08 | 2012-04-26 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
JP2012190994A (en) | 2011-03-10 | 2012-10-04 | Renesas Electronics Corp | Method of manufacturing semiconductor device and semiconductor device |
JP2014207252A (en) | 2011-08-17 | 2014-10-30 | 株式会社村田製作所 | Semiconductor device, manufacturing method therefor, and portable telephone |
US9131634B2 (en) * | 2011-11-15 | 2015-09-08 | Qualcomm Incorporated | Radio frequency package on package circuit |
-
2013
- 2013-08-05 US US13/958,646 patent/US9252147B2/en not_active Expired - Fee Related
-
2014
- 2014-07-22 WO PCT/US2014/047548 patent/WO2015020786A2/en active Application Filing
-
2016
- 2016-01-08 US US14/991,868 patent/US20160126240A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10347545B2 (en) | 2016-05-20 | 2019-07-09 | Commissariat A L'energie Atomioue Et Aux Energies Alternatives | Method for producing on the same transistors substrate having different characteristics |
Also Published As
Publication number | Publication date |
---|---|
US9252147B2 (en) | 2016-02-02 |
WO2015020786A3 (en) | 2015-04-02 |
WO2015020786A2 (en) | 2015-02-12 |
US20150035072A1 (en) | 2015-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10079293B2 (en) | Semiconductor device having a gap defined therein | |
US20160126240A1 (en) | Methods and apparatuses for forming multiple radio frequency (rf) components associated with different rf bands on a chip | |
US9412818B2 (en) | System and method of manufacturing a fin field-effect transistor having multiple fin heights | |
US9425296B2 (en) | Vertical tunnel field effect transistor | |
US9153587B2 (en) | Fin-type semiconductor device | |
US8847315B2 (en) | Complementary metal-oxide-semiconductor (CMOS) device and method | |
US10116285B2 (en) | Integration of a replica circuit and a transformer above a dielectric substrate | |
US20170278842A1 (en) | Integrated circuits including a finfet and a nanostructure fet | |
US9245971B2 (en) | Semiconductor device having high mobility channel | |
US9263522B2 (en) | Transistor with a diffusion barrier | |
US10546852B2 (en) | Integrated semiconductor devices and method of fabricating the same | |
US10522687B2 (en) | Wrap-around gate structures and methods of forming wrap-around gate structures | |
US20230282716A1 (en) | High performance device with double side contacts | |
WO2023283500A1 (en) | Three dimensional (3d) double gate semiconductor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: QUALCOMM INCORPORATED, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DUTTA, RANADEEP;YEAP, CHOH FEI;SIGNING DATES FROM 20130813 TO 20130814;REEL/FRAME:037444/0397 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |