CN115695574A

CN115695574A - Avalon protocol conversion method, device, equipment and medium

Info

Publication number: CN115695574A
Application number: CN202211432436.9A
Authority: CN
Inventors: 刘伟; 王洪良; 牟奇; 卢圣才
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2022-11-15
Filing date: 2022-11-15
Publication date: 2023-02-03

Abstract

The application discloses an Avalon protocol conversion method, device, equipment and medium, which are applied to the technical field of bus protocol conversion and comprise the following steps: configuring an Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through a channel corresponding to the Avalon-ST bus channel number; receiving data on an Avalon-ST bus through a depacketizer, and if the channel number of a channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, storing the data into a data cache module; and reading the data from the data caching module through a controller, and transmitting the data to an Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory. The method can ensure the universality of the data written into the storage by the FPGA algorithm module, realize the separation of the data written into the storage from the calculation, and is favorable for the system-level interconnection, the development, the maintenance and the upgrade of the algorithm module.

Description

Avalon protocol conversion method, device, equipment and medium

Technical Field

The present application relates to the field of bus protocol conversion technologies, and in particular, to an Avalon protocol conversion method, apparatus, device, and medium.

Background

At present, heterogeneous acceleration generally utilizes an FPGA to help a CPU to calculate, an FPGA algorithm module writes calculated data into a memory, and the prior art generally uses two buses respectively according to specific service requirements, and does not have a relatively universal conversion design. Fig. 1 is a schematic diagram of writing data of an FPGA algorithm module in the prior art, where the data calculated by the FPGA algorithm module needs to be written into a RAM through an original RAM interface or written into a DDR through an Avalon-MM bus interface. The interfaces of the general algorithm modules are all ready/valid handshake signals (Avalon-ST protocol simple edition), so the algorithm core needs to perform calculation and control at the same time. In summary, the prior art has the following disadvantages: all are specific business requirements and specific analysis, and designers can realize conversion according to requirements, so that the method is not flexible and universal. Moreover, the control and the calculation are not separated, the coupling is extremely high, the system level interconnection is not facilitated, and the development, the maintenance and the upgrading are not facilitated.

Disclosure of Invention

In view of this, an object of the present application is to provide an Avalon protocol conversion method, apparatus, device, and medium, which can ensure the universality of writing data into a storage by an FPGA algorithm module, and implement separation of writing data into the storage and calculation, and are beneficial to system-level interconnection, development, maintenance, and upgrade of the algorithm module. The specific scheme is as follows:

in a first aspect, the present application discloses an Avalon protocol conversion method, including:

configuring an Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through a channel corresponding to the Avalon-ST bus channel number;

receiving data on an Avalon-ST bus through a depacketizer, and if the channel number of a channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, storing the data into a data cache module;

and reading the data from the data caching module through a controller, and transmitting the data to an Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory.

Optionally, the method further includes:

and if the channel number of the channel to which the data belongs is not consistent with the channel number of the Avalon-ST bus, directly discarding the data.

Optionally, the storing the data into the data caching module includes:

storing the data into a FIFO;

correspondingly, the reading the data from the data cache module by the controller includes: reading, by a controller, the data from the FIFO.

Optionally, the method further includes:

and if the FIFO is full, suspending receiving data on the Avalon-ST bus.

Optionally, the configuring the Avalon-ST bus channel number includes:

the Avalon-ST bus channel number is configured to the first register.

Optionally, the method further includes:

respectively configuring a write address initial address and a write data length of an Avalon-MM bus to a second register and a third register;

calculating a write burst address and a burst length based on the write address initial address and the write data length through a controller, and transmitting the data and the write burst address and the burst length to an Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory based on the write burst address and the burst length.

Optionally, the Avalon-ST bus channel number is configured to the first register through the APB bus, and the write address initial address and the write data length of the Avalon-MM bus are configured to the second register and the third register, respectively.

Optionally, the configuring, by the APB bus, the Avalon-ST bus channel number to the first register, and configuring the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register, respectively, includes:

and configuring an Avalon-ST bus channel number to a first register by utilizing a CPU and an APB bus, and configuring a write address initial address and a write data length of the Avalon-MM bus to a second register and a third register respectively.

Optionally, the method further includes:

and when a waiting request signal sent by the Avalon-MM bus slave module is received and represents that the Avalon-MM bus slave module is busy currently, the data is suspended from being sent.

Optionally, the method further includes:

configuring a working trigger register of a preset Avalon-ST to Avalon-MM conversion module so as to start the controller and the unpacker to work;

and setting the working state characterization register to be in a working state.

Optionally, the first register, the second register, the third register, the working trigger register, the working state characterization register, the unpacker, and the data caching module all belong to a module for converting preset Avalon-ST to Avalon-MM.

Optionally, the preset Avalon-ST to Avalon-MM module is connected to the Avalon-MM bus slave module via an Avalon-MM bus.

In a second aspect, the present application discloses an Avalon protocol conversion device, comprising:

the configuration module is used for configuring an Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through a channel corresponding to the Avalon-ST bus channel number;

the device comprises a depacketizer and a data cache module, wherein the depacketizer is used for receiving data on an Avalon-ST bus, and storing the data into the data cache module if the channel number of a channel to which the data belongs is consistent with the channel number of the Avalon-ST bus;

and the controller is used for reading the data from the data cache module and transmitting the data to the Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory.

Optionally, the depacketizer is further configured to directly discard the data if the channel number of the channel to which the data belongs is not consistent with the Avalon-ST bus channel number.

Optionally, the depacketizer is specifically configured to store the data in an FIFO; accordingly, the controller is specifically configured to read the data from the FIFO.

Optionally, the unpacker is further configured to suspend receiving data on the Avalon-ST bus if the FIFO is full.

Optionally, the configuration module is specifically configured to configure the Avalon-ST bus channel number to the first register.

Optionally, the configuration module is further configured to configure a write address initial address and a write data length of the Avalon-MM bus to the second register and the third register, respectively;

correspondingly, the controller is used for calculating a write burst address and a burst length based on the write address initial address and the write data length, and transmitting the data and the burst length of the write burst address to the Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory based on the write burst address and the burst length.

Optionally, the configuration module is specifically configured to configure the Avalon-ST bus channel number to the first register through the APB bus, and configure the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register, respectively.

Optionally, the configuration module is a CPU, and the CPU is configured to configure the Avalon-ST bus channel number to the first register through the APB bus, and configure the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register, respectively.

Optionally, the controller is further configured to suspend sending the data when receiving a wait request signal sent by the Avalon-MM bus slave and the wait request signal indicates that the Avalon-MM bus slave is currently busy.

Optionally, the configuration module is further configured to configure a working trigger register of the preset Avalon-ST to Avalon-MM conversion module, so as to start the controller and the unpacker to work; and the working state characterization register is set to be in a working state.

And the preset Avalon-ST to Avalon-MM module is connected with the Avalon-MM bus slave module through an Avalon-MM bus.

In a third aspect, the present application discloses an electronic device, comprising a storage unit and a processing unit, wherein:

the storage unit is used for storing a computer program;

the processing unit is configured to execute the computer program to implement the above-mentioned Avalon protocol conversion method.

In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned Avalon protocol conversion method.

It can be seen that, in the present application, an Avalon-ST bus channel number is configured, an FPGA algorithm module transmits calculated data out through a channel corresponding to the Avalon-ST bus channel number, and receives data on an Avalon-ST bus through a depacketizer, if the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in a data cache module, the data is read from the data cache module through a controller, and the data is transmitted to an Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into a memory. That is, according to the application, the channel number of the Avalon-ST bus of the channel of the data transmitted by the FPGA algorithm module is configured, the data on the Avalon-ST bus is received through the unpacker, and when the channel number of the channel to which the data belong is consistent with the channel number of the Avalon-ST bus, the data is stored in the data caching module, the data is read from the data caching module through the controller and is transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory, therefore, the Avalon-ST bus protocol is converted into the Avalon-MM bus protocol, the data calculated by the algorithm module is written into the memory instead of the algorithm module itself controlling the writing, the universality of the data written into the memory by the FPGA algorithm module can be guaranteed, the separation of the data written into the memory and the calculation is realized, and the system level interconnection, the development, the maintenance and the upgrading of the algorithm module are facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of FPGA algorithm module data writing in the prior art;

fig. 2 is a flowchart of an Avalon protocol conversion method disclosed in an embodiment of the present application;

FIG. 3 is a block diagram of a specific Avalon-ST to Avalon-MM module disclosed in an embodiment of the present application;

FIG. 4 is a diagram illustrating an application scenario in which a specific Avalon-ST protocol is converted to Avalon-MM according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an Avalon protocol conversion apparatus disclosed in an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

First, terms related to the present application are explained:

FPGA: field Programmable Gate Arrays;

IC: integrated circuits, commonly known as chips;

FIFO: first-in first-out storage;

DDR: the double-rate synchronous dynamic random access memory is one of the memories;

RAM: random Access Memory, random Access Memory;

pceie: the peripheral component interconnect express is a high-speed serial computer expansion bus standard;

an ASIC (Application Specific Integrated Circuit);

avalon bus: the bus is proposed by Intel, and the design of an Intel FPGA system is commonly used for controlling high-speed data stream transmission, a read-write register, a memory and off-chip equipment;

Avalon-Stream: the Avalon bus flow mode is also called Avalon-ST or AVST, the protocol is simple, unidirectional data flow is supported, no address line exists, and the Avalon bus flow mode is generally used for high-bandwidth low-delay scenes;

Avalon-Memory Map: the device is also called Avalon-MM or AVMM and is provided with an address line which is generally used for reading and writing operation of a status register and a control register; the method supports a burst mode, is mainly used for moving a large amount of data in the burst mode, and has a complex protocol;

APB (Advanced personal Bus): the peripheral bus means that the bus protocol is one of the AMBA bus structures proposed by ARM corporation, and has become almost a standard on-chip bus structure.

With the popularization and application development of technologies such as AI, big data, 5G, deep learning and the like, the task of an internet server is more serious, the performance of a CPU (central processing unit) is not enough to support the business requirements of various videos, images and the like, and heterogeneous acceleration becomes an effective solution. The heterogeneous acceleration generally utilizes the FPGA to help the CPU to perform calculation, shares the working pressure of the CPU, and often requires module connection, system interconnection, and the like in the FPGA design process, which requires a standard bus, but the same bus also has a protocol that is not required for use. In the prior art, two buses are generally used respectively according to specific service requirements, and a relatively universal conversion design does not exist. The data calculated by the FPGA algorithm module needs to be written into the RAM by using an original RAM interface or written into the DDR by using an Avalon-MM bus interface. The interfaces of the general algorithm modules are all ready/valid handshake signals (Avalon-ST protocol simple version), so the algorithm core is required to perform calculation and control at the same time. In summary, the prior art has the following disadvantages: all are specific business requirements and specific analysis, and designers can realize conversion according to requirements, so that the method is not flexible and universal. Moreover, the control and the calculation are not separated, the coupling is extremely high, the system level interconnection is not facilitated, and the development, the maintenance and the upgrading are not facilitated. Therefore, the Avalon protocol conversion scheme is provided, the universality of data written into the storage by the FPGA algorithm module can be guaranteed, the separation of data written into the storage and calculation is realized, and the system-level interconnection, development, maintenance and upgrading of the algorithm module are facilitated.

Referring to fig. 2, an embodiment of the present application discloses an Avalon protocol conversion method, including:

step S11: configuring an Avalon-ST bus channel number; and the FPGA algorithm module transmits the calculated data out through a channel corresponding to the Avalon-ST bus channel number.

It can be understood that the FPGA algorithm module is a module implemented based on an FPGA, which calculates data by using a preset algorithm, and the preset algorithm corresponds to a calculation task. For example, the calculation task is an encryption and decryption task, the preset algorithm is an encryption and decryption algorithm, the calculation task is an image processing task, and the preset algorithm is an image processing algorithm.

In one embodiment, the Avalon-ST bus channel number may be configured to the first register.

Step S12: and receiving data on the Avalon-ST bus through a depacketizer, and storing the data into a data caching module if the channel number of the channel to which the data belong is consistent with the channel number of the Avalon-ST bus.

In a specific embodiment, if the channel number of the channel to which the data belongs is not consistent with the Avalon-ST bus channel number, the data is directly discarded.

Step S13: and reading the data from the data caching module through a controller, and transmitting the data to an Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory.

In one embodiment, the data may be stored in a FIFO; reading, by a controller, the data from the FIFO. And if the FIFO is full, suspending receiving data on the Avalon-ST bus. That is, the data buffer module is a FIFO.

And when a wait request signal sent by the Avalon-MM bus slave is received and represents that the Avalon-MM bus slave is currently busy, suspending sending the data.

Further, in the embodiment of the application, the write address initial address and the write data length of the Avalon-MM bus can be respectively configured to the second register and the third register; calculating a write burst address and a burst length based on the write address initial address and the write data length through a controller, and transmitting the data and the write burst address and the burst length to an Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory based on the write burst address and the burst length.

In addition, the embodiment of the application can configure a working trigger register of a preset Avalon-ST to Avalon-MM module so as to start the controller and the unpacker to work; and the working state characterizing register is set to be in working state. And after finishing writing the data, setting the working state characterization register to be in an idle state.

After the work trigger register is configured, the unpacker waits for data on the AVST bus, if the channel numbers are not matched, the unpacker directly discards the data after receiving the data, if the channel numbers are matched, the unpacker starts receiving the startofpacket signal after receiving the startofpacket signal until receiving the endofpacket signal, and a ready/valid handshake signal protocol needs to be followed in the process. And writing the received valid data into the FIFO, and if the FIFO is full in the process, suspending receiving the AVST bus data and suspending writing the data into the FIFO. And after the work trigger register is configured, the controller takes out data through the FIFO, transmits the burst address, the burst length and the data to the slave module, and when the Avmm _ wait request signal transmitted by the slave module is high, the slave module is busy, transmission is suspended, and when the Avmm _ wait request signal is low, the slave module is idle, and the burst address, the burst length and the data can be transmitted. After the AVMM bus write transmission is finished, the working state characterization register is set to be in an idle state and is set to be low, and the module is represented to be idle.

In one implementation mode, an Avalon-ST bus channel number is configured to a first register through an APB bus, a write address initial address and a write data length of the Avalon-MM bus are configured to a second register and a third register respectively, and a working trigger register and a working state representation register of a preset Avalon-ST to Avalon-MM module are configured.

Further, an Avalon-ST bus channel number is configured to a first register through an APB bus by utilizing a CPU, and a writing address initial address and a writing data length of the Avalon-MM bus are respectively configured to a second register and a third register. And configuring a working trigger register and a working state representation register of a preset Avalon-ST to Avalon-MM conversion module. The CPU can be an internal CPU of the FPGA or an external CPU, the external CPU schedules data through a pcie Bar space mechanism, and the internal CPU can be an ARM hard core embedded in the FPGA or a soft core built by the FPGA with logic.

And the first register, the second register, the third register, the working trigger register, the working state representation register, the unpacker and the data caching module all belong to a module for converting preset Avalon-ST to Avalon-MM. The preset Avalon-ST to Avalon-MM module is connected with the Avalon-MM bus slave module through an Avalon-MM bus. It should be noted that the Avalon-ST and Avalon-MM are both part of the Avalon bus, but they cannot be directly interconnected, and the present application designs a general Avalon-ST protocol to Avalon-MM protocol module. The Avalon-MM protocol is converted into the Avalon-ST protocol, the data calculated by the algorithm module is written into the RAM or DDR by using the FPGA internal CPU or external CPU scheduling data, and the algorithm module is not controlled to write.

The Avalon-MM bus slave module is a slave module corresponding to the preset Avalon-ST to Avalon-MM module, is a preset Avalon-MM bus interconnection module, and the preset Avalon-MM bus interconnection module writes data into DDR or RAM through a DDR controller or a RAM controller. And the DDR controller or the RAM controller is a slave module relative to the preset Avalon-MM bus interconnection module.

For example, referring to fig. 3, fig. 3 is a schematic diagram of a specific Avalon-ST to Avalon-MM module provided in an embodiment of the present application. The Avalon-ST to Avalon-MM module comprises a register, a FIFO, a unpacker, an APB bus, an Avalon-MM bus, an Avalon-ST bus interface and the like. The registers are configured through an APB bus, wherein a register list is shown in a table one, R/W represents readable and writable, WT represents a write trigger, and RO represents read only.

Watch 1

The unpacking device is responsible for receiving data on an Avalon-ST bus, unpacking the data, taking out effective data, and placing the effective data into an FIFO (first in first out) which is used for temporarily storing the unpacked data. The controller is responsible for calculating the burst write address (avmm _ waddr) and the burst length (avmm _ burst) of the Avalon-MM bus at each time according to the initial write address and the write data length, and controlling the Avalon-MM bus behavior. When the register start is triggered, the controller transfers the burst write address and burst length to the slave module via the avmm _ write signal (i.e., write signal), and transfers the data in the RAM or DDR back via the avmm _ write data signal (i.e., write data signal) and the avmm _ begin burst signal (i.e., start burst signal). The Avmm _ waitrequest signal (i.e., slave busy state indicator signal) is high, which means that the slave block is busy and the handshake is invalid. When data starts to be transmitted to the slave module, an avst _ startofpacket signal is enabled, when data transmission is finished, an avst _ endofpacket signal is enabled, and an avst _ channel represents the first channel, and the channel configuration can be carried out according to a register channel. avst _ valid and avst _ ready are transmission handshake signals, and avst _ data represents data. The i _ psel, i _ paddr, i _ enable, i _ pwrite, i _ pwdata, o _ prdata and o _ pready are all signals designed based on the APB protocol and used for configuring the register.

The Avalon-ST to Avalon-MM module runs as follows: 1. three registers, namely, write _ addr, write _ length, channel and the like, are configured through the APB bus, so that the module is informed of which address to write data from the Avalon-MM bus, how much data to write and which channel to read data from the Avalon-ST bus. 2. APB bus writes register start, informs module to start working, and sets register status high after module working. 3. The unpacker waits for data on the AVST bus after receiving start, directly discards the data after receiving if channle numbers do not match, and starts receiving after receiving a startofpacket signal until receiving an endofpacket signal if channle numbers match, wherein a ready/valid handshake signal protocol is required to be followed in the process. And writing the received valid data into the FIFO, and if the FIFO is full in the process, suspending receiving the Avalon-ST bus data and suspending writing the data into the FIFO. 4. When the register start is triggered, the controller module takes out data through FIFO and transmits the address, the burst length and the data to the slave module, the slave module informs the master module whether to receive the data through an Avmm _ wait request signal, the slave module is busy when the slave module is high, the master stops sending the data, and the slave module is idle when the slave module is low, and the address, the burst length and the data can be sent. 5. After the Avalon-MM bus write transfer is complete, the register status is set low, indicating that the module is idle.

Further, referring to fig. 4, fig. 4 is a schematic view of an application scenario of converting the Avalon-ST protocol to Avalon-MM, which is disclosed in the embodiment of the present application. The system mainly comprises a CPU, an APB bus splitting arbitration module, an Avalon-ST to Avalon-MM conversion module, a kernel (namely an algorithm core, the FPGA algorithm module), an Avalon-MM bus interconnection module, a DDR controller, a Block RAM controller and the like. The CPU can be an ARM hard core embedded in the FPGA or a soft core built by the FPGA with logic and is mainly responsible for controlling scheduling; the Avalon-MM bus interconnection module is used for bus splitting arbitration, wherein S represents a bus slave, and M represents a bus master; the DDR controller and the Block RAM controller respectively control an external storage DDR and an internal storage RAM; the kernel is responsible for the acceleration algorithm; the Avalon-ST to Avalon-MM conversion module is responsible for converting an Avalon-ST bus into an Avalon-MM bus and moving kernel output data into a DDR or a RAM; the APB bus is used for register read-write configuration.

It should be noted that all modules in the present application are designed by using a standard bus protocol, which greatly facilitates the design and integration at the system level. The decoupling among the modules ensures the independence, the portability and the maintainability of the modules to the maximum extent. The avst interface protocol is converted into the avmm interface, so that the interface control of the kernel algorithm computing module is simplified, and the algorithm module is convenient to concentrate on computing rather than controlling. The scheduling method can realize full flow, and all modules can be synchronously performed. The flexibility of the system is improved by a method of configuring addresses, lengths and channels by a register, the control authority is given to the CPU as far as possible, and the development and design of a CPU control program are greatly facilitated. And digital IC and FPGA are digital circuit design, and the scheme provided by the application is suitable for FPGA design and digital IC design.

It can be seen that, in the embodiment of the present application, an Avalon-ST bus channel number is configured, an FPGA algorithm module transmits calculated data through a channel corresponding to the Avalon-ST bus channel number, receives data on an Avalon-ST bus through a depacketizer, stores the data in a data cache module if the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, reads the data from the data cache module through a controller, and transmits the data to an Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data in a memory. That is, in the embodiment of the present application, the channel number of the Avalon-ST bus of the channel through which the FPGA algorithm module transmits data is configured, the data on the Avalon-ST bus is received by the unpacker, and when the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, the data is stored in the data cache module, and the data is read from the data cache module by the controller and transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory, so that the Avalon-ST bus protocol is converted into the Avalon-MM bus protocol, and the data calculated by the algorithm module is written into the memory, instead of the algorithm module itself controlling the writing, which can ensure the universality of writing the data into the memory by the FPGA algorithm module, and realize the separation of writing the data into the memory from the calculation, thereby facilitating the system-level interconnection, development, maintenance and upgrade of the algorithm module.

Referring to fig. 5, an embodiment of the present application discloses an Avalon protocol conversion apparatus, including:

a configuration module 11, configured to configure an Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through a channel corresponding to the Avalon-ST bus channel number;

the unpacking device 12 is used for receiving data on an Avalon-ST bus, and if the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, storing the data into a data caching module;

and the controller 13 is configured to read the data from the data caching module and transmit the data to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into a memory.

It can be seen that, in the embodiment of the present application, an Avalon-ST bus channel number is configured, an FPGA algorithm module transmits calculated data out through a channel corresponding to the Avalon-ST bus channel number, and receives data on an Avalon-ST bus through a depacketizer, and if the channel number of the channel to which the data belongs is consistent with the Avalon-ST bus channel number, the data is stored in a data cache module, the data is read from the data cache module through a controller, and the data is transmitted to an Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into a memory. That is, in the embodiment of the present application, the channel number of the Avalon-ST bus of the channel through which the FPGA algorithm module transmits data is configured, the data on the Avalon-ST bus is received by the unpacker, and when the channel number of the channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, the data is stored in the data cache module, and the data is read from the data cache module by the controller and transmitted to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory.

The depacketizer 12 is further configured to directly discard the data if the channel number of the channel to which the data belongs is not consistent with the Avalon-ST bus channel number.

Further, the unpacker 12 is specifically configured to store the data into the FIFO; accordingly, the controller 13 is specifically configured to read the data from the FIFO.

The unpacker 12 is also used to suspend receiving data on the Avalon-ST bus if the FIFO is full.

The configuration module 11 is specifically configured to configure the Avalon-ST bus channel number to the first register.

The configuration module 11 is further configured to configure a write address initial address and a write data length of the Avalon-MM bus to the second register and the third register, respectively;

correspondingly, the controller 13 is configured to calculate a write burst address and a burst length based on the write address initial address and the write data length, and transmit the data and the burst length of the write burst address to the Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data into the memory based on the write burst address and the burst length.

The configuration module 11 is specifically configured to configure, through the APB bus, the Avalon-ST bus channel number to the first register, and configure, respectively, the write address initial address and the write data length of the Avalon-MM bus to the second register and the third register.

And in one embodiment, the configuration module is a CPU, and the CPU is used for configuring the Avalon-ST bus channel number to a first register through an APB bus and configuring the write address initial address and the write data length of the Avalon-MM bus to a second register and a third register respectively.

Further, the controller is further configured to suspend sending the data when a wait request signal sent by the Avalon-MM bus slave is received and the wait request signal indicates that the Avalon-MM bus slave is currently busy.

Further, the configuration module 11 is further configured to configure a working trigger register of a preset Avalon-ST to Avalon-MM module, so as to start the controller and the unpacker to work; and the working state characterizing register is set to be in working state.

After the work trigger register is configured, the unpacker waits for data on an Avalon-ST bus, if the channel numbers are not matched, the unpacker directly discards the data after receiving the data, if the channel numbers are matched, the unpacker starts receiving after receiving a startofpacket signal until receiving an endofpacket signal, and a ready/valid handshake signal protocol needs to be followed in the process. And writing the received valid data into the FIFO, and if the FIFO is full in the process, suspending receiving the AVST bus data and suspending writing the data into the FIFO. And after the work trigger register is configured, the controller takes out data through the FIFO, transmits the burst address, the burst length and the data to the slave module, and when the Avmm _ wait request signal transmitted by the slave module is high, the slave module is busy, transmission is suspended, and when the Avmm _ wait request signal is low, the slave module is idle, and the burst address, the burst length and the data can be transmitted. After the AVMM bus write transmission is finished, the working state characterization register is set to be in an idle state and is set to be low, and the module is represented to be idle.

In an embodiment, the first register, the second register, the third register, the working trigger register, the working state characterization register, the unpacker, and the data caching module all belong to a preset Avalon-ST to Avalon-MM conversion module.

Referring to fig. 6, an embodiment of the present application discloses an electronic device, which includes a processing unit 21 and a storage unit 22; the storage unit 22 is configured to store a computer program; the processing unit 21 is configured to execute the computer program to implement the following steps:

configuring an Avalon-ST bus channel number; the FPGA algorithm module transmits the calculated data through a channel corresponding to the Avalon-ST bus channel number; receiving data on an Avalon-ST bus through a depacketizer, and if the channel number of a channel to which the data belongs is consistent with the channel number of the Avalon-ST bus, storing the data into a data cache module; and reading the data from the data caching module through a controller, and transmitting the data to an Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: and if the channel number of the channel to which the data belongs is not consistent with the channel number of the Avalon-ST bus, directly discarding the data.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: storing the data into a FIFO; reading, by a controller, the data from the FIFO.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: and if the FIFO is full, suspending receiving data on the Avalon-ST bus.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: the Avalon-ST bus channel number is configured to the first register.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: respectively configuring a write address initial address and a write data length of an Avalon-MM bus to a second register and a third register; calculating a write burst address and a burst length based on the write address initial address and the write data length through a controller, and transmitting the data and the write burst address and the burst length to an Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory based on the write burst address and the burst length.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: and configuring the Avalon-ST bus channel number to a first register through an APB bus, and configuring the write address initial address and the write data length of the Avalon-MM bus to a second register and a third register respectively.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: and configuring an Avalon-ST bus channel number to a first register by utilizing a CPU and an APB bus, and configuring a write address initial address and a write data length of the Avalon-MM bus to a second register and a third register respectively.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: and when a waiting request signal sent by the Avalon-MM bus slave module is received and represents that the Avalon-MM bus slave module is busy currently, the data is suspended from being sent.

In this embodiment, when the processing unit 21 executes the computer subprogram stored in the storage unit 22, the following steps may be specifically implemented: configuring a working trigger register of a preset Avalon-ST to Avalon-MM conversion module so as to start the controller and the unpacker to work; and setting the working state characterization register to be in a working state.

The first register, the second register, the third register, the working trigger register, the working state representation register, the unpacker and the data caching module all belong to a module for converting preset Avalon-ST to Avalon-MM. The preset Avalon-ST to Avalon-MM module is connected with the Avalon-MM bus slave module through an Avalon-MM bus.

Further, an embodiment of the present application discloses a computer readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the following steps:

In this embodiment, when the computer subprogram stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: and if the channel number of the channel to which the data belongs is not consistent with the channel number of the Avalon-ST bus, directly discarding the data.

In this embodiment, when the computer subprogram stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: storing the data into a FIFO; reading, by a controller, the data from the FIFO.

In this embodiment, when the computer subprogram stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: and if the FIFO is full, suspending receiving data on the Avalon-ST bus.

In this embodiment, when the processor executes the computer subprogram stored in the computer readable storage medium, the following steps may be specifically implemented: the Avalon-ST bus channel number is configured to the first register.

In this embodiment, when the processor executes the computer subprogram stored in the computer readable storage medium, the following steps may be specifically implemented: respectively configuring a write address initial address and a write data length of an Avalon-MM bus to a second register and a third register; calculating, by a controller, a write burst address and a burst length based on the write address initial address and a write data length, and transmitting the data and the write burst address and the burst length to an Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to a memory based on the write burst address and the burst length.

In this embodiment, when the computer subprogram stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: and configuring the Avalon-ST bus channel number to a first register through an APB bus, and configuring the write address initial address and the write data length of the Avalon-MM bus to a second register and a third register respectively.

In this embodiment, when the computer subprogram stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: and configuring an Avalon-ST bus channel number to a first register by utilizing a CPU and an APB bus, and configuring a write address initial address and a write data length of the Avalon-MM bus to a second register and a third register respectively.

In this embodiment, when the computer subprogram stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: and when a waiting request signal sent by the Avalon-MM bus slave module is received and represents that the Avalon-MM bus slave module is busy currently, the data is suspended from being sent.

In this embodiment, when the computer subprogram stored in the computer-readable storage medium is executed by the processor, the following steps may be specifically implemented: configuring a working trigger register of a preset Avalon-ST to Avalon-MM conversion module so as to start the controller and the unpacker to work; and setting the working state characterization register to be in a working state.

The first register, the second register, the third register, the working trigger register, the working state representation register, the unpacker and the data caching module all belong to a preset Avalon-ST to Avalon-MM conversion module. The preset Avalon-ST to Avalon-MM module is connected with the Avalon-MM bus slave module through an Avalon-MM bus.

In the present specification, the embodiments are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same or similar parts between the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The method, apparatus, device and medium for converting the Avalon protocol provided by the present application are described in detail above, and specific examples are applied in the present disclosure to explain the principles and embodiments of the present application, and the description of the above embodiments is only used to help understand the method and core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An Avalon protocol conversion method, comprising:

2. The Avalon protocol conversion method of claim 1, further comprising:

3. The Avalon protocol conversion method of claim 1, wherein said storing said data in a data cache module comprises:

storing the data into a FIFO;

correspondingly, the reading the data from the data caching module through the controller includes: reading, by a controller, the data from the FIFO.

4. The Avalon protocol conversion method according to claim 3, further comprising:

and if the FIFO is full, suspending receiving data on the Avalon-ST bus.

5. The Avalon protocol conversion method of claim 1, wherein said configuring an Avalon-ST bus channel number comprises:

the Avalon-ST bus channel number is configured to the first register.

6. The Avalon protocol conversion method of claim 5, further comprising:

calculating, by a controller, a write burst address and a burst length based on the write address initial address and a write data length, and transmitting the data and the write burst address and the burst length to an Avalon-MM bus slave module, so that the Avalon-MM bus slave module writes the data to a memory based on the write burst address and the burst length.

7. The Avalon protocol conversion method of claim 6,

and configuring the Avalon-ST bus channel number to a first register through an APB bus, and configuring the write address initial address and the write data length of the Avalon-MM bus to a second register and a third register respectively.

8. The Avalon protocol conversion method of claim 7, wherein the configuring of the Avalon-ST bus channel number to the first register and the write address initial address and write data length of the Avalon-MM bus to the second register and the third register, respectively, via the APB bus comprises:

9. The Avalon protocol conversion method of claim 6, further comprising:

10. The Avalon protocol conversion method of claim 6, further comprising:

11. The Avalon protocol conversion method of claim 10,

the first register, the second register, the third register, the working trigger register, the working state representation register, the unpacker and the data caching module all belong to a module for converting preset Avalon-ST to Avalon-MM.

12. The Avalon protocol conversion method of claim 11, wherein said preset Avalon-ST to Avalon-MM module is connected to said Avalon-MM bus slave module via an Avalon-MM bus.

13. An Avalon protocol conversion device, comprising:

the device comprises a depacketizer and a data caching module, wherein the depacketizer is used for receiving data on an Avalon-ST bus, and storing the data into the data caching module if the channel number of a channel to which the data belongs is consistent with the channel number of the Avalon-ST bus;

and the controller is used for reading the data from the data caching module and transmitting the data to the Avalon-MM bus slave module so that the Avalon-MM bus slave module writes the data into a memory.

14. An electronic device, comprising a storage unit and a processing unit, wherein:

the storage unit is used for storing a computer program;

the processing unit for executing the computer program to implement the Avalon protocol conversion method according to any of claims 1 to 13.

15. A computer-readable storage medium for holding a computer program, wherein the computer program, when executed by a processor, implements the Avalon protocol conversion method according to any one of claims 1 to 13.