CN117807004A - Communication interface for network-on-chip and NandFlash controller - Google Patents
Communication interface for network-on-chip and NandFlash controller Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The communication interface utilizes a request path module to carry out data verification and clock domain crossing processing on a request data packet sent by the network on chip, and then the request data packet is converted to obtain a configuration instruction in an AHB (advanced high performance bus) signal form through a protocol conversion module to complete configuration on the NandFlash controller.
Description
Technical Field
The application relates to the field of integrated circuits, in particular to a communication interface for a network-on-chip and a NandFlash controller.
Background
Along with the continuous downsizing of the processing technology of integrated circuit chips, the development cost and the period are rapidly increased due to the physical properties of chip raw material silicon and the processing difficulty, and accordingly, the moore's law is about to fail. The method greatly shortens the period of chip design and manufacture, but the data packet transmission interaction between a plurality of integrated packaged dies has difficulty and affects the development of the technology.
Disclosure of Invention
Aiming at the problems and the technical requirements, the application provides a communication interface for a network-on-chip and a NandFlash controller, and the technical scheme of the application is as follows:
the communication interface is connected with the NandFlash controller through an AHB interface by connecting the network on the chip with the network on the chip through a network on chip port, and comprises:
the request path module is used for receiving a request data packet transmitted by the network on chip through the network on chip port, and carrying out data verification and clock domain crossing processing on the request data packet; the request data packet is used for requesting to execute corresponding operation on NandFlash;
the protocol conversion module is used for carrying out protocol conversion on the request data packet which is subjected to data verification and cross-clock domain processing to obtain a configuration instruction in the form of an AHB bus signal, and sending the configuration instruction to the NandFlash controller through an AHB interface, wherein the configuration instruction is used for indicating the NandFlash controller to execute corresponding operation on the NandFlash according to the request data packet;
the protocol conversion module is also used for receiving response data in the form of an AHB bus signal sent by the NandFlash controller through an AHB interface when the NandFlash controller completes corresponding operation on the NandFlash according to the request data packet to generate response data, and carrying out protocol conversion on the response data to obtain a response data packet and sending the response data packet to the response path module;
And the response path module is used for feeding back the response data packet to the network-on-chip through the network-on-chip port after the clock domain crossing processing is completed.
The request path module comprises a checking unit and a first FIFO which are sequentially connected, wherein a data input port of the checking unit is connected with an upper network port, a data output port of the checking unit is connected with a data input port of the first FIFO, and a data output port of the first FIFO is connected with the protocol conversion module; the first FIFO is realized by adopting an asynchronous FIFO;
the verification unit caches the request data packet and performs data verification, and when the data verification of the request data packet passes, the verification unit writes the request data packet into the first FIFO; when the data verification of the request data packet is not passed, the verification unit discards the request data packet; the first FIFO buffers the request data packet passing the data verification until the protocol conversion module reads the request data packet from the first FIFO, and the clock domain crossing processing of the request data packet from the network-on-chip side clock domain to the NandFlash controller side clock domain is completed.
The first FIFO has a first word pre-fetching function, and the data of the data output port of the first FIFO is the data pointed by the current internal read pointer of the first FIFO; the inverted FIFO almost full signal is used as a ready signal output to the master device that sent the write request event, and the empty signal is inverted as a full signal output to the master device that sent the read request event.
The further technical scheme is that the verification unit comprises a verification control state machine and a cache queue, and the cache queue is realized by adopting a synchronous FIFO;
the check control state machine sequentially receives each flit in the request data packet, checks each received flit according to the check bit, and for any received flit: when the verification control state machine passes the flit verification, writing the flits into a cache queue, and sequentially receiving the next flit for verification; when the verification control state machine fails to verify the flits, the remaining flits in the request data packet are sequentially received, and after all the flits remaining in the request data packet are received, all the received flits are discarded and the existing flits in the cache queue are emptied, so that the request data packet which fails to verify the data is discarded;
and in the process that the verification control state machine sequentially verifies each micro-slice in the request data packet, shielding the read request of the cache queue until the verification control state machine receives and verifies that all the micro-slices in the request data packet pass through the write-in cache queue, and responding to the read request of the cache queue to read out the request data packet passing through the data verification, and writing the read request into the first FIFO.
The verification unit further comprises a first information register, wherein the verification control state machine is further used for controlling the first information register to register end-to-end confirmation information in the request data packet; the check control state machine is further used for controlling the first information register to send all registered end-to-end confirmation information to the response path module after the data packet is requested to be written into the first FIFO in the cache queue; wherein the end-to-end acknowledgement information is information requesting a predetermined flit in the data packet.
And the response path module is also used for generating a confirmation data packet aiming at the request data packet according to the end-to-end confirmation information, feeding the confirmation data packet back to the network-on-chip through the network-on-chip port, and enabling the confirmation data packet to instruct the communication interface to confirm that the request data packet is received and pass data verification.
The response path module comprises an output control unit, a second FIFO and a confirmation data packet generation unit, wherein the second FIFO is an asynchronous FIFO;
the data input port of the second FIFO is connected with the protocol conversion module and receives the response data packet sent by the protocol conversion module, and after the second FIFO finishes the clock domain crossing processing of the response data packet from the clock domain of the NandFlash controller side to the clock domain of the network-on-chip side, the response data packet is sent to the output control unit through the data output port of the second FIFO;
The confirmation data packet generation unit comprises a second information register, a confirmation data packet control state machine and a confirmation data packet generation logic, wherein the confirmation data packet control state machine controls the second information register to register all end-to-end confirmation information sent by the request path module, and is also used for controlling the second information register to send all registered end-to-end confirmation information to the confirmation data packet generation logic, and is also used for controlling the confirmation data packet generation logic to generate a confirmation data packet according to all received end-to-end confirmation information and send the confirmation data packet to the output control unit;
the output control unit is used for feeding back the received response data packet or the acknowledgement data packet to the network-on-chip through the network-on-chip port, carrying out priority arbitration on the response data packet and the acknowledgement data packet according to the pre-priority when the response data packet and the acknowledgement data packet are received simultaneously, feeding back the conflict data packet with higher priority to the network-on-chip through the network-on-chip port, and waiting for next priority arbitration for the other conflict data packet with lower priority, wherein the two conflict data packets are the response data packet and the acknowledgement data packet which are received simultaneously.
The further technical scheme is that the data package formats of the request data package, the response data package and the confirmation data package are the same, and any one of the request data package, the response data package and the confirmation data package sequentially comprises a head flit, a length flit, an address flit, a plurality of data flits and a tail flit which are sequentially arranged;
the first microchip records an event ID, an event type, an initial network-on-chip ID, a target network-on-chip ID and a buffer network-on-chip ID of an operation event executed by the data packet; the event type of the request data packet is any one of an erasure event, a write data event, a read request event, a DMA write data event, a DMA read request event and a shared write data event; (1) When the event type of the request data packet is an erasure event or a write data event, the event type of the acknowledgement data packet aiming at the request data packet is a write response event; (2) When the event type of the request data packet is a DMA write data event, the event type of the confirmation data packet aiming at the request data packet is a DMA write response event; (3) When the event type of the request data packet is a shared write data event, the event type of the response data packet aiming at the request data packet is an interrupt event; (4) When the event type of the request data packet is a read request event, the event types of the acknowledgement data packet and the response data packet aiming at the request data packet are read response events; (5) When the event type of the request data packet is a DMA read request event, the event types of the acknowledgement data packet and the response data packet aiming at the request data packet are both DMA write response events;
The length body flit carries the data length, the address body flit carries the storage address, and the data body flit carries the data content of the data load;
the trailer is used for marking the end of transmission of the request data packet.
The further technical scheme is that the state transfer method for checking and controlling the state machine comprises the following steps:
(1) After reset, entering an IDLE state for initialization setting, wherein the secondary state is CHECKHEAD;
(2) In CHECKHEAD state, receiving the first flit in the request data packet and checking according to the check bit, when the check of the first flit is passed, the minor state is check-up, when the check of the first flit is not passed, the minor state is ERROR state, and when the first flit is not received, the first flit is kept in CHECKHEAD state;
(3) In the check klen state, receiving a length flit in the request data packet and checking according to the check bit, wherein the minor state is CHECKADDR when the length flit is checked and is ERROR state when the length flit is not checked, and the check klen state is continuously remained when the length flit is not received;
(4) In CHECKADDR state, receiving address flits in the request data packet and checking according to check bits, wherein the minor state is CHECKDATA state when the address flits pass the check and the event type of the request data packet is a write-related event, the minor state is WAITTAIL state when the address flits pass the check and the event type of the request data packet is other event types except the write-related event, the minor state is ERROR state when the address flits do not pass the check, and the address flits stay in CHECKLEN state when the address flits are not received; write related events include write data events, DMA write data events, and shared write data events;
(5) In CHECKDATA state, receiving a data volume flit in a request data packet, checking according to check bits, and counting the data length of the data volume flit; when the data length of the data volume flit is matched with the data length carried by the length volume flit and the data volume flit passes the verification, the minor state is WAITTAIL state, when the data length of the data volume flit is not matched with the data length carried by the length volume flit or the data volume flit does not pass the verification, the minor state is ERROR state, and when the data volume flit is not received or all the data volume flits are not verified, the state is kept in CHECKDATA;
(6) Sequentially receiving the rest flits in the request data packet in the ERROR state, and setting the next state as the CLEAR state after receiving the tail flits, otherwise, continuing to stay in the ERROR state;
(7) In the CLEAR state, discarding all received flits and emptying the flits in the cache queue, so as to discard the request data packet which is not passed by the data verification, wherein the secondary state is an IDLE state;
(8) In the WAITTAIL state, the secondary state after the tail microchip is monitored to be in the RECTAIL state, otherwise, the tail microchip stays in the WAITTAIL state continuously;
(9) In the RECTAIL state, receiving the tail microchip, writing the tail microchip into a cache queue, canceling the read request shielding of the cache queue, and reading out the complete data packet which passes the verification in the cache queue;
(10) In the CHECKDONE state, setting a ready signal to an invalid level to prohibit the input of new flits and wait for all flits in the cache queue to be read out, and controlling the first information register to handshake with the response path module; when the buffer queue is empty and the handshake between the first information register and the response path module is completed, the secondary state is CHECKHEAD, otherwise, the buffer queue stays in the chekdone state.
The protocol conversion module comprises an unpacking logic unit, a protocol conversion control state machine and a packing logic unit;
the unpacking logic unit is used for unpacking the request data packet which is subjected to data check and cross-clock domain processing, extracting unpacked data and sending the unpacked data to the protocol conversion control state machine, wherein the unpacked data comprises event types of the request data packet and data carried by each data body microchip;
the protocol conversion control state machine is used for generating a configuration instruction of the NandFlash controller according to the data carried by each registered data body microchip through the AHB interface according to the event type in the unpacked data;
the protocol conversion control state machine is also used for receiving response data generated by the corresponding operation of the NandFlash to the NandFlash by the configuration instruction executed by the NandFlash controller through the AHB interface and sending the response data to the packing logic unit;
And the packing logic unit is used for packing the response data to generate a response data packet and sending the response data packet to the response path module.
The further technical scheme is that a valid signal and a ready signal are adopted to handshake between a data receiver and a data sender which have a data communication relationship in a communication interface, and the data receiver and the data sender complete handshake when the valid signal and the ready signal are both in an effective level, so that the data communication is realized.
The beneficial technical effects of this application are:
the application discloses a communication interface facing network on chip and NandFlash controller, the communication interface is used for receiving a request data packet of network on chip, after data verification and clock domain crossing processing are carried out by using a request path module, protocol conversion is carried out by using a protocol conversion module to obtain a configuration instruction in the form of AHB bus signals, the effect of completing configuration on the NandFlash controller according to the request data packet is achieved, when the NandFlash controller generates response data for NandFlash operation, the protocol conversion module can also carry out protocol conversion to generate a corresponding response data packet, and the corresponding response data packet is fed back to the network on chip by using the response path module, so that the data packet transmission efficiency between the network on chip and the NandFlash controller can be improved, the expansion and integration of multi-die interconnection to the NandFlash controller can be realized, the difficulty of efficient transmission and interaction of the data packet integrated by multiple dies can be solved, better system performance can be realized under limited power consumption, and a technical foundation is provided for the development of a multi-die integration technology.
Drawings
Fig. 1 is an application scenario diagram of a communication interface of the network-on-chip and NandFlash controller of the present application.
Fig. 2 is a schematic structural diagram of a communication interface facing a network on chip and a NandFlash controller according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a communication interface facing a network on chip and a NandFlash controller according to another embodiment of the present application.
Fig. 4 is a flit structure schematic diagram of a packet structure in one embodiment of the present application.
FIG. 5 is a state transition diagram of a check control state machine in one embodiment of the present application.
Detailed Description
The following describes the embodiments of the present application further with reference to the accompanying drawings.
The application discloses a communication interface for a network-on-chip and a NandFlash controller, please refer to an application scene graph shown in FIG. 1, and the communication interface is connected with the NandFlash controller through an AHB interface by connecting the network-on-chip port with the network-on-chip, so that transfer transmission between the network-on-chip and the NandFlash controller can be realized. The NandFlash controller is connected with and controls the NandFlash. The communication interface is connected with the NandFlash controller through the AHB interface, and is connected with the write-in data port and the read-out data port of the NandFlash controller through the AHB interface.
Referring to fig. 2, the internal structure diagram of the communication interface mainly includes a request path module, a protocol conversion module and a response path module:
the request path module is used for receiving a request data packet transmitted by the network on chip through the network on chip port, carrying out data verification and clock domain crossing processing on the request data packet, and requesting to execute corresponding operation on the NandFlash.
The protocol conversion module is used for carrying out protocol conversion on the request data packet which is subjected to data verification and cross-clock domain processing to obtain a configuration instruction in the form of an AHB bus signal, and sending the configuration instruction to the NandFlash controller through an AHB interface, wherein the configuration instruction is used for indicating the NandFlash controller to execute corresponding operation on the NandFlash according to the request data packet, so that the NandFlash controller can complete corresponding operation on the NandFlash after completing a configuration flow according to the configuration instruction.
The corresponding operations can be mainly divided into three general categories: erase, write, and read. When the NandFlash controller executes corresponding operations related to reading on the NandFlash according to the request data packet, response data is often generated, and the response data includes data to be read. But may not generate response data when the NandFlash controller performs a corresponding operation related to erasing or writing on the NandFlash in accordance with the request packet.
And the protocol conversion module is also used for receiving the response data in the form of an AHB bus signal sent by the NandFlash controller through the AHB interface when the NandFlash controller finishes corresponding operation on the NandFlash according to the request data packet to generate response data, and carrying out protocol conversion on the response data to obtain a response data packet and sending the response data packet to the response path module.
And the response path module is used for feeding back the response data packet to the network-on-chip through the network-on-chip port after the clock domain crossing processing is completed.
In one embodiment, a valid signal and a ready signal are adopted to handshake between a data receiver and a data sender which have data communication relations at will in the communication interface, and handshake is completed when the valid signal and the ready signal are both in an effective level, so that the current data is effectively and successfully transmitted, the data receiver and the data sender are realized to realize data communication, the condition that the data is not lost in the transmission process is ensured, and the reliability of the data transmission is improved.
Next, the following is specifically introduced to three modules in the communication interface respectively:
1. and a request path module.
In one embodiment, please refer to the structure diagram of the request path module shown in fig. 3, the request path module includes a check unit and a first FIFO, which are sequentially connected, a data input port of the check unit is connected to a network port on the connection pad, a data output port of the check unit is connected to a data input port of the first FIFO, a data output port of the first FIFO is connected to the protocol conversion module, and the first FIFO is implemented by using an asynchronous FIFO. The checking unit caches the request data packet and performs data checking, and when the data checking of the request data packet passes, the checking unit writes the request data packet into the first FIFO. Because of the device characteristics of the NandFlash particles, the service life of the NandFlash particles is relatively limited, so that when the data verification of the request data packet fails, the verification unit discards the request data packet and prevents error data from being written into the NandFlash. The first FIFO buffers the request data packet passing the data verification until the protocol conversion module reads the request data packet from the first FIFO, so that the clock domain crossing processing of the request data packet from the network-on-chip side clock domain to the NandFlash controller side clock domain can be completed. The check unit and the first FIFO are described below, respectively.
Check unit
Referring to fig. 3, the check unit includes a check control state machine and a cache queue, and the cache queue is implemented by using a synchronous FIFO.
In the application, the request data packet comprises a plurality of flits which are sequentially arranged, and then the verification control state machine sequentially receives each flit in the request data packet and verifies each received flit according to the verification bit. For any flit received: when the verification control state machine passes the flit verification, the flits are written into the cache queue, and the next flit is received in sequence for verification. When the verification control state machine fails to verify the flits, the rest flits in the request data packet are sequentially received but are not written into the cache queue, and after all the flits in the request data packet are received, all the received flits are discarded and the existing flits in the cache queue are emptied, so that the request data packet which fails to verify the data is discarded.
In the process of sequentially checking each flit in the request data packet by the checking control state machine, the read request of the cache queue is shielded, so that the flit in the cache queue is not allowed to be read out until the data checking of the whole request data packet is completed. And after the verification control state machine receives and verifies that all flits in the request data packet pass and writes the flits into the cache queue, the verification control state machine responds to a read request for the cache queue to read out the request data packet with the passed data verification and writes the request data packet into the first FIFO.
In one embodiment, the request packet sequentially includes a header flit, a plurality of length flits sequentially arranged, an address flit, a plurality of data flits sequentially arranged, and a tail flit, please refer to the schematic diagram shown in fig. 4, and the information carried by each flit includes:
(a) The header flit records an event ID, event type, start network-on-chip ID, destination network-on-chip ID, and buffer network-on-chip ID of an operation event performed by the packet. The start network-on-chip ID in the request packet is the ID of the network-on-chip that sent the request packet, and the destination network-on-chip ID in the request packet is the ID of the network-on-chip that received the request packet. The network-on-chip ID of the buffer is an ID of the network-on-chip for intermediately buffering the request packet. That is, the request packet is sent by the network-on-chip of the starting network-on-chip ID, buffered by the network-on-chip of the buffered network-on-chip ID, and then received by the network-on-chip of the destination network-on-chip ID.
The event type of the request data packet is any one of an erasure event, a write data event, a read request event, a DMA write data event, a DMA read request event and a shared write data event.
(b) The length body flit carries the data length, the address body flit carries the memory address, and the data body flit carries the data content of the data load.
In addition, only one data volume flit can be transmitted on one data link in the network-on-chip within one clock period, so that the transmission paths of a plurality of data volume flits in the network-on-chip are prevented from generating conflicts.
(c) The trailer is used for marking the end of transmission of the request data packet.
Therefore, the check control state can sequentially receive the head flit, the length flit, the address flit, the data flit, the length flit, the address flit and the data flit … … tail flit in the request data packet and sequentially check the request data packet.
In another embodiment, as shown in fig. 3, the verification unit further includes a first information register, where the first information register is used to register data required during operation of the verification unit. In addition, the check control state machine is further configured to control the first information register to register the end-to-end acknowledgement information for subsequent use when the end-to-end acknowledgement information in the request packet is checked. The end-to-end acknowledgement information is information of a predetermined flit in the request packet, where the end-to-end acknowledgement information is usually some flit information carrying important data, and may be preconfigured, for example, in actual application, the end-to-end acknowledgement information includes a header flit, a length flit, and an address flit.
The end-to-end acknowledgement information registered by the first information register in the request path module is mainly used for generating an acknowledgement data packet for the request data packet, wherein the acknowledgement data packet is used for indicating that the communication interface has acknowledged the receipt of the request data packet and passes the data verification. The first information register is thus connected to the response path module and enables data communication. And after the flits cached in the cache queue are read out to the first FIFO, controlling the first information register to send all the registered end-to-end confirmation information to the response path module. The response path module generates a confirmation data packet for the request data packet according to the end-to-end confirmation information, and feeds back the confirmation data packet to the network-on-chip through the network-on-chip port, and the response path module part is described in detail later.
One state transition method for checking the control state machine includes, referring to the state transition diagram shown in fig. 5:
(1) After reset, the device enters an IDLE state for initialization setting, and the secondary state is CHECKHEAD.
(2) And in a CHECKHEAD state, receiving the head flit in the request data packet, checking according to the check bit, and continuously staying in a CHECKHEAD state when the head flit is checked and passed and when the head flit is not checked and passed and the ERROR is detected.
When the end-to-end confirmation information comprises the head flit, the step receives the head flit in the request data packet, checks the head flit according to the check bit, and controls the first information register to register data carried by the head flit.
(3) In the check klen state, the length flit in the request data packet is received and checked according to the check bit, the minor state is CHECKADDR when the length flit is checked and is ERROR state when the length flit is not checked, and the check klen state is continued when the length flit is not received.
When the end-to-end confirmation information comprises the length flit, the step receives the length flit in the request data packet, checks the length flit according to the check bit, and controls the first information register to register the data length carried by the length flit.
(4) In CHECKADDR state, the address flit in the request packet is received and checked according to the check bit, the minor state is CHECKDATA state when the address flit is checked and the event type of the request packet is a write-related event, the minor state is WAITTAIL state when the address flit is checked and the event type of the request packet is other event types except the write-related event, the minor state is ERROR state when the address flit is not checked, and the state is kept CHECKADDR when the address flit is not received.
Write related events include write data events, DMA write data events, and shared write data events. Other event types besides write related events include erase events, read request events, and DMA read request events.
When the end-to-end confirmation information comprises an address body flit, the step receives the address body flit in the request data packet, checks the address body flit according to the check bit, and controls the first information register to register the data address carried by the address body flit.
(5) In CHECKDATA state, receiving the data volume flit in the request data packet, checking according to the check bit, and counting the data length of the data volume flit. The minor state is WAITTAIL state when the data length of the data volume flit is matched with the data length carried by the length volume flit and the data volume flit is checked to pass, the minor state is ERROR state when the data length of the data volume flit is not matched with the data length carried by the length volume flit or the data volume flit is checked to fail, and the state is kept CHECKDATA when the data volume flit is not received or all the data volume flits are not checked.
(6) And in the ERROR state, sequentially receiving the rest flits in the request data packet, and after receiving the tail flits, setting the next state as the CLEAR state, otherwise, continuing to stay in the ERROR state.
(7) In the CLEAR state, all flits received are discarded and the existing flits in the cache queue are emptied, so that the request data packet with failed data verification is discarded, and the next state is an IDLE state.
(8) In the WAITTAIL state, the subsequent state of the tail microchip is detected to be a RECTAIL state, otherwise, the tail microchip stays in the WAITTAIL state.
(9) In the RECTAIL state, receiving the tail flit, writing the tail flit into the cache queue, canceling the read request shielding of the cache queue, and reading out the complete data packet which passes the verification in the cache queue, wherein the minor state is CHECKDONE state.
(10) In the chekdone state, the ready signal is set to an inactive level to disable the input of new flits and wait for all flits in the cache queue to be read out and control the first information register to handshake with the response path module. When the cache queue is empty, which indicates that the flit in the cache queue has been read out into the first FIFO, and the handshake between the first information register and the response path module is completed, the next state is CHECKHEAD. Otherwise, stay in chekdone state.
(II) first FIFO
The first FIFO implements data buffering and cross-clock domain processing. In another embodiment, the first FIFO has a first word prefetch function, i.e. the data of the data output port of the first FIFO is the data pointed to by the current internal read pointer of the first FIFO, and the first FIFO without the first word prefetch function needs to sample the FIFO read request before putting valid read data on the data output port. The first FIFO with the first-word prefetch function is more convenient to handshake with valid/ready signals, and specifically, for the first FIFO with the first-word prefetch function, the inverted FIFO almost full signal is used as a ready signal output to the master device sending the write request event, and the empty signal is inverted as a full signal output to the master device sending the read request event.
2. Protocol conversion module
Referring to fig. 2, the protocol conversion module includes an unpacking logic unit, a protocol conversion control state machine, and a packing logic unit, where:
the unpacking logic unit is used for unpacking the request data packet which is processed by the data check and cross-clock domain processing, extracting unpacked data and sending the unpacked data to the protocol conversion control state machine, wherein the unpacked data comprises event types of the request data packet and data carried by each data volume microchip.
And the protocol conversion control state machine is used for generating a configuration instruction of the NandFlash controller according to the data carried by each registered data volume flit through the AHB interface according to the event type in the unpacked data.
The protocol conversion control state machine is also used for receiving response data generated by the corresponding operation of the NandFlash to the NandFlash by the configuration instruction executed by the NandFlash controller through the AHB interface and sending the response data to the packing logic unit.
And the packing logic unit is used for packing the response data to generate a response data packet and sending the response data packet to the response path module.
The data packet format of the response data packet generated by the packing logic unit is the same as the request data packet, the difference is that the event types in the first flit are different, and the other formats and definitions are the same, so that the embodiment is not repeated. When the event type of the request data packet is a shared write data event, a read request event or a DMA read request event, the protocol conversion module receives corresponding response data and generates a response data packet, and: (1) When the event type of the request data packet is a shared write data event, the event type of the response data packet for the request data packet is an interrupt event. (2) When the event type of the request data packet is a read request event, the event type of the response data packet for the request data packet is a read response event. (3) When the event type of the request data packet is a DMA read request event, the event type of the response data packet for the request data packet is a DMA write response event.
3. Response path module
The response path module includes an output control unit and a second FIFO, please refer to fig. 3. The second FIFO is an asynchronous FIFO and, similar to the first FIFO, may also be configured with a first word prefetch function. The data input port of the second FIFO is connected with the protocol conversion module and receives the response data packet sent by the protocol conversion module, and after the second FIFO finishes the clock domain crossing processing of the response data packet from the clock domain of the NandFlash controller side to the clock domain of the network-on-chip side, the response data packet is sent to the output control unit through the data output port of the second FIFO. And the output control unit is used for feeding back the received response data packet to the network-on-chip through the network-on-chip port.
In an embodiment in which the first information register in the request path module sends the registered end-to-end acknowledgement information to the response path module, the response path module further comprises an acknowledgement packet generating unit. The acknowledgement data packet generation unit comprises a second information register, an acknowledgement data packet control state machine and acknowledgement data packet generation logic, wherein the acknowledgement data packet control state machine is used for controlling the second information register to register all end-to-end acknowledgement information sent by the request path module, and is also used for controlling the second information register to send all registered end-to-end acknowledgement information to the acknowledgement data packet generation logic, and is also used for controlling the acknowledgement data packet generation logic to generate acknowledgement data packets according to all received end-to-end acknowledgement information and send the acknowledgement data packets to the output control unit. The output control unit is further configured to feed back the received acknowledgement packet to the network on chip through the network on chip port.
The data packet format of the acknowledgement data packet generated by the acknowledgement data packet generating unit is the same as the request data packet, except that the event types in the first flit are different, and the other formats and definitions are the same, which is not described in detail in this embodiment. When the event type of the request data packet received by the communication interface is an erasure event, a write data event, a DMA write data event, a read request event and a DMA read request event, the communication interface generates a corresponding confirmation data packet, and: (1) When the event type of the request data packet is an erasure event or a write data event, the event type of the acknowledgement data packet aiming at the request data packet is a write response event; (2) When the event type of the request data packet is a DMA write data event, the event type of the acknowledgement data packet for the request data packet is a DMA write response event. (3) When the event type of the request data packet is a read request event, the event type of the acknowledgement data packet aiming at the request data packet is a read response event; (4) When the event type of the request data packet is a DMA read request event, the event type of the acknowledgement data packet for the request data packet is a DMA write response event.
In practical application, when the output control unit receives the response data packet and the acknowledgement data packet at the same time, the output control unit arbitrates the priority of the response data packet and the acknowledgement data packet according to the priority in advance, feeds back the conflict data packet with higher priority to the network-on-chip through the network-on-chip port, and waits for the next priority arbitration for the conflict data packet with lower priority, wherein the two conflict data packets are the response data packet and the acknowledgement data packet which are received at the same time.
The above are only preferred embodiments of the present application, and the present application is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present application are to be considered as being included within the scope of the present application.
Claims (10)
1. The utility model provides a communication interface towards network on chip and NandFlash controller which characterized in that, the communication interface connects NandFlash controller through network on the network on chip port connection piece, through AHB interface, the communication interface includes:
the request path module is used for receiving a request data packet transmitted by the network-on-chip through the network-on-chip port and carrying out data check and clock domain crossing processing on the request data packet; the request data packet is used for requesting to execute corresponding operation on NandFlash;
the protocol conversion module is used for carrying out protocol conversion on a request data packet which is subjected to data verification and cross-clock domain processing to obtain a configuration instruction in the form of an AHB bus signal, and sending the configuration instruction to the NandFlash controller through the AHB interface, wherein the configuration instruction is used for indicating the NandFlash controller to execute corresponding operation on the NandFlash according to the request data packet;
The protocol conversion module is further used for receiving response data in the form of an AHB bus signal sent by the NandFlash controller through the AHB interface when the NandFlash controller completes corresponding operation on the NandFlash according to the request data packet to generate response data, and carrying out protocol conversion on the response data to obtain a response data packet and sending the response data packet to the response path module;
and the response path module is used for feeding back the response data packet to the network-on-chip through the network-on-chip port after the clock domain crossing processing is completed.
2. The communication interface of claim 1, wherein the request path module comprises a check unit and a first FIFO connected in sequence, a data input port of the check unit being connected to the network-on-chip port, a data output port of the check unit being connected to a data input port of the first FIFO, a data output port of the first FIFO being connected to the protocol conversion module; the first FIFO is realized by adopting an asynchronous FIFO;
the verification unit caches the request data packet and performs data verification, and when the data verification of the request data packet passes, the verification unit writes the request data packet into a first FIFO; when the data verification of the request data packet is not passed, the verification unit discards the request data packet; and the first FIFO buffers the request data packet passing the data verification until the protocol conversion module reads the request data packet from the first FIFO, so as to finish the clock domain crossing processing of the request data packet from the network-on-chip side clock domain to the NandFlash controller side clock domain.
3. The communication interface of claim 2, wherein the first FIFO has a first word prefetch function, and the data at the data output port of the first FIFO is the data pointed to by the current first FIFO internal read pointer; the inverted FIFO almost full signal is used as a ready signal output to the master device that sent the write request event, and the empty signal is inverted as a full signal output to the master device that sent the read request event.
4. The communication interface of claim 2, wherein the check unit comprises a check control state machine and a cache queue, the cache queue implemented with a synchronous FIFO;
the check control state machine sequentially receives each flit in the request data packet, checks each received flit according to the check bit, and for any received flit: when the verification control state machine passes the verification of the flit, writing the flit into the cache queue, and sequentially receiving the next flit for verification; when the verification control state machine fails to verify the flits, sequentially receiving the rest flits in the request data packet, discarding all the received flits and emptying the existing flits in the cache queue after receiving all the rest flits in the request data packet, so as to discard the request data packet with failed data verification;
And in the process that the verification control state machine sequentially verifies each flit in the request data packet, shielding a read request of the cache queue until the verification control state machine receives and verifies that all flits in the request data packet pass the write-in of the cache queue, and then responding to the read request of the cache queue to read out the request data packet passing the data verification and write the read request into the first FIFO.
5. The communication interface of claim 4, wherein the verification unit further comprises a first information register, the verification control state machine further configured to control the first information register to register end-to-end acknowledgement information in the request packet; the check control state machine is further configured to control the first information register to send all the end-to-end acknowledgement information registered to the response path module after the data packet is requested to be written into the first FIFO in the buffer queue; wherein the end-to-end acknowledgement information is information of a predetermined flit in the request packet;
the response path module is further configured to generate a confirmation data packet for the request data packet according to the end-to-end confirmation information, and feed back the confirmation data packet to the network-on-chip through the network-on-chip port, where the confirmation data packet is used to instruct the communication interface to confirm that the request data packet is received and pass data verification.
6. The communication interface of claim 5, wherein the response path module comprises an output control unit, a second FIFO, and an acknowledgement packet generation unit, the second FIFO being an asynchronous FIFO;
the data input port of the second FIFO is connected with the protocol conversion module and receives a response data packet sent by the protocol conversion module, and after the second FIFO finishes the clock domain crossing processing of the response data packet from the clock domain of the NandFlash controller side to the clock domain of the network-on-chip side, the response data packet is sent to the output control unit through the data output port of the second FIFO;
the acknowledgement data packet generating unit comprises a second information register, an acknowledgement data packet control state machine and acknowledgement data packet generating logic, the acknowledgement data packet control state machine controls the second information register to register all end-to-end acknowledgement information sent by the request path module, the acknowledgement data packet control state machine is also used for controlling the second information register to send all registered end-to-end acknowledgement information to the acknowledgement data packet generating logic, and the acknowledgement data packet control state machine is also used for controlling the acknowledgement data packet generating logic to generate acknowledgement data packets according to all received end-to-end acknowledgement information and send the acknowledgement data packets to the output control unit;
The output control unit is used for feeding back the received response data packet or the acknowledgement data packet to the network-on-chip through the network-on-chip port, carrying out priority arbitration on the response data packet and the acknowledgement data packet according to the pre-priority when the response data packet and the acknowledgement data packet are received simultaneously, feeding back the conflict data packet with higher priority to the network-on-chip through the network-on-chip port, and waiting for next priority arbitration for the conflict data packet with lower priority, wherein the two conflict data packets are the response data packet and the acknowledgement data packet which are received simultaneously.
7. The communication interface of claim 5, wherein the data packets of the request packet, the response packet and the acknowledgement packet have the same format, and any one of the request packet, the response packet and the acknowledgement packet sequentially comprises a header flit, a length flit, an address flit, a plurality of sequentially arranged data flits and a tail flit;
the first flit records an event ID, an event type, an initial network-on-chip ID, a target network-on-chip ID and a buffer network-on-chip ID of an operation event executed by the data packet; the event type of the request data packet is any one of an erasure event, a write data event, a read request event, a DMA write data event, a DMA read request event and a shared write data event; (1) When the event type of the request data packet is an erasure event or a write data event, the event type of the acknowledgement data packet aiming at the request data packet is a write response event; (2) When the event type of a request data packet is a DMA write data event, the event type of a confirmation data packet aiming at the request data packet is a DMA write response event; (3) When the event type of a request data packet is a shared write data event, the event type of a response data packet aiming at the request data packet is an interrupt event; (4) When the event type of the request data packet is a read request event, the event types of the acknowledgement data packet and the response data packet aiming at the request data packet are read response events; (5) When the event type of the request data packet is a DMA read request event, the event types of the acknowledgement data packet and the response data packet aiming at the request data packet are both DMA write response events;
The length body flit carries the data length, the address body flit carries the storage address, and the data body flit carries the data content of the data load;
the tail flit is used for marking the transmission end of the request data packet.
8. The communication interface of claim 7, wherein the state transition method of the check control state machine comprises:
(1) After reset, entering an IDLE state for initialization setting, wherein the secondary state is CHECKHEAD;
(2) In CHECKHEAD state, receiving the first flit in the request data packet and checking according to the check bit, when the check of the first flit is passed, the minor state is check-up, when the check of the first flit is not passed, the minor state is ERROR state, and when the first flit is not received, the first flit is kept in CHECKHEAD state;
(3) In the check klen state, receiving a length flit in the request data packet and checking according to the check bit, wherein the minor state is CHECKADDR when the length flit is checked and is ERROR state when the length flit is not checked, and the check klen state is continuously remained when the length flit is not received;
(4) In CHECKADDR state, receiving address flits in the request data packet and checking according to check bits, wherein the minor state is CHECKDATA state when the address flits pass the check and the event type of the request data packet is a write-related event, the minor state is WAITTAIL state when the address flits pass the check and the event type of the request data packet is other event types except the write-related event, the minor state is ERROR state when the address flits do not pass the check, and the address flits stay in CHECKLEN state when the address flits are not received; write related events include write data events, DMA write data events, and shared write data events;
(5) In CHECKDATA state, receiving a data volume flit in a request data packet, checking according to check bits, and counting the data length of the data volume flit; when the data length of the data volume flit is matched with the data length carried by the length volume flit and the data volume flit passes the verification, the minor state is WAITTAIL state, when the data length of the data volume flit is not matched with the data length carried by the length volume flit or the data volume flit does not pass the verification, the minor state is ERROR state, and when the data volume flit is not received or all the data volume flits are not verified, the state is kept in CHECKDATA;
(6) Sequentially receiving the rest flits in the request data packet in an ERROR state, and setting the next state as a CLEAR state after receiving the tail flits, otherwise, continuing to stay in the ERROR state;
(7) In the CLEAR state, discarding all received flits and emptying the prior flits in the cache queue, thereby discarding the request data packet which is not passed by the data verification, and the minor state is an IDLE state;
(8) In the WAITTAIL state, the secondary state after the tail microchip is monitored to be in the RECTAIL state, otherwise, the tail microchip stays in the WAITTAIL state continuously;
(9) In the RECTAIL state, receiving the tail microchip, writing the tail microchip into a cache queue, canceling the read request shielding of the cache queue, and reading out the complete data packet which passes the verification in the cache queue;
(10) In the CHECKDONE state, setting a ready signal to an invalid level to prohibit the input of new flits and wait for all flits in a cache queue to be read out, and controlling the first information register to handshake with the response path module; and when the cache queue is empty and the handshake between the first information register and the response path module is completed, the secondary state is CHECKHEAD, otherwise, the first information register is kept in the CHECKDONE state.
9. The communication interface of claim 7, wherein the protocol conversion module comprises an unpacking logic unit, a protocol conversion control state machine, and a packing logic unit;
the unpacking logic unit is used for unpacking the request data packet which is subjected to data check and cross-clock domain processing, extracting unpacked data and sending the unpacked data to the protocol conversion control state machine, wherein the unpacked data comprises event types of the request data packet and data carried by each data volume microchip;
the protocol conversion control state machine is used for generating a configuration instruction of the NandFlash controller according to the data carried by each registered data body microchip through an AHB interface according to the event type in the unpacked data;
the protocol conversion control state machine is further used for receiving response data generated by the corresponding operation of the NandFlash to the NandFlash by the configuration instruction executed by the NandFlash controller through the AHB interface and sending the response data to the packing logic unit;
And the packing logic unit is used for packing the response data to generate a response data packet and sending the response data packet to the response path module.
10. The communication interface of claim 7, wherein a valid signal and a ready signal are adopted to handshake between a data receiver and a data sender in the communication interface, and the valid signal and the ready signal are both at active levels to complete handshake, so that the data receiver and the data sender realize data communication.
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| CN118568025B (en) * | 2024-08-02 | 2024-10-01 | 中国电子科技集团公司第五十八研究所 | Memory management communication interface for network-on-chip and DDR controller |
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