CN115694469A

CN115694469A - MIPI interface circuit and control method, chip and terminal thereof

Info

Publication number: CN115694469A
Application number: CN202110875833.2A
Authority: CN
Inventors: 黄泽; 胡国宇
Original assignee: Galaxycore Shanghai Ltd Corp
Current assignee: Galaxycore Shanghai Ltd Corp
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2023-02-03

Abstract

An MIPI interface circuit and its control method, chip, terminal, MIPI interface circuit includes: the first switch unit is used for conducting in a high-speed mode, and a first end of the first switch unit is connected with a power supply voltage; the high-speed driver is used for driving and outputting a high-speed signal in the high-speed mode, and an input end of the high-speed driver is coupled to the second end of the first switch unit; the second switch unit is used for being conducted in the high-speed mode, a first end of the second switch unit is coupled with an output end of the high-speed driver, and a second end of the second switch unit is grounded; and the low-power-consumption driver is used for driving and outputting the low-power-consumption signal in a low-power-consumption mode. The technical scheme of the invention can solve the problem of insufficient withstand voltage of the MOS tube in the transmitting interface driver.

Description

MIPI interface circuit and control method, chip and terminal thereof

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an MIPI interface circuit and a control method, a chip and a terminal thereof.

Background

Mobile Industry Processor Interface (MIPI) is an open standard and a specification established by the MIPI alliance for Mobile application processors.

In the MIPI protocol D physical layer (D-PHY) or C physical layer (C-PHY), an output port may output a High Speed (HS) mode signal and a Low Power (LP) mode signal. As shown in fig. 1, in the conventional MIPI interface circuit, a high-speed mode signal and a low-power mode signal are driven by an HS driver and an LP driver (shown in dotted lines in fig. 1), respectively. The output voltage swing of the LP mode is 0-1.2V, and the output voltage swing of the HS mode is 0.1-0.3V. Under the non-advanced process, the voltage of the internal analog power supply of the chip is 1.2V.

However, with the use of advanced processes (e.g., 28nm process), the voltage of the analog power supply inside the chip is reduced. If the HS driver uses the chip inner tube with advanced manufacturing process, the source-drain withstand voltage of the chip inner tube is less than 1.2V, so that the MOS tube in the HS driver bears unsafe source-drain voltage when the sending interface works in the LP mode.

Disclosure of Invention

The invention solves the technical problem of insufficient voltage resistance of an MOS tube in a transmitting interface driver.

In order to solve the above technical problem, an embodiment of the present invention provides a method for controlling an MIPI interface circuit, where the MIPI interface circuit includes: a high speed driver, a first switching unit, a second switching unit and a low power consumption driver; the first end of the first switch unit is connected to a power supply voltage; the input end of the high-speed driver is coupled with the second end of the first switch unit; the first end of the second switch unit is coupled with the output end of the high-speed driver, and the second end of the second switch unit is grounded; the control method of the MIPI interface circuit comprises the following steps: controlling the high-speed driver to work in a high-speed mode through the first time sequence control signal and outputting a high-speed signal; the first switch unit is controlled to be switched on or switched off through a second time sequence control signal; the second switch unit is controlled to be switched on or switched off through a third time sequence control signal; and controlling the low-power-consumption driver to work in a low-power-consumption mode through the fourth timing control signal so as to drive and output a low-power-consumption signal in the low-power-consumption mode.

In order to solve the above technical problem, an embodiment of the present invention further discloses an MIPI interface circuit, where the MIPI interface circuit includes: the first switch unit is used for being conducted in a high-speed mode, and a first end of the first switch unit is connected to a power supply voltage; the high-speed driver is used for driving and outputting a high-speed signal in the high-speed mode, and an input end of the high-speed driver is coupled to the second end of the first switch unit; the second switch unit is used for conducting in the high-speed mode, a first end of the second switch unit is coupled with the output end of the high-speed driver, and a second end of the second switch unit is grounded; and the low-power-consumption driver is used for driving and outputting the low-power-consumption signal in a low-power-consumption mode.

Optionally, the MIPI interface circuit further includes: and the mode switching unit is used for controlling the first switch unit to be conducted in a high-speed mode and controlling the second switch unit to be conducted in the high-speed mode according to the working mode of the interface circuit.

Optionally, an output end of the mode switching unit outputs a mode control voltage, and the mode control voltage controls the first switch unit and the second switch unit to be in an on state in the high-speed mode and to be in an off state in the low-power mode.

Optionally, the mode switching unit includes: a first input end of the NOR gate is connected with a first control voltage, and a second input end of the NOR gate is connected with a second control voltage; a first input end of the NAND gate is coupled with an output end of the NOR gate, and a second input end of the NAND gate is connected with a third control voltage; and the input end of the NOT gate is coupled with the output end of the NAND gate, and the output end of the NOT gate outputs the mode control voltage.

Optionally, the high-speed driver includes a plurality of high-speed driving units connected in parallel, an input end of each high-speed driving unit is coupled to the second end of the corresponding first switching unit, and an output end of each high-speed driving unit is coupled to the first end of the corresponding second switching unit; or the input end of each high-speed driving unit is coupled with the second end of the corresponding first switch unit, and the output end of each high-speed driving unit is coupled with the first end of the same second switch unit; or the input end of each high-speed driving unit is coupled with the second end of the same first switch unit, and the output end of each high-speed driving unit is coupled with the first end of the corresponding second switch unit; or, the input end of each high-speed driving unit is coupled to the second end of the same first switch unit, and the output end of each high-speed driving unit is coupled to the first end of the same second switch unit.

Optionally, the first switch unit includes a first NMOS transistor, a gate of the first NMOS transistor is connected to a first control voltage, a source of the first NMOS transistor is coupled to an input terminal of the high-speed driver, and a drain of the first NMOS transistor is connected to a power supply voltage; the second switch unit comprises a second NMOS tube, the grid electrode of the second NMOS tube is connected with a second control voltage, the drain electrode of the second NMOS tube is coupled with the output end of the high-speed driver, and the source electrode of the second NMOS tube is grounded.

Optionally, the number of the first NMOS transistors is one or more, and the first NMOS transistors are connected in parallel or in series: the number of the second NMOS tubes is one or more, and the second NMOS tubes are mutually connected in parallel or in series.

Optionally, the first switch unit includes a first resistor, the second switch unit includes a second resistor, the number of the first resistors is one or more, and the plurality of first resistors are connected in parallel or in series: the number of the second resistors is one or more, and the plurality of second resistors are mutually connected in parallel or in series.

Optionally, the number of the first switch units is one or more, and the plurality of first switch units are connected in parallel or in series: the number of the second switch units is one or more, and the second switch units are mutually connected in parallel or in series.

The embodiment of the invention also discloses a chip which comprises the MIPI interface circuit.

The embodiment of the invention also discloses a terminal which comprises the MIPI interface circuit.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the technical scheme of the invention, the MIPI interface circuit comprises a first switch unit which is used for conducting in a high-speed mode, and the first end of the first switch unit is connected with a power supply voltage; the high-speed driver is used for driving and outputting a high-speed signal in the high-speed mode, and an input end of the high-speed driver is coupled to the second end of the first switch unit; the second switch unit is used for conducting in the high-speed mode, a first end of the second switch unit is coupled with the output end of the high-speed driver, and a second end of the second switch unit is grounded; and the low-power-consumption driver is used for driving and outputting the low-power-consumption signal in a low-power-consumption mode. According to the technical scheme, the first switch unit and the second switch unit are arranged and are in different states in different modes, so that the source-drain end voltage of the internal tube of the high-speed driver is smaller, the problem of insufficient voltage resistance of the MOS tube in the high-speed driver is avoided, normal work of the high-speed driver is guaranteed, and driving performance is improved.

Drawings

Fig. 1 is a schematic diagram of a MIPI interface circuit in the prior art;

fig. 2 is a schematic structural diagram of an MIPI interface circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a specific structure of an MIPI interface circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of another MIPI interface circuit according to another embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a mode switching unit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a mode switching unit according to an embodiment of the present invention;

FIG. 7 is a timing diagram of signals according to one embodiment of the present invention;

FIG. 8 is a timing diagram of another embodiment of the present invention.

Detailed Description

As described in the background, with the use of advanced processes (e.g., 28nm processes), the voltage of the on-chip analog power supply is reduced. If the HS driver uses the chip inner tube with advanced manufacturing process, the source-drain withstand voltage of the chip inner tube is less than 1.2V, so that the MOS tube in the HS driver bears unsafe source-drain voltage when the sending interface works in the LP mode.

The inventor of the present application finds, through research, that in the conventional MIPI interface circuit shown in fig. 1, when the interface operates in the low power consumption mode, the output voltage Vout swings in a range of 0 to 1.2V, and at this time, the input signal Vup = Vdn =0 (i.e., the control signal B) of the high-speed driver, and the MOS transistor in the high-speed driver may bear an unsafe source-drain voltage of 1.2V.

According to the technical scheme, the first switch unit and the second switch unit are arranged and are in different states in different modes, so that the source-drain voltage of the internal tube of the high-speed driver is smaller, the problem of insufficient withstand voltage of the MOS tube in the high-speed driver is solved, normal work of the high-speed driver is guaranteed, and driving performance is improved.

The high-speed mode (which may also be referred to as a high-speed signal mode) in the embodiments of the present invention is used for high-speed data transmission, for example, the transmission rate is 80Mbps to 1Gbps/Lane.

The low power consumption mode (also called as a low power consumption signal mode) in the embodiment of the invention is used for control, and the power consumption is generally low, for example, the maximum transmission frequency is 10MHz.

Accordingly, the high-speed driver in the embodiments of the present invention refers to a driver capable of operating in a high-speed mode, and the output signal may be referred to as a high-speed signal. In the embodiment of the present invention, the low power consumption driver refers to a driver capable of operating in a low power consumption mode, and an output signal may be referred to as a low power consumption signal.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 is a schematic structural diagram of an MIPI interface circuit according to an embodiment of the present invention.

The MIPI interface circuit comprises a first switch unit and a second switch unit which are respectively used for conducting in a high-speed mode. The first terminal of the first switch unit is connected to the power voltage VX400, the first terminal of the second switch unit is coupled to the output terminal of the high-speed driver 20, and the second terminal of the second switch unit is grounded AVSS.

In fig. 2, the first switching unit is exemplified by a MOS transistor MN1, and the second switching unit is exemplified by a MOS transistor MN 2.

It should be understood by those skilled in the art that the first switching unit and the second switching unit may be any other practicable switching devices besides MOS transistors, and the embodiment of the present invention is not limited thereto.

An output signal Vout of the MIPI interface circuit may be a high-speed signal or a low-power consumption signal. With continued reference to fig. 2, the mipi interface circuit further includes a high-speed driver 20 for driving and outputting a high-speed signal in a high-speed mode, wherein an input terminal of the high-speed driver 20 is coupled to the second terminal of the MOS transistor MN 1. The MIPI interface circuit further comprises a low power driver 21 (shown in dotted line in fig. 2) for driving an output low power signal in a low power mode.

In a specific implementation, the drain of the MOS transistor MN1 is connected to the power voltage VX400, and the source of the MOS transistor MN1 is coupled to one end of the high-speed driver 20. The drain of the MOS transistor MN2 is coupled to the other end of the high-speed driver 20, and the source of the MOS transistor MN2 is grounded AVSS. The gate of the MOS transistor MN1 and the gate of the MOS transistor MN2 are connected to the control voltage Vsw. The control voltage Vsw is a combination of the low power consumption control-related signal and the high speed control-related signal.

In specific implementation, the device types of the MOS transistor MN1 and the MOS transistor MN2 may be a chip internal (core) transistor, and may also be an input/output (IO) transistor. The core tube is selected, so that the on-resistance is small, and the performance of the interface is better when the interface works in a high-speed mode. The IO tube is selected, so that the source-drain voltage resistance is high, and the high-speed driver is safer when the interface works at low power consumption. The gate control voltages of the MOS transistor MN1 and the MOS transistor MN2 may be the same or different. The related power supply voltage only needs to ensure the normal work of the circuit, and the others have no limitation.

It should be noted that the high-speed driver of the embodiment of the present invention may be D-PHY, may be C-PHY, or may be a combination of D-PHY and C-PHY (C/D-PHY Combo).

In a non-limiting embodiment of the present invention, the MIPI interface circuit may further include a mode switching unit (not shown) for controlling the first switching unit to be turned on in the high speed mode and controlling the second switching unit to be turned on in the high speed mode according to an operation mode of the interface circuit

Further, the output terminal of the mode switching unit outputs a mode control voltage (i.e., the aforementioned control voltage Vsw) that controls the first switching unit and the second switching unit to be in an on state in the high speed mode and to be in an off state in the low power consumption mode.

In one embodiment, in the MIPI interface circuit shown in fig. 3 and 4, the high-speed driver 20 includes a plurality of high-speed driving units connected in parallel, an input terminal of each high-speed driving unit is coupled to the second terminal of the corresponding first switching unit, and an output terminal of each high-speed driving unit is coupled to the first terminal of the corresponding second switching unit; or the input end of each high-speed driving unit is coupled with the second end of the corresponding first switch unit, and the output end of each high-speed driving unit is coupled with the first end of the same second switch unit; or the input end of each high-speed driving unit is coupled with the second end of the same first switch unit, and the output end of each high-speed driving unit is coupled with the first end of the corresponding second switch unit; or, the input end of each high-speed driving unit is coupled to the second end of the same first switch unit, and the output end of each high-speed driving unit is coupled to the first end of the same second switch unit.

In a non-limiting embodiment of the present invention, referring to fig. 5, fig. 5 shows an input signal and an output signal of the mode switching unit. The input Signals of the mode switching unit include a first Control voltage Vlpdp, a second Control voltage Vlpdn, a third Control voltage Vhsen, and a Control signal a (Control Signals a), and the output Signals of the mode switching unit include a mode Control voltage Vsw and a Control signal B (Control Signals B), and the Control signal B is used for being input to the high speed driver 20.

In one non-limiting embodiment of the present invention, the mode switching unit includes: a first input end of the NOR gate is connected with a first control voltage, and a second input end of the NOR gate is connected with a second control voltage; a first input end of the NAND gate is coupled with an output end of the NOR gate, and a second input end of the NAND gate is connected with a third control voltage; and the input end of the NOT gate is coupled with the output end of the NAND gate, and the output end of the NOT gate outputs the mode control voltage.

Referring to fig. 6, in the specific structure of the mode switching unit, a first input terminal of the nor gate O1 is connected to the first control voltage Vlpdp, a second input terminal of the nor gate O1 is connected to the second control voltage Vlpdn, a first input terminal of the nand gate A1 is coupled to an output terminal of the nor gate O1, and a second input terminal of the nand gate A1 is connected to the third control voltage Vhsen. The input end of the not gate N1 is coupled to the output end of the nand gate A1, and the output end of the not gate N1 outputs the mode control voltage Vsw.

Further, the mode switching unit may also provide the control signals B of the high speed driver 20, i.e. the input voltages Vup and Vdn. Specifically, the input end of the not gate N2 is connected to the fourth control voltage Vupa, the output end of the not gate N1 is coupled to the first input end of the nand gate A2, the second input end of the nand gate A2 is connected to the third control voltage Vhsen, and the output end of the nand gate A2 outputs the voltage Vup. The input end of the not gate N3 is connected to the fifth control voltage Vdna, the output end of the not gate N3 is coupled to the first input end of the nand gate A3, the second input end of the nand gate A3 is connected to the third control voltage Vhsen, and the output end of the nand gate A3 outputs the voltage Vdn.

In this embodiment, when the MIPI transmitter operates in a high-speed mode (HS mode), the input voltages Vlpdp and Vlpdn of the low power consumption driver 21 are both 0 (that is, the first control voltage and the second control voltage are both 0), and the mode control voltage Vsw is the power supply voltage AVDD. The input voltage Vup = Vupa (fourth control voltage), and the input voltage Vdn = Vdna (fifth control voltage). At this time, the control signal B of the high-speed driver 20 acts. When the MIPI transmitter operates in a low power mode (LP mode), the third control voltage Vhsen =0, the mode control voltage Vsw =0, the input voltage Vup = AVDD, the input voltage Vdn = AVDD, the control signal of the high-speed driver 20 is pulled high, and the high-speed driver 20 outputs a high impedance state.

Fig. 7 shows a timing chart of each signal in the High Speed Mode (High Speed Mode). The first control voltage Vlpdp and the second control voltage Vlpdn are 0, the third control voltage Vhsen is high, the control signal a and the control signal B are in an active state, and the control voltage Vsw is the power supply voltage AVDD. The control signal a and the control signal B are in an active state, which may mean that the corresponding MOS transistors can be controlled to be turned on.

Referring to fig. 3, when the MIPI transmitter operates in the high speed mode (HS mode), the input voltages Vlpdp and Vlpdn (i.e. the first control voltage and the second control voltage) of the low power consumption driver 21 are both 0, and the low power consumption driver 21 outputs the high impedance state. Meanwhile, the mode control voltage Vsw is the power supply voltage AVDD, the MOS transistor MN1 and the MOS transistor MN2 are turned on, and the high-speed driver 20 operates normally.

In another embodiment, referring to fig. 4, when the MIPI transmitter operates in a high speed mode (HS mode), the input voltages Vlpdp and Vlpdn of the low power consumption driver 21 are both 0, and the low power consumption driver 21 outputs a high impedance state. Meanwhile, the mode control voltage Vsw is the power supply voltage AVDD, the MOS transistor MN1 and the MOS transistor MN2 are turned on, and the high-speed driver 20 operates normally.

Fig. 8 shows a timing chart of respective signals in the Low Power Mode (Low Power Mode). The first control voltage Vlpdp and the second control voltage Vlpdn are in an active state, the third control voltage Vhsen is at a low level, the control signal a is in an active state, the control signal B is in an inactive state, and the control voltage Vsw is at a low level. The control signal B being in an inactive state may refer to being able to control the corresponding MOS transistor to turn off.

Referring to fig. 3, when the MIPI transmitter operates in a low power mode (LP mode), the mode control voltage Vsw is 0, the MOS transistor MN1 and the MOS transistor MN2 are turned off, and the high-speed driver 20 outputs a high impedance state. The low power consumption driver 21 operates normally. At this time, the source terminal voltage of the MOS transistor MN4 in the high-speed driver 20 is slightly lower than the power supply voltage AVDD, so as to ensure that the source-drain voltage of the MOS transistor MN4 is within a safe range.

In another embodiment, referring to fig. 4, when the MIPI transmitter operates in a low power mode (LP mode), the mode control voltage Vsw is 0, the MOS transistor MN1 and the MOS transistor MN2 are turned off, and the high-speed driver 20 outputs a high impedance state. The low power consumption driver 21 operates normally. At this time, the source end voltages of the MOS transistors MN4 and MN6 in the high-speed driver 20 are slightly lower than the power supply voltage AVDD, so as to ensure that the source-drain voltages of the MOS transistors MN4 and MN6 are within a safe range.

In a non-limiting embodiment of the present invention, the number of the first NMOS transistors (i.e. MOS transistor MN 1) is one or more, and a plurality of the first NMOS transistors are connected in parallel or in series with each other: the number of the second NMOS tubes (namely the MOS tubes MN 2) is one or more, and the second NMOS tubes are mutually connected in parallel or in series. The control voltages connected to the gates of the first NMOS transistors may be the same or different; the control voltages connected to the gates of the second NMOS transistors may be the same or different.

The embodiment of the invention also discloses a control method of the MIPI interface circuit, which is a time sequence control method and specifically comprises the following steps: controlling the high-speed driver to work in a high-speed mode through the first time sequence control signal and outputting a high-speed signal; the first switch unit is controlled to be switched on or switched off through a second time sequence control signal; the second switch unit is controlled to be switched on or switched off through a third time sequence control signal; and controlling the low-power-consumption driver to work in a low-power-consumption mode through the fourth timing control signal so as to drive and output a low-power-consumption signal in the low-power-consumption mode.

It should be noted that the sequence numbers of the steps in this embodiment do not represent a limitation on the execution sequence of the steps.

In a specific implementation, when the high-speed driver is controlled to work in a high-speed mode, the first switch unit and the second switch unit are controlled to be conducted; and when the low-power-consumption driver is controlled to work in a low-power-consumption mode, the first switch unit and the second switch unit are controlled to be turned off.

In an implementation, the first timing control signal may be the first control voltage vpdp, the second control voltage vpdn, the control signal B, and the mode control voltage Vsw in the foregoing embodiment.

The second and third timing control signals may be the mode control voltage Vsw in the foregoing embodiment.

The fourth timing control signal may be the first control voltage vpdp, the second control voltage vpdn, the control signal B, and the mode control voltage Vsw in the foregoing embodiment.

It can be understood that, with respect to the timing relationship among the first timing control signal, the second timing control signal, the third timing control signal and the fourth timing control signal, reference may be made to the description of the foregoing embodiments, and details are not repeated herein.

The embodiment of the invention also discloses a chip which comprises the MIPI interface circuit. The chip may be a single chip component or may be a chip module.

The embodiment of the invention also discloses a terminal piece, and the terminal comprises the MIPI interface circuit. . The terminal includes, but is not limited to, a mobile phone, a computer, a tablet computer and other terminal devices.

The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A control method of an MIPI interface circuit is characterized in that the MIPI interface circuit comprises the following steps: a high speed driver, a first switching unit, a second switching unit and a low power consumption driver; the first end of the first switch unit is connected with a power supply voltage; the input end of the high-speed driver is coupled with the second end of the first switch unit; the first end of the second switch unit is coupled with the output end of the high-speed driver, and the second end of the second switch unit is grounded; the control method comprises the following steps:

controlling the high-speed driver to work in a high-speed mode through the first time sequence control signal and outputting a high-speed signal;

the first switch unit is controlled to be switched on or switched off through a second time sequence control signal;

the second switch unit is controlled to be switched on or switched off through a third time sequence control signal;

and controlling the low-power-consumption driver to work in a low-power-consumption mode through the fourth timing control signal so as to drive and output a low-power-consumption signal in the low-power-consumption mode.

2. An MIPI interface circuit, comprising:

the first switch unit is used for conducting in a high-speed mode, and a first end of the first switch unit is connected with a power supply voltage;

the high-speed driver is used for driving and outputting a high-speed signal in the high-speed mode, and an input end of the high-speed driver is coupled to the second end of the first switch unit;

the second switch unit is used for conducting in the high-speed mode, a first end of the second switch unit is coupled with the output end of the high-speed driver, and a second end of the second switch unit is grounded;

and the low-power-consumption driver is used for driving and outputting the low-power-consumption signal in a low-power-consumption mode.

3. The MIPI interface circuit of claim 2, further comprising:

and the mode switching unit is used for controlling the first switch unit to be conducted in a high-speed mode and controlling the second switch unit to be conducted in the high-speed mode according to the working mode of the interface circuit.

4. The MIPI interface circuit of claim 3, wherein an output terminal of the mode switching unit outputs a mode control voltage, the mode control voltage controlling the first switching unit and the second switching unit to be in a turned-on state in the high-speed mode and to be in a turned-off state in the low-power consumption mode.

5. The MIPI interface circuit of claim 4, wherein the mode switching unit comprises:

a first input end of the NOR gate is connected with a first control voltage, and a second input end of the NOR gate is connected with a second control voltage;

the first input end of the NAND gate is coupled with the output end of the NOR gate, and the second input end of the NAND gate is connected with a third control voltage;

and the input end of the NOT gate is coupled with the output end of the NAND gate, and the output end of the NOT gate outputs the mode control voltage.

6. The MIPI interface circuit of claim 2, wherein the high-speed driver includes a plurality of parallel high-speed driving units, an input terminal of each high-speed driving unit is coupled to the second terminal of the corresponding first switching unit, and an output terminal of each high-speed driving unit is coupled to the first terminal of the corresponding second switching unit; or the input end of each high-speed driving unit is coupled with the second end of the corresponding first switch unit, and the output end of each high-speed driving unit is coupled with the first end of the same second switch unit; or the input end of each high-speed driving unit is coupled with the second end of the same first switch unit, and the output end of each high-speed driving unit is coupled with the first end of the corresponding second switch unit; or, the input end of each high-speed driving unit is coupled to the second end of the same first switch unit, and the output end of each high-speed driving unit is coupled to the first end of the same second switch unit.

7. The MIPI interface circuit of claim 2, wherein the first switch unit comprises a first NMOS transistor, a gate of the first NMOS transistor is connected to a first control voltage, a source of the first NMOS transistor is coupled to an input terminal of the high-speed driver, and a drain of the first NMOS transistor is connected to a power supply voltage; the second switch unit comprises a second NMOS tube, the grid electrode of the second NMOS tube is connected with a second control voltage, the drain electrode of the second NMOS tube is coupled with the output end of the high-speed driver, and the source electrode of the second NMOS tube is grounded.

8. The MIPI interface circuit of claim 7, wherein the number of the first NMOS transistors is one or more, and a plurality of first NMOS transistors are connected in parallel or in series with each other: the number of the second NMOS tubes is one or more, and the second NMOS tubes are mutually connected in parallel or in series.

9. The MIPI interface circuit of claim 2, wherein the first switch unit includes a first resistor, the second switch unit includes a second resistor, the number of the first resistors is one or more, a plurality of the first resistors are connected in parallel or in series with each other: the number of the second resistors is one or more, and the plurality of second resistors are mutually connected in parallel or in series.

10. The MIPI interface circuit of claim 2, wherein the number of the first switch units is one or more, and a plurality of the first switch units are connected in parallel or in series with each other: the number of the second switch units is one or more, and the second switch units are mutually connected in parallel or in series.

11. A chip comprising the MIPI interface circuit of any one of claims 2 to 10.

12. A terminal, characterized by comprising the MIPI interface circuit of any one of claims 2 to 10.