CN115692506A - A gate-all-round transistor and its manufacturing method - Google Patents

Abstract

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for improving the working performance of the gate-all-around transistor. The gate-all-around transistor includes: the semiconductor device comprises a semiconductor substrate, an active structure, a first gate stack structure and a second gate stack structure. An active structure is formed on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region between the source region and the drain region. And the first gate stack structure and the second gate stack structure sequentially surround the periphery of the channel region along the direction from the source region to the drain region. The first work function layer included by the first gate stack structure and the second work function layer included by the second gate stack structure are made of materials which are completely different, and the first work function layer and the second work function layer are non-pinch-off layers. The manufacturing method of the gate-all-around transistor is used for manufacturing the gate-all-around transistor.

Description

A gate-all-round transistor and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a gate-around transistor and a manufacturing method thereof.

Background technique

Compared with planar transistors and fin field effect transistors, gate-all-around transistors have advantages such as higher gate control capability, and can improve the working performance of semiconductor devices including the gate-all-around transistors.

However, in an actual application process, the performance improvement of the gate-all-around transistor is not ideal.

Contents of the invention

The object of the present invention is to provide a gate-all-around transistor and a manufacturing method thereof, which are used to improve the working performance of the gate-all-round transistor.

In order to achieve the above object, the present invention provides a gate-all-around transistor, which includes: a semiconductor substrate, an active structure, a first gate stack structure and a second gate stack structure.

The above active structure is formed on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region between the source region and the drain region. Along the direction from the source region to the drain region, the first gate stack structure and the second gate stack structure surround the periphery of the channel region in turn. The materials of the first work function layer included in the first gate stack structure and the second work function layer included in the second gate stack structure are completely different, and both the first work function layer and the second work function layer are non-pinching layers.

Compared with the prior art, in the gate-around transistor provided by the present invention, along the direction from the source region to the drain region, the first gate stack structure and the second gate stack structure surround the periphery of the channel region in sequence. Moreover, the materials of the first work function layer included in the first gate stack structure and the second work function layer included in the second gate stack structure are completely different. Based on this, because the work function values of the work function layers of different materials are different, and the one with the smaller work function value has a lower ability to bind electrons, and the one with a larger work function value has a higher ability to bind electrons, Therefore, a built-in electric field can be formed between the first work function layer and the second work function layer when the gate-all-around transistor is in the on state. In this case, in the actual application process, the work function values of the first work function layer and the second work function layer can be adjusted to enhance the electric field at the source through the built-in electric field and improve the drain-induced barrier lowering effect , to improve the working performance of the gate-around transistor. Alternatively, the work function values of the first work function layer and the second work function layer can also be adjusted to reduce the electric field at the drain through the built-in electric field, improve the hot carrier injection effect, and improve the working performance of the gate-all-around transistor.

The present invention also provides a method for manufacturing a gate-all-round transistor, which includes:

A semiconductor substrate is provided.

Active structures are formed on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region between the source region and the drain region.

Along the direction from the source region to the drain region, a first gate stack structure and a second gate stack structure surrounding the periphery of the channel region are sequentially formed. The materials of the first work function layer included in the first gate stack structure and the second work function layer included in the second gate stack structure are completely different, and both the first work function layer and the second work function layer are non-pinching layers.

Compared with the prior art, for the beneficial effects of the manufacturing method of the gate-all-around transistor provided by the present invention, reference may be made to the analysis of the beneficial effect of the gate-all-around transistor described above, and details are not repeated here.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

Fig. 1 is a structural schematic diagram after forming a fin structure in an embodiment of the present invention;

FIG. 2 is a schematic structural diagram after forming a sacrificial gate and gate sidewalls in an embodiment of the present invention;

3 is a schematic longitudinal cross-sectional view of a structure after forming a source region and a drain region in an embodiment of the present invention;

4 is a schematic longitudinal cross-sectional view of a structure after forming a dielectric layer in an embodiment of the present invention;

5 is a schematic longitudinal cross-sectional view of the structure after forming the channel region in the embodiment of the present invention;

6 is a schematic longitudinal cross-sectional view of the structure after forming the first gate stack material in an embodiment of the present invention;

7 is a schematic longitudinal cross-sectional view of the structure after the first gate stack structure is formed in an embodiment of the present invention;

8 is a schematic longitudinal cross-sectional view of the structure after removing the mask layer in the embodiment of the present invention;

9 is a schematic longitudinal cross-sectional view of the first structure after forming the second gate stack structure in an embodiment of the present invention;

10 is a schematic longitudinal cross-sectional view of the structure after forming the first gate dielectric layer and the second gate dielectric layer in the embodiment of the present invention;

11 is a schematic longitudinal cross-sectional view of the structure after forming the first work function layer and the second work function layer in the embodiment of the present invention;

12 is a schematic longitudinal cross-sectional view of the structure after forming the first gate stack structure and the second gate stack structure in the embodiment of the present invention;

FIG. 13 is a flowchart of a method for manufacturing a gate-all-around transistor provided by an embodiment of the present invention.

Reference numerals: 11 is a semiconductor substrate, 12 is a shallow trench isolation structure, 13 is a fin structure, 131 is a stacked layer, 1311 is a sacrificial layer, 1312 is a channel layer, 14 is a source formation region, 15 is a drain formation region, 16 is a transition region, 17 is a sacrificial gate, 18 is a gate spacer, 19 is a source region, 20 is a drain region, 21 is a dielectric layer, 22 is a channel region, 221 is a nanowire/sheet, and 23 is the first Gate stack material, 24 is a mask layer, 25 is a first gate stack structure, 251 is a first gate dielectric layer, 252 is a first work function layer, 253 is a first gate metal layer, 26 is a second gate stack structure, 261 is a second gate dielectric layer, 262 is a second work function layer, and 263 is a second gate metal layer.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more than one, unless otherwise clearly and specifically defined.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, and it may be the internal communication of two elements or the interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

The gate-all-around transistor includes a channel region having at least one layer of nanowires/sheets. Each layer of nanowires/sheets has a gap with the semiconductor substrate. Moreover, when the channel region includes at least two layers of nanowires/sheets, there are gaps between adjacent nanowires/sheets. Based on this, the gate stack structure included in the gate-all-around transistor can surround the outer periphery of each layer of nanowires/sheets through the aforementioned gap. In other words, the gate stack structure included in the gate-all-around transistor can not only be formed on the top of each layer of nanowires/sheets and the sidewalls along the width direction, but also can be formed on the bottom of each layer of nanowires/sheets, so the gate-around Compared with planar transistors and fin field effect transistors, transistors have advantages such as higher gate control capability, and can improve the working performance of semiconductor devices including the gate-around transistors.

However, in the actual application process, the improvement of the working performance of the gate-all-around transistor is not ideal. For example, take the gate-around transistor as an example of an input-output transistor for illustration: when the gate length of the gate-around transistor is further reduced, the electric field strength between the source region and the drain region of the input-output transistor is relatively large, making the load The carriers gain more energy from the electric field, causing the energy of the carriers to no longer maintain a state of thermal equilibrium. Moreover, when the energy of the carrier exceeds the interface barrier between the semiconductor substrate and the gate dielectric layer, it will be injected into the gate dielectric layer, thereby generating interface states, gate dielectric layer defects or being trapped by defects, making the gate dielectric layer The charge increases or fluctuates unstable, which in turn leads to gate leakage, making it difficult to improve the working performance of the gate-all-around transistor. Another example: take the gate-all-round transistor as the core transistor for example: when the gate length of the gate-all-around transistor is further reduced, the length of the channel region decreases and the voltage V _ds increases, so that the power consumption of the drain junction and the source junction When the best layer is close, the electric force line in the channel can cross from the drain region to the source region, and cause the source barrier height to decrease, thereby increasing the number of carriers injected into the channel from the source region, resulting in an increase in the drain current, and finally making The gate-around transistor cannot be turned off.

In order to solve the above technical problems, an embodiment of the present invention provides a gate-all-around transistor and a manufacturing method thereof. Wherein, in the gate-all-around transistor provided by the embodiment of the present invention, the materials of the first work function layer included in the first gate stack structure and the second work function layer included in the second gate stack structure are completely different, so as to improve the gate-all-around transistor. work performance.

As shown in FIG. 9 and FIG. 12 , the gate-all-around transistor provided by the embodiment of the present invention includes: a semiconductor substrate 11 , an active structure, a first gate stack structure 25 and a second gate stack structure 26 . The aforementioned active structures are formed on the semiconductor substrate 11 . The active structure includes a source region 19 , a drain region 20 , and a channel region 22 between the source region 19 and the drain region 20 . Along the direction from the source region 19 to the drain region 20 , the first gate stack structure 25 and the second gate stack structure 26 surround the periphery of the channel region 22 in turn. The materials of the first work function layer 252 included in the first gate stack structure 25 and the second work function layer 262 included in the second gate stack structure 26 are completely different, and both the first work function layer 252 and the second work function layer 262 are non- pinch fault.

Specifically, the specific structure of the above-mentioned semiconductor substrate can be set according to actual application scenarios. For example, the semiconductor substrate may be a silicon substrate, a silicon germanium substrate, a germanium substrate, a silicon-on-insulator substrate, and the like without other structures formed thereon. Another example: if the gate-all-around transistor provided by the embodiment of the present invention is applied to a second-layer or higher-layer gate-all-around transistor included in an integrated circuit, the semiconductor substrate may at least include a semiconductor substrate, a first layer formed on the semiconductor substrate A device structure, and a dielectric layer covering the first layer of the device structure. In this case, the materials of each part included in the semiconductor substrate can be set according to actual needs, as long as they can be applied to the gate-all-around transistor provided by the embodiment of the present invention.

For the above active structure, in terms of materials, the material of the source region, drain region and channel region included in the active structure may be semiconductor materials such as silicon, silicon germanium, germanium or III-V compounds. Specifically, the materials of the source region and the drain region may be the same or different. Wherein, when the materials of the source region and the drain region are the same, the source region and the drain region can be formed simultaneously in a unified operation step, which simplifies the manufacturing process of the gate-around transistor.

Structurally, the channel region includes at least one layer of nanowires/sheets. Wherein, the number of layers of nanowires/sheets included in the channel region can be set according to actual application scenarios, and is not specifically limited here. In addition, each layer of nanowires/sheets has a gap with the semiconductor substrate. Moreover, in the case that the channel region includes at least two layers of nanowires/sheets, there are gaps between adjacent two layers of nanowires/sheets. The first gate stack structure and the second gate stack structure included in the gate-all-around transistor surround the periphery of each nanowire/sheet through the above-mentioned gap, so the size of the above-mentioned gap can be determined according to the size of the first gate stack structure and the second gate stack structure. Specification.

For the above first gate stack structure and the second gate stack structure, the first gate stack structure may only include the first gate dielectric layer and the first work function layer. Wherein, the first gate dielectric layer is formed on the outer periphery of each nanowire/sheet close to the source region. The material of the first gate dielectric layer may be insulating materials such as HfO ₂ , ZrO ₂ , TiO ₂ or Al ₂ O ₃ . The above-mentioned first work function layer is formed on the first gate dielectric layer. The material of the first work function layer may be a conductive material such as TiN, TaN or TiSiN. Wherein, as shown in FIG. 9 and FIG. 10 , the fact that the first work function layer 252 is a non-pinching layer means that in an actual application process, the actual thickness of the first work function layer 252 formed on the first gate dielectric layer 251 is equal to The initial design thickness of the first work function layer 252 . In other words, in the actual manufacturing process, after the first work function layer 252 is formed on the first gate dielectric layer 251, the above-mentioned gaps are just filled or not filled. In addition, as shown in FIGS. 9 and 10 , the first gate stack structure 25 may further include a first gate metal layer 253 . At this time, the first gate dielectric layer 251 , the first work function layer 252 and the first gate metal layer 253 included in the first gate stack structure 25 jointly fill up the part of the gap near the source region 19 . Wherein, the material of the first gate metal layer 253 may be a conductive material such as tungsten, silver, gold or platinum.

As for the second gate stack structure, the second gate stack structure may only include the second gate dielectric layer and the second work function layer. Wherein, the second gate dielectric layer is formed on the periphery of each layer of nanowires/sheets close to the drain region. The second work function layer is formed on the second gate dielectric layer. In addition, as shown in FIGS. 9 and 10 , the second gate stack structure 26 may further include a second gate metal layer 263 . Wherein, the meaning of the second work function layer 262 being a non-pinching layer can be referred to above, and will not be repeated here. Moreover, the materials of the second gate dielectric layer 261 and the second gate metal layer 263 can be determined by referring to the materials of the first gate dielectric layer 251 and the first gate metal layer 253 mentioned above, and are not specifically limited here. Specifically, the material of the first gate dielectric layer 251 may be the same as or different from that of the second gate dielectric layer 261 . The material of the first gate dielectric metal layer may be the same as or different from that of the second gate metal layer 263 .

The type of material of the second work function layer can be set according to the material of the first work function layer and actual requirements. Based on this, because the work function values of the work function layers of different materials are different, and the one with the smaller work function value has a lower ability to bind electrons, and the one with a larger work function value has a higher ability to bind electrons, Therefore, when the gate-all-around transistor is on and the materials of the first work function layer and the second work function layer are completely different, a built-in electric field is formed between the first work function layer and the second work function layer of different materials. . In this case, in the actual application process, the work function values of the first work function layer and the second work function layer can be adjusted to enhance the electric field at the source through the above-mentioned built-in electric field and improve the drain-induced barrier lowering effect , to improve the working performance of the gate-around transistor. Alternatively, the work function values of the first work function layer and the second work function layer can also be adjusted to reduce the electric field at the drain through the built-in electric field, improve the hot carrier injection effect, and improve the working performance of the gate-all-around transistor.

It can be seen that the specific materials of the first work function layer and the second work function layer can be based on the specific type of the corresponding effect in the gate-around transistor to be improved in the actual application scene, as well as the conductivity type of the gate-around transistor and each work function material The work function value is determined.

In one example, when the above-mentioned gate-around transistor is a core transistor, since the thickness of the gate dielectric layer included in the core gate-around transistor is relatively small, as the core transistor is further scaled down, the leakage induced in the core transistor The barrier lowering effect is more pronounced. Based on this, in this case, when the gate-around transistor is an N-type gate-around transistor, the work function value of the first work function layer is greater than the work function value of the second work function layer. At this time, when the gate-around transistor is in an on state, the potential of the drain region is higher than that of the source region. And the work function value of the first work function layer is greater than the work function value of the second work function layer. Based on this, the direction of the built-in electric field generated between the first work function layer and the second work function layer includes the direction from the drain region to the source region, so that the electric field at the source terminal can be enhanced through the built-in electric field, and the drain of the gate-around transistor can be improved. induced barrier-lowering effect.

In this case, when the gate-around transistor is a P-type transistor, the work function value of the first work function layer is smaller than the work function value of the second work function layer. For the analysis of the working principle in this case, reference may be made to the previous analysis of the principle of the N-type gate-all-round transistor in this case, and details will not be repeated here.

Of course, in addition to the core transistor, as long as there is a drain-induced barrier lowering effect in the gate-around transistor, the above-mentioned method can be used for adjustment.

In another example, when the above-mentioned gate-around transistor is an input-output transistor, since the thickness of the gate dielectric layer included in the input-output transistor is relatively large, with the further scaling of the input-output transistor, the The hot carrier injection effect is more obvious. Based on this, when the gate-around transistor is an N-type gate-around transistor, the work function value of the first work function layer is smaller than the work function value of the second work function layer. At this time, when the gate-around transistor is in an on state, the potential of the drain region is higher than that of the source region. And the work function value of the first work function layer is smaller than the work function value of the second work function layer. Based on this, the direction of the built-in electric field generated between the first work function layer and the second work function layer includes the direction from the source region to the drain region, so that the electric field at the drain terminal can be reduced by the built-in electric field, and the thermal stability of the gate-around transistor can be improved. Carrier injection effect.

In this case, when the gate-around transistor is a P-type gate-around transistor, the work function value of the first work function layer is greater than the work function value of the second work function layer. For the analysis of the working principle in this case, reference may be made to the previous analysis of the principle of the N-type gate-all-round transistor in this case, and details will not be repeated here.

Of course, in addition to the input and output transistors, as long as there is a drain-induced barrier lowering effect in the gate-around transistor, the above-mentioned method can be used for adjustment.

Wherein, the work function values corresponding to the above-mentioned first work function layer and the second work function layer, and the work function difference between them can be set according to actual application scenarios, and are not specifically limited here.

Exemplarily, the work function value of the first work function layer and/or the work function value of the second work function layer are greater than 3.9 eV and less than 5.2 eV. In this case, because the work function value corresponding to the material of the work function layer of the gate-all-around transistor is mostly in the range of 3.9eV to 5.2eV, the work function value of the first work function layer and/or the work function value of the second work function layer When the function value is greater than 3.9eV and less than 5.2eV, it is convenient to manufacture the first work function layer and the second work function layer by using known materials, reducing the manufacturing difficulty of the gate-all-around transistor.

Exemplarily, the absolute value of the work function difference between the first work function layer and the second work function layer is greater than or equal to 0.3 eV and less than or equal to 0.9 eV. In the actual application process, within a certain range, the greater the absolute value of the work function difference between the first work function layer and the second work function layer, the greater the field strength of the built-in electric field formed between the two. Correspondingly, the degree to which the leakage-induced barrier lowering effect can be improved or the hot carrier injection effect can be improved is greater. However, when the field strength of the built-in electric field formed between the two is greater, the degree of influence on the threshold voltage of the gate-around transistor will also increase. Based on this, when the absolute value of the work function difference between the first work function layer and the second work function layer is greater than or equal to 0.3eV and less than or equal to 0.9eV, the absolute value of the work function difference between the two The value is moderate, which can prevent the hot carrier injection effect or leakage-induced barrier lowering effect from being difficult to suppress due to the small absolute value. At the same time, it can also prevent the threshold voltage of the gate-around transistor from failing to meet the working requirement due to the large absolute value.

In the actual application process, along the length direction of the channel region, the specific lengths of the first gate stack structure and the second gate stack structure, and the proportional relationship between the lengths of the two can be set according to actual needs, which will not be discussed here. Specific limits. Exemplarily, the ratio of the length of the first gate stack structure to the length of the second gate stack structure may range from 1:2 to 4:1. At this time, the ratio between the length of the first gate stack structure and the length of the second gate stack structure has a certain optional range, so that the length of the first gate stack structure and the length of the second gate stack structure can be adjusted according to different actual application scenarios. The length of the structure is set to a corresponding range, which improves the applicability of the gate-all-around transistor provided by the embodiment of the present invention in different application scenarios.

Wherein, preferably, the ratio between the length of the first gate stack structure and the length of the second gate stack structure is 1:1. At this time, the length of the first gate stack structure is equal to the length of the second gate stack structure. Correspondingly, the formation space of the first gate stack structure is equal to the size of the formation space of the second gate stack structure, so as to prevent the difficulty of lowering the drain terminal due to the different lengths of the first gate stack structure and the second gate stack structure. The degree of the electric field or the degree of the source electric field to be enhanced determines the work function values of the first work function layer and the second work function layer, and the corresponding materials.

In addition, the thicknesses of the first gate dielectric layer included in the first gate stack structure and the second gate dielectric layer included in the second gate stack structure may be the same or different. Based on this, along the length direction of the channel region, the first gate dielectric layer is closer to the source region, and the second gate dielectric layer is closer to the drain region. Moreover, since the field strength is inversely proportional to the thickness of the gate dielectric layer, when the thicknesses of the first gate dielectric layer and the second gate dielectric layer are different, the thickness of the first gate dielectric layer can be set to be smaller than that of the second gate dielectric layer. Thickness, so that by reducing the thickness of the first gate dielectric layer, the electric field at the source terminal can be further enhanced, and the drain-induced barrier reduction effect of the gate-around transistor can be improved; and the thickness of the second gate dielectric layer can be increased , to further reduce the electric field at the drain end, and improve the hot carrier injection effect of the gate-all-around transistor.

In some cases, as shown in FIG. 1 , FIG. 9 and FIG. 12 , the above-mentioned gate-all-around transistor further includes a shallow trench isolation structure 12 , a gate spacer 18 and a dielectric layer 21 . Wherein, the above-mentioned shallow trench isolation structure 12 is formed on the semiconductor substrate 11 for isolating different active regions of the semiconductor substrate 11 to prevent electric leakage. The thickness of the shallow trench isolation structure 12 can be set according to actual conditions. The material of the shallow trench isolation structure 12 may be an insulating material such as SiN, Si ₃ N ₄ , SiO ₂ or SiCO. The gate spacer 18 is formed at least on the side of the first gate stack structure 25 close to the source region 19 and the side of the second gate stack structure 26 close to the drain region 20, so that the first gate stack structure 25 and the second gate The stacked structure 26 is isolated from other conductive structures formed later, so as to improve the electrical characteristics of the gate-around transistor. The material of the gate spacer 18 can be an insulating material such as silicon oxide or silicon nitride. The dielectric layer 21 covers the semiconductor substrate 11 and its top is flush with the tops of the first gate stack structure and the second gate stack structure. In the actual manufacturing process, the presence of the dielectric layer 21 can protect the source region 19 and the drain region 20 from subsequent operations such as removing the sacrificial gate and the sacrificial layer, and improve the yield of the gate-around transistor. The material of the dielectric layer 21 may be insulating materials such as silicon oxide or silicon nitride.

As shown in FIG. 13 , an embodiment of the present invention provides a method for manufacturing a gate-all-around transistor. Hereinafter, the manufacturing process will be described based on perspective views or cross-sectional views of operations shown in FIGS. 1 to 12 . Specifically, the manufacturing method of the gate-around transistor includes:

First, a semiconductor substrate is provided. Specifically, for the specific structure and material of the semiconductor substrate, reference may be made to the foregoing, which will not be repeated here.

As shown in FIG. 5 , an active structure is formed on a semiconductor substrate 11 . The active structure includes a source region 19 , a drain region 20 , and a channel region 22 between the source region 19 and the drain region 20 .

Specifically, information such as the specific structure and material of the source region, the drain region and the channel region included in the active structure can be referred to above, and will not be repeated here.

In practical applications, processes such as epitaxial growth, photolithography and etching can be used to form fins on the semiconductor substrate. A shallow trench isolation structure is formed on the part of the semiconductor substrate exposed outside the fins by using processes such as deposition and etching. Wherein, the part of the fin exposed outside the shallow trench isolation structure is a fin structure. As shown in FIG. 1 , along the thickness direction of the semiconductor substrate 11 , the fin structure 13 includes at least one stacked layer 131 . Each layer stack 131 includes a sacrificial layer 1311 and a channel layer 1312 on the sacrificial layer 1311 . Specifically, the above-mentioned channel layer 1312 is used to manufacture the film layer of nanowires/sheets included in the channel region, so the number of layers of the stack 131 included in the fin structure 13 is equal to the number of layers of nanowires/sheets included in the channel region Number, the material and thickness of each channel layer 1312 are respectively equal to the material and thickness of the corresponding nanowire/sheet. In addition, the material of the sacrificial layer 1311 may be any semiconductor material different from that of the channel layer 1312 . For example: when the material of the channel layer 1312 is silicon, the material of the sacrificial layer 1311 is silicon germanium.

Next, as shown in FIG. 1 , along the length direction of the fin structure 13 , the fin structure 13 includes a source forming region 14 , a drain forming region 15 , and a transition region 16 between the source forming region 14 and the drain forming region 15 . As shown in FIG. 2 , the sacrificial gate 17 and the gate sidewall 18 across the portion of the fin structure 13 corresponding to the transition region can be sequentially formed by using processes such as deposition and etching. The material of the sacrificial gate 17 may be easily removable material such as polysilicon. The gate spacer 18 is at least located on both sides of the sacrificial gate 17 along the length direction, and the material of the gate spacer 18 can be referred to above, and will not be repeated here. Then, the portion of the fin structure located in the source formation region and the drain formation region may be removed under the mask effect of the sacrificial gate and the gate spacer. And as shown in FIG. 3 , a source region 19 and a drain region 20 are respectively formed on both sides of the remaining part of the fin structure along the length direction of the fin structure by adopting epitaxial growth and other processes. As shown in FIG. 4 , the dielectric layer 21 covering the semiconductor substrate 11 can be formed by using processes such as deposition and chemical mechanical polishing. The top of the dielectric layer 21 is flush with the top of the sacrificial gate 17 . Finally, as shown in Figure 5, the sacrificial gate and the part of the sacrificial layer located in the transition region are sequentially removed by wet etching or dry etching, so that the part of each channel layer located in the transition region forms a corresponding layer Nanowires/sheets 221, obtaining active structures.

It should be noted that the above active structure can be formed in various ways. How to form the above active structure is not the main feature of the present invention, so in this specification, it is only briefly introduced so that those skilled in the art can easily implement the present invention. Those skilled in the art can completely imagine other ways to manufacture the above-mentioned active structure.

As shown in FIG. 9 and FIG. 12 , along the direction from the source region 19 to the drain region 20 , a first gate stack structure 25 and a second gate stack structure 26 surrounding the outer periphery of the channel region 22 are formed in sequence. The materials of the first work function layer 252 included in the first gate stack structure 25 and the second work function layer 262 included in the second gate stack structure 26 are completely different, and both the first work function layer 252 and the second work function layer 262 are non- pinch fault.

Specifically, information such as each structure included in the first gate stack structure and the second gate stack structure, and materials of each structure can be referred to above, and will not be repeated here. In addition, the sequence of forming the first gate stack structure and the second gate stack structure can be determined according to actual needs, and is not specifically limited here.

In one example, along the length direction of the channel region, the channel region has a first region and a second region. The first gate stack structure surrounds the periphery of the first region, and the second gate stack structure surrounds the periphery of the second region. In this case, when the first gate stack structure is formed before the second gate stack structure, along the direction from the source region to the drain region, the first gate stack structure and the second gate stack structure surrounding the outer periphery of the channel region are sequentially formed. The structure may include the following steps: as shown in FIG. 6 , forming a first gate stack material 23 surrounding the periphery of the first region and the second region. Specifically, processes such as atomic layer deposition can be used to form the first gate dielectric material (for manufacturing the first gate dielectric layer), the first work function material (for manufacturing the first work function material) and the first work function material (for manufacturing the first functional layer), and the first gate metal material (for manufacturing the first gate metal layer). The parts of the first gate dielectric material, the first work function material and the first gate metal material exposed outside the gate region are removed by chemical mechanical polishing and other processes to obtain the first gate stack material 23 . Next, a process such as photolithography may be used to form a mask layer on a portion of the first gate stack material corresponding to the first region. Wherein, the mask layer may be formed only on the part of the first gate stack material corresponding to the first region, or may also be formed on the part of the dielectric layer corresponding to the source region. Then, as shown in FIG. 7 , under the masking effect of the mask layer 24, wet etching or dry etching is used to selectively remove the part of the first gate stack material located on the periphery of the second region, so that the first gate stack material A remaining portion of the gate stack material forms the first gate stack structure 25 . And as shown in FIG. 8 , the mask layer is removed by wet etching or dry etching. Finally, as shown in FIG. 9 , a second gate stack structure 26 surrounding the periphery of the second region is formed. Specifically, processes such as atomic layer deposition can be used to form the second gate dielectric material (for manufacturing the second gate dielectric layer), the second work function material (for manufacturing the second work function layer), and the second gate metal material (for manufacturing the second gate metal layer). The exposed parts of the second gate dielectric material, the second work function material and the second gate metal material outside the gate region are removed by chemical mechanical polishing and other processes to obtain the second gate stack structure 26 .

Of course, the above method may also be adopted, first forming the second gate stack structure surrounding the periphery of the second region in the channel region, and then forming the first gate stack structure surrounding the periphery of the first region in the channel region.

In another example, when the first gate stack structure and the second gate stack structure are formed at the same time, along the direction from the source region to the drain region, the first gate stack structure and the first gate stack structure surrounding the periphery of the channel region are sequentially formed. The second gate stack structure may include the following steps: as shown in FIG. 10 , sequentially forming the first gate dielectric layer 251 included in the first gate stack structure 25 on the periphery of the channel region 22 along the direction from the source region 19 to the drain region 20 and the second gate dielectric layer 261 included in the second gate stack structure 26 . As shown in FIG. 11 , the first work function layer 252 on the first gate dielectric layer 251 and the second work function layer 262 on the second gate dielectric layer 261 are sequentially formed.

Specifically, in this case, when the material and thickness of the first gate dielectric layer and the second gate dielectric layer are the same, the first gate dielectric layer and the second gate dielectric layer can be formed simultaneously by using processes such as atomic layer deposition.

When the thickness and/or material of the first gate dielectric layer and the second gate dielectric layer are different, along the length direction of the channel region, the channel region has a first region and a second region. And the first gate stack structure surrounds the periphery of the first region, and the second gate stack structure surrounds the periphery of the second region. For illustration: the first gate dielectric material surrounding the first region and the second region may be formed first. And selectively remove the part of the first gate dielectric material corresponding to the second region to obtain the first gate dielectric layer. Next, a second gate dielectric material covering the first gate dielectric layer and the second region is formed by using a process such as atomic layer deposition. Then, under the effect of the mask of the corresponding mask layer, the second gate dielectric material is selectively etched, and only the part of the second gate dielectric material located on the periphery of the second region is reserved, so as to obtain the second gate dielectric layer. Wherein, the forming sequence of the first gate dielectric layer and the second gate dielectric layer can be interchanged.

Finally, the first work function layer and the second work function layer may also be sequentially formed in this way. Wherein, the formation order of the above-mentioned first work function layer and the second work function layer may also be interchanged. In addition, as shown in FIG. 12 , in the case where the first gate stack structure 25 and the second gate stack structure 26 further include a first gate metal layer 253 and a second gate metal layer 263 , processes such as physical vapor deposition can also be used. A first gate metal layer 253 and a second gate metal layer 263 are formed to obtain a first gate stack structure 25 and a second gate stack structure 26 .

Compared with the prior art, for the beneficial effects of the gate-all-around transistor provided by the embodiment of the present invention, reference may be made to the analysis of the beneficial effect of the gate-all-around transistor described above, and details will not be repeated here.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (11)

1. A gate-around transistor, characterized in that it comprises: a semiconductor substrate, an active structure formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region between the source region and the drain region; Along the direction from the source region to the drain region, the first gate stack structure and the second gate stack structure surrounding the outer periphery of the channel region are sequentially surrounded; the first gate stack structure includes the first work function layer and the The materials of the second work function layer included in the second gate stack structure are completely different, and both the first work function layer and the second work function layer are non-pinching layers. 2. The gate-all-around transistor according to claim 1, wherein when the gate-all-around transistor is a core transistor, When the gate-around transistor is an N-type gate-around transistor, the work function value of the first work function layer is greater than the work function value of the second work function layer; When the gate-around transistor is a P-type gate-around transistor, the work function value of the first work function layer is smaller than the work function value of the second work function layer. 3. The gate-all-around transistor according to claim 1, wherein when the gate-all-around transistor is an input-output transistor, When the gate-around transistor is an N-type gate-around transistor, the work function value of the first work function layer is smaller than the work function value of the second work function layer; When the gate-around transistor is a P-type gate-around transistor, the work function value of the first work function layer is greater than the work function value of the second work function layer. 4. The gate-all-around transistor according to any one of claims 1 to 3, wherein the work function value of the first work function layer and/or the work function value of the second work function layer is greater than 3.9 eV , and less than 5.2eV. 5. The gate-all-around transistor according to any one of claims 1 to 3, wherein the absolute value of the work function difference between the first work function layer and the second work function layer is greater than or equal to 0.3 eV, and less than or equal to 0.9eV. 6. The gate-all-round transistor according to any one of claims 1-3, wherein a ratio of the length of the first gate stack structure to the length of the second gate stack structure ranges from 1:2 to 4:1. 7. The gate-all-around transistor according to any one of claims 1-3, wherein the first gate dielectric layer included in the first gate stack structure and the second gate dielectric layer included in the second gate stack structure The layers differ in material and/or thickness. 8. The gate-all-around transistor according to claim 7, wherein the thickness of the first gate dielectric layer is smaller than the thickness of the second gate dielectric layer. 9. A method for manufacturing a gate-around transistor, comprising: providing a semiconductor substrate; forming an active structure on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region between the source region and the drain region; Along the direction from the source region to the drain region, a first gate stack structure and a second gate stack structure surrounding the periphery of the channel region are sequentially formed; the first gate stack structure includes a first work function layer and the The materials of the second work function layer included in the second gate stack structure are completely different, and both the first work function layer and the second work function layer are non-pinching layers. 10. The method for manufacturing a gate-all-round transistor according to claim 9, wherein, along the length direction of the channel region, the channel region has a first region and a second region; the first gate stack The structure surrounds the periphery of the first region, and the second gate stack structure surrounds the periphery of the second region; The formation of a first gate stack structure and a second gate stack structure surrounding the periphery of the channel region in sequence along the direction from the source region to the drain region includes: forming a first gate stack material surrounding the first region and the second region; forming a mask layer on a portion of the first gate stack material corresponding to the first region; Under the mask effect of the mask layer, the part of the first gate stack material located on the periphery of the second region is selectively removed, so that the remaining part of the first gate stack material forms the first gate stacked structure; removing the mask layer; The second gate stack structure surrounding the periphery of the second region is formed. 11. The method for manufacturing a gate-all-round transistor according to claim 9, characterized in that, along the direction from the source region to the drain region, a first gate stack structure and a first gate stack structure surrounding the periphery of the channel region are formed in sequence The second gate stack structure, comprising: Along the direction from the source region to the drain region, the first gate dielectric layer included in the first gate stack structure and the second gate dielectric layer included in the second gate stack structure are sequentially formed on the outer periphery of the channel region. medium layer; The first work function layer on the first gate dielectric layer and the second work function layer on the second gate dielectric layer are sequentially formed.

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