CN115692429A - Far infrared light sensor with double absorption layers and manufacturing method thereof - Google Patents

Abstract

A far infrared light sensor comprises a substrate, a thermopile structure and a heat absorption layer. The thermopile structure is disposed on the substrate. The heat absorption layer covers the thermopile structure, wherein the heat absorption layer is provided with a hollow space left after the metal layer is etched.

Description

Far infrared light sensor with double absorption layers and manufacturing method thereof

Technical Field

The present invention relates to a thermometer structure, and more particularly, to a far-infrared light sensor having a double absorption layer for improving heat collection efficiency and a method for manufacturing the same.

Background

Fig. 1 shows a cross-sectional view of a conventional far infrared light sensing structure 1, in which the far infrared light sensing structure 1 includes a far infrared light sensing element 10 and a peripheral circuit 15. The far-infrared light sensing device 10 is formed on the substrate 11 and has a sensing region 16. The sensing region 16 can sense far infrared FIR. The far infrared light sensing device 10 includes a dielectric layer 12, and a sensing region is located in the dielectric layer 12. The sensing region 16 has a stack structure 161 and partition (partition) structures 162 and 163, wherein the partition structures 162 and 163 form a ring structure and surround the stack structure 161. Stack structure 161 and spacer structures 162 and 163 comprise polysilicon layers poly1 and poly2, respectively.

The far infrared light sensing structure can be manufactured by a CMOS process, and a peripheral circuit 15 is further formed on the substrate 11, wherein the peripheral circuit 15 includes at least one Metal Oxide Semiconductor (MOS) element 17, a plurality of metal layers M1 to M4, and a via hole V0. The via V0 is used to electrically connect the metal layers M1-M4 and the MOS device 17.

However, in the conventional far infrared light sensing device 10, the thickness h0 of the dielectric layer 12 above the sensing region 16 is limited by the CMOS process and cannot be easily adjusted. This results in that the sensing performance and the frame rate of the far infrared light sensing device 10 cannot be precisely controlled and adjusted.

Accordingly, the present invention provides a far infrared light sensor and a method for manufacturing the same, in which the heat collection efficiency is improved by reducing the volume of the heat absorbing layer.

Disclosure of Invention

The invention aims to provide a far infrared light sensor and a manufacturing method thereof, wherein the far infrared light sensor improves the heat collection efficiency by reducing the volume of a heat absorption layer and arranging a plurality of heat absorption layers.

Another objective of the present invention is to provide a far-infrared sensor and a method for manufacturing the same, in which a silicon nitride layer is disposed on a heat absorption layer to increase the absorption spectrum range of far-infrared light.

To achieve the above object, the present invention provides a far-infrared light sensor including a substrate, a thermopile structure, and a heat absorbing layer. The thermopile structure is disposed on the substrate. The heat absorption layer covers on the thermopile structure and is provided with a first heat absorption layer overlapped on a second heat absorption layer, wherein the first heat absorption layer and the second heat absorption layer are connected by a connecting layer, and the sectional area of the connecting layer is smaller than that of the first heat absorption layer and the second heat absorption layer.

In addition, the present invention also provides a method for manufacturing a far-infrared light sensing device, comprising: forming a thermopile structure on a substrate; forming a first metal layer over the thermopile structure partially overlapping the thermopile structure; forming a barrier layer over the thermopile structure corresponding to the thermopile structure; forming a second metal layer above the barrier layer corresponding to the barrier layer, wherein the thermopile structure, the first metal layer, the barrier layer and the second metal layer are coated in a dielectric layer; etching from the surface of the dielectric layer to the first metal layer, the second metal layer and the substrate by a first etching step; and removing the first metal layer, the second metal layer and a part of the substrate below the thermopile structure by a second etching step so that the dielectric layer between the thermopile structure and the barrier layer forms a double-layer heat absorption layer.

In addition, the invention also provides a far infrared light sensor comprising the substrate, the thermopile structure and the heat absorption layer. The thermopile structure is disposed on the substrate. The heat absorption layer covers the thermopile structure, wherein a hollow space left after the metal layer is etched is formed in the heat absorption layer.

In the far infrared light sensing element of the embodiment of the invention, the heat absorption layer can remove medium layers in different shapes and areas in the heat absorption layer by configuring different sacrificial metal layers.

In order that the manner in which the above recited and other objects, features and advantages of the present invention are obtained will become more apparent, a more particular description of the invention briefly described below will be rendered by reference to the appended drawings. In the description of the present invention, the same components are denoted by the same reference numerals, and the description thereof is made herein.

Drawings

FIG. 1 is a cross-sectional view of a known far-infrared light sensing structure;

fig. 2 is a sectional view of a far-infrared light sensor of an embodiment of the present invention;

fig. 3A to 3K are flow charts illustrating a process of manufacturing a far-infrared light sensor according to an embodiment of the present invention;

FIG. 4 is a cross-sectional view of a far-infrared light sensing element according to another embodiment of the present invention; and

fig. 5 is a cross-sectional view of a far infrared light sensing element according to still another embodiment of the present invention.

Description of the reference numerals

200. Far infrared light sensing element

21. Thermopile structure

22. Partition structure

23. 230 dielectric layer

231. First absorption layer

232. Connecting layer

233. Second absorption layer

242-244 barrier layer

900. Peripheral circuit

91. Metal oxide semiconductor element

V0 guide hole

P1 first polysilicon layer

P2 second polysilicon layer

Detailed Description

According to the far-infrared light sensor disclosed by the embodiment of the invention, at least one hollow space is formed by removing part of the medium layer in the heat absorption layer, and a plurality of heat absorption layers are formed in the far-infrared light advancing direction, so that the heat absorption efficiency is improved. In addition, silicon nitride (Si) is also disposed on the heat absorption layer ₂ N ₄ ) The layer to increase the absorption spectral range of the far infrared light.

Fig. 2 is a cross-sectional view of the far-infrared light sensor 2 according to an embodiment of the present invention. The far-infrared light sensor 2 includes a substrate 20, and a far-infrared light sensing element (sometimes simply referred to as a sensing element) 200 and a peripheral circuit 900 are formed on the substrate 20. The far infrared light sensor 2 of fig. 2 is, for example, a Micro Electro Mechanical System (MEMS) structure having a stack structure of 2 layers of polysilicon and 5 layers of metal made by a standard CMOS process.

The peripheral circuit 900 includes, for example, a Metal Oxide Semiconductor (MOS) device 91, a plurality of metal layers M1-M5 (but not limited to five layers, and also four layers, six layers, or more than six layers), and a plurality of vias (via) V0, wherein the devices are embedded in the dielectric layer 23. The via V0 connects the metal layers M1-M5 and the MOS device 91. The manner in which the MOS device 91 is fabricated in CMOS is well known and is not a primary objective of the present invention, and therefore, will not be described herein.

The sensing device 200 includes a thermopile structure 21, a spacer structure 22, a heat absorbing layer (e.g., covering the thermopile structure 21 and a dielectric layer 23 thereon), a plurality of barrier layers 242-244 (the function of which is illustrated later), and a plurality of metal layers M1-M5. In one embodiment, the plurality of metal layers M1-M5 in the sensing device 200 and the plurality of metal layers M1-M5 in the peripheral circuit 900 are fabricated by the same CMOS process.

The separation structure 22 is disposed on the substrate 20 and is used for separating each pixel of the far-infrared light sensor 2 from its neighboring pixels, wherein each pixel includes a plurality of thermocouples connected in series to form the thermopile structure 21. The separation structure 22 comprises a first polysilicon layer P1 and a second polysilicon layer P2 separated by a dielectric layer 230. The thermopile structure 21 is rectangular, for example, if viewed from above the far-infrared light sensor 2, and the separation structure 22 surrounds the periphery of the thermopile structure 21 and is between pixels.

The thermopile structure 21 is disposed on a substrate 20, such as a silicon substrate 20, but not limited thereto, and may be made of materials used for substrates in conventional MEMS structures. The thermopile structure 21 includes a first polysilicon layer P1 and a second polysilicon layer P2 (which are fabricated by the same CMOS process as the first polysilicon layer P1 and the second polysilicon layer P2 in the separation structure 22, but not limited thereto), stacked on each other, wherein the seebeck coefficients of the first polysilicon layer P1 and the second polysilicon layer P2 are different. A dielectric layer 230 (such as, but not limited to, silicon oxide) is sandwiched between the first polysilicon layer P1 and the second polysilicon layer P2 for isolation. The principle that the metal layer (e.g. M1) is connected to the first polysilicon layer P1 and the second polysilicon layer P2 through the via hole V0 to form a thermocouple, and a plurality of thermocouples (thermocouples) are connected to form a thermopile is known, and therefore, the description thereof is omitted.

The heat absorption layer (formed by the dielectric layer 23, for example) covers the thermopile structure 21 and is disposed thereon for absorbing the thermal energy of the far infrared FIR and transmitting the thermal energy to the thermopile structure 21. In the present invention, the heat absorbing layer has a hollow space HS left after a metal layer (for example, but not limited to, a metal layer M2 described later) is etched, so as to reduce the entire volume of the heat absorbing layer.

In one embodiment, the hollow space HS is aligned with one of the metal layers M1 to M5 in a transverse direction (e.g., a left-right direction in fig. 2), for example, fig. 2 shows the same layer as the metal layer M2. In another embodiment, the hollow space HS does not align any of the metal layers M1-M5 in the lateral direction, such as being fabricated by a deposition and patterning process different from that of the metal layers M1-M5 in a CMOS process.

In other embodiments, the hollow space HS may be formed only on one side of the heat absorption layer as shown in fig. 4. Alternatively, multiple layers of hollow spaces, such as HS1 and HS2 shown in fig. 5, may be formed in the heat absorbing layer. More specifically, the hollow space HS in the heat absorption layer may have different shapes and volumes according to different applications, as long as the overall volume of the heat absorption layer can be reduced, and is not particularly limited.

In one embodiment, the heat absorbing layer comprises a first heat absorbing layer 231 overlapping a second heat absorbing layer 233, wherein the first heat absorbing layer 231 and the second heat absorbing layer 233 are connected by a connecting layer 232, and the cross-sectional area of the connecting layer 232 is smaller (e.g., 1/5 to 1/10, but not limited to) than the cross-sectional areas of the first heat absorbing layer 231 and the second heat absorbing layer 233, for example, forming a dumbbell-like shape.

For example, the width of the connection layer 232 is less than 10 microns. In current end products, the pixel size is about 80 microns.

As mentioned above, since the connection layer 232 is formed after etching the sacrificial metal layer, the connection layer 232 aligns or misaligns one of the metal layers M1-M5 in the lateral direction, depending on whether the sacrificial metal layer is one of the metal layers M1-M5.

In addition, the upper surface of the heat absorbing layer (more specifically, the first absorbing layer 231) is further provided with a barrier layer (e.g., silicon nitride) 243, and the barrier layer 243 is used as an etching stop layer. The absorption spectrum of silicon nitride layer 243 is between 8 microns and 10 microns. The absorption spectrum of the silicon oxide layer (i.e., the heat absorbing layer) is between 10 microns and 12 microns. Therefore, the absorbable spectral range of the sensing device 200 can be increased, and the heat collection efficiency can be improved. In addition, in order to reduce the entire volume of the heat absorbing layer, the height of the barrier layer 243 in the longitudinal direction is lower than the uppermost layer M5 of the plurality of metal layers M1 to M5. For example, the barrier layer 243 may be between the metal layers M2 and M3, between the metal layers M3 and M4, or between the metal layers M4 and M5, without any particular limitation.

Referring to fig. 3A to fig. 3K, a process of manufacturing the far-infrared light sensor 2 according to the embodiment of the present invention is described.

As shown in fig. 3A, first, a dielectric layer 23 is formed on the substrate 20, and the dielectric layer 23 is, for example, thermal oxide grown silicon oxide or PECVD deposited undoped silicon oxide (USG), phosphorus doped silicon oxide (PSG), boron doped phosphorus silicon oxide (BPSG), or the like as a heat conductive layer.

Next, a first polysilicon layer P1, a dielectric layer 230 and a second polysilicon layer P2, which are used as the thermopile structure 21 and the separation structure 22 of the far-infrared light sensing element 200, are deposited and patterned on the dielectric layer 23. The material of the dielectric layer 230 is, for example, silicon oxide, but is not limited thereto. The seebeck coefficient of the first polysilicon layer P1 is different from that of the second polysilicon layer P2. As mentioned before, the separation structure 22 is used to separate different pixels. In other words, a plurality of the nir sensing elements 200 may be fabricated on the substrate 20 at the same time.

In addition, a peripheral circuit 900, such as a MOS device 91, is formed on the substrate 20, wherein the method of fabricating the MOS device 91 on the substrate 20 by a CMOS process is known and will not be described herein.

As shown in fig. 3B, another dielectric layer 23 is deposited on the substrate 20 again to bury the MOS device 91, the thermopile structure 21 and the separation structure 22 in the dielectric layer 23. The manner of forming the dielectric layer 23 is as described above, and therefore, will not be described herein.

As shown in fig. 3C, a plurality of vertical vias V0 are formed in the dielectric layer 23 and connected to the MOS device 91, the first polysilicon layer P1 and the second polysilicon layer P2. The via V0 is a conductive metal such as tungsten, polysilicon, aluminum, copper, or aluminum-copper alloy, but not limited thereto. The manner of forming vias in dielectric layer 23 is known and will not be described herein.

As shown in fig. 3D, a metal layer M1 is then deposited and patterned on the surface of the dielectric layer 23. The metal layer M1 is electrically connected to the via V0. At this time, a thermopile structure 21 is completed on the substrate 20, which is formed by connecting the metal layer M1 to two polysilicon layers having different seebeck coefficients through the via hole V0.

As shown in fig. 3E, after covering the metal layer M1 with a dielectric layer 23, a barrier layer 242 is deposited and patterned, and then another dielectric layer 23 covers the barrier layer 242. The barrier layer 242 serves as an etch stop layer in subsequent etching steps. The manner of forming the dielectric layer 23 is as described above, and therefore, will not be described herein.

As shown in fig. 3F, another via V0 is formed in the dielectric layer 23 to electrically connect to the metal layer M1.

As shown in fig. 3G, next, a metal layer M2 is deposited on the surface of the dielectric layer 23, and the metal layer M2 partially overlaps the thermopile structure 21, for example, the metal layer M2 does not overlap the metal layer M1. In the present invention, the metal layer M2 is used to define the connection layer 232. For example, a portion of the metal layer M2 is formed annularly above the thermopile structure 21.

As shown in fig. 3H, a plurality of metal layers M3, M4 and M5 and a plurality of vias V0 connecting the plurality of metal layers M3, M4 and M5 are sequentially formed in the dielectric layer 23 on the substrate 20 by a CMOS process according to a method similar to that shown in fig. 3C to fig. 3G, and a barrier layer 243 is formed above the thermopile structure 21 corresponding to the thermopile structure 21, wherein the barrier layer 243 is used as an etching stop layer in a subsequent etching step. A portion of the metal layer M4 is correspondingly disposed over the barrier layer 243. In addition, a barrier layer 244 is formed, and the barrier layer 244 is not shielded above the metal layer M5.

After the step of fig. 3H is completed, the thermopile structure 21, the separation structure 22, the plurality of metal layers M1-M5, the plurality of barrier layers 242-244, the plurality of vias V0, and the MOS device 91 are embedded in the dielectric layer 23.

In the present invention, the dielectric layer 23 formed multiple times is formed by the same method and material, and thus the same reference numerals are used to simplify the description.

As shown in fig. 3I, before the etching is started, a photoresist layer 30 is formed on the upper surface of the dielectric layer 23, and the photoresist layer 30 is not covered above the thermopile structure 21 and the separation structure 22.

Fig. 3J shows a first etching step, for example using Reactive Ion Etching (RIE), which etches from the upper surface of the dielectric layer 23 to the metal layer M2, the metal layer M4 and the substrate 20, and removes the photoresist layer 30. In this step, the metal layer M2 and the metal layer M4 are used as etching stop layers in the first etching step. The first etching step is, for example, dry etching, which has a higher etching rate for the dielectric layer 23 than for the metal layers M2, M4.

Fig. 3K shows a second etching step, such as wet etching using tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH), to remove the metal layer M2, the metal layer M4 and a portion of the substrate 20 under the thermopile structure 21, so that the dielectric layer 23 between the thermopile structure 21 and the barrier layer 243 forms two heat absorbing layers 231, 233 and the thermopile structure 21 is suspended. In the second etching step, the etching rate of the etching solution to the metal layers M2 and M4 is higher than that to the dielectric layer 23. By removing the metal layer M2, the hollowed-out space HS may be formed in the heat absorbing layer.

The double heat absorbing layer includes a first heat absorbing layer 231, a second heat absorbing layer 233, and a connecting layer 232 connected between the first heat absorbing layer 231 and the second heat absorbing layer 233. In the present invention, the cross-sectional area of the connection layer 232 is smaller than the cross-sectional areas of the first and second heat absorbing layers 231 and 233 to form a structure shaped like a dumbbell.

For example, when the thermopile structure 21 is rectangular as viewed from above, the cross-sectional area of the connection layer 232 is also rectangular, but is not limited thereto. The cross-sectional area of the connecting layer 232 may also be other shapes, such as circular.

Finally, a third etching step is performed on the structure of fig. 3K to remove the barrier layers 242, 243, and 244 and the dielectric layer 23 above the metal layer M5, so as to complete the far-infrared light sensor 2 shown in fig. 2. The third etching step is, for example, dry etching (e.g., RIE) having a higher etching rate for the dielectric layer 23 than for the metal layer M5 and the barrier layers 242, 243, 244. In this step, the metal layer M5 and the barrier layers 242, 243, and 244 serve as etching stop layers in the third etching step.

In the present invention, the height of the barrier layer 243 (e.g., silicon nitride layer) in the longitudinal direction is preferably lower than the top-most layers of the metal layers M1-M5, for example, as shown in FIG. 2, between the metal layers M3 and M4, so as to further reduce the overall volume of the heat absorption layer and improve the heat collection efficiency.

In the present invention, the arrangement positions and the connection relationships of the metal layers M1 to M5 depend on actual requirements, and are not limited to those shown in the drawings of the present specification.

It should be noted that although the thermopile structure 21 is described as being formed by two polysilicon layers, the present invention is not limited thereto, and the two polysilicon layers may be replaced by one metal layer and one polysilicon layer, or by two metal layers, as long as the seebeck coefficients of the two materials are different.

Although the thermopile structure 21 is shown in the drawings as being formed by two polysilicon layers stacked one on top of the other, the invention is not limited thereto, and the two polysilicon layers may be contacted in the lateral direction to form a lateral thermopile structure.

It should be understood that the number of components, the size ratio and the like in the embodiments and the drawings are only for illustrative purposes and are not intended to limit the present invention.

In summary, since the volume of the heat absorption layer affects the sensing performance, the structure of the heat absorption layer needs to be adjusted. In view of the above, the present invention further provides a far infrared light sensor (for example, refer to fig. 2) and a method for manufacturing the same (for example, refer to fig. 3A to 3K) that improves heat collection efficiency by reducing the volume of the heat absorption layer, wherein the method achieves the purpose of reducing the volume by disposing a sacrificial metal layer in the heat absorption layer during the manufacturing process and removing the sacrificial metal layer before the manufacturing process is completed. In addition, the heat collection efficiency is further improved by arranging the plurality of heat absorption layers and arranging the barrier layer on the plurality of heat absorption layers.

Although the present invention has been disclosed by way of examples, it is not intended to be limited thereto, and various changes and modifications can be made by one of ordinary skill in the art without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the scope defined by the appended claims.

Claims (20)

1. A far-infrared light sensor, comprising:

a substrate;

a thermopile structure disposed on the substrate; and

the thermoelectric module comprises a thermoelectric pile structure, a heat absorption layer, a first heat absorption layer and a second heat absorption layer, wherein the thermoelectric pile structure is covered by the heat absorption layer, the first heat absorption layer is overlapped on the second heat absorption layer, the first heat absorption layer is connected with the second heat absorption layer through a connecting layer, and the sectional area of the connecting layer is smaller than that of the first heat absorption layer and that of the second heat absorption layer.

2. The far-infrared light sensor of claim 1, further comprising a peripheral circuit disposed on the substrate, the peripheral circuit comprising a plurality of metal layers, wherein the connecting layer aligns one of the metal layers in a lateral direction.

3. The far-infrared light sensor of claim 1, further comprising a peripheral circuit disposed on the substrate, the peripheral circuit comprising a plurality of metal layers, wherein the connecting layer does not align the metal layers in a lateral direction.

4. The far-infrared light sensor of claim 1, wherein the width of the connection layer is less than 10 microns.

5. The far-infrared light sensor according to claim 1, wherein the cross-sectional area of the connection layer is less than 1/10 of the cross-sectional areas of the first and second heat absorbing layers.

6. The far-infrared light sensor of claim 1, wherein the upper surface of the first heat absorbing layer is further provided with a barrier layer, the barrier layer serving as an etch stop layer.

7. The far-infrared light sensor of claim 6, further comprising a peripheral circuit disposed on the substrate, the peripheral circuit comprising a plurality of metal layers, wherein the blocking layer is lower than an uppermost layer of the metal layers.

8. The far-infrared light sensor of claim 1, wherein the thermopile structure comprises:

the method comprises the steps that a first polycrystalline silicon layer and a second polycrystalline silicon layer are stacked mutually, wherein the Seebeck coefficients of the first polycrystalline silicon layer and the second polycrystalline silicon layer are different;

the dielectric layer is clamped between the first polycrystalline silicon layer and the second polycrystalline silicon layer; and

and the metal layer is respectively connected with the first polycrystalline silicon layer and the second polycrystalline silicon layer through guide holes.

9. A method for manufacturing a far-infrared light sensing element comprises the following steps:

forming a thermopile structure on a substrate;

forming a first metal layer over the thermopile structure partially overlapping the thermopile structure;

forming a barrier layer over the thermopile structure corresponding to the thermopile structure;

forming a second metal layer above the barrier layer corresponding to the barrier layer, wherein the thermopile structure, the first metal layer, the barrier layer and the second metal layer are coated in a dielectric layer;

etching from the surface of the dielectric layer to the first metal layer, the second metal layer and the substrate by a first etching step; and

removing the first metal layer, the second metal layer and a part of the substrate below the thermopile structure by a second etching step, so that the dielectric layer between the thermopile structure and the barrier layer forms a double-layer heat absorption layer.

10. The method of manufacturing of claim 9, wherein the bi-layer heat absorbing layer comprises:

a first heat absorbing layer;

a second heat absorbing layer; and

and the connecting layer is connected between the first heat absorbing layer and the second heat absorbing layer, and the sectional area of the connecting layer is smaller than that of the first heat absorbing layer and that of the second heat absorbing layer.

11. The method of manufacturing of claim 10, wherein the first metal layer defines the connection layer.

12. The method of manufacturing of claim 9, further comprising:

etching the dielectric layer to the barrier layer after the second etching step with a third etching step.

13. The method of manufacturing of claim 12, further comprising:

forming a plurality of metal layers on the substrate, wherein the barrier layer is lower than the uppermost layer of the metal layers.

14. The fabrication method of claim 9, wherein prior to the first etching step, the fabrication method further comprises:

and forming a light resistance layer on the surface of the dielectric layer, wherein the light resistance layer is not covered above the thermopile structure.

15. The method of manufacturing of claim 9, further comprising:

forming a plurality of metal layers on the substrate, wherein the first metal layer and the second metal layer correspond to two of the metal layers.

16. A far-infrared light sensor, comprising:

a substrate;

a thermopile structure disposed on the substrate; and

the heat absorption layer covers the thermopile structure, and a hollow space left after the metal layer is etched is formed in the heat absorption layer.

17. The far-infrared light sensor of claim 16, further comprising a peripheral circuit disposed on the substrate, the peripheral circuit comprising a plurality of metal layers, wherein the hollowed-out space aligns one of the metal layers in a lateral direction.

18. The far-infrared light sensor of claim 16, further comprising peripheral circuitry disposed on the substrate, the peripheral circuitry comprising a plurality of metal layers, wherein the hollowed-out space does not align with one of the metal layers in a lateral direction.

19. The far-infrared light sensor of claim 16, wherein the upper surface of the heat absorbing layer is further provided with a barrier layer, the barrier layer serving as an etch stop layer.

20. The far-infrared light sensor of claim 19, further comprising a peripheral circuit disposed on the substrate, the peripheral circuit comprising a plurality of metal layers, wherein the barrier layer is lower than an uppermost layer of the metal layers.

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