CN115691088A - Control signal transmission unit, system and method - Google Patents
Control signal transmission unit, system and method Download PDFInfo
- Publication number
- CN115691088A CN115691088A CN202310005115.9A CN202310005115A CN115691088A CN 115691088 A CN115691088 A CN 115691088A CN 202310005115 A CN202310005115 A CN 202310005115A CN 115691088 A CN115691088 A CN 115691088A
- Authority
- CN
- China
- Prior art keywords
- subsystem
- control
- level
- control signal
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a control signal transmission unit, a system and a method, which enable the high level holding time of the write permission of a register in a subsystem and the low level holding time of the system when the control signal becomes low level and enters a turn-off mode by setting the number of preset pulses entering a system control mode, and ensure that the subsystem can correctly enter the control mode and correctly control the register setting and normally run only when the control signal strictly meets the conditions; the application is simple, the system resource is saved, and the system cost is reduced.
Description
Technical Field
The invention relates to the field of signal transmission, in particular to a control signal transmission unit, a control signal transmission system and a control signal transmission method.
Background
For complex systems, various control signals and data are often required to be transmitted, and the common transmission modes include an IIC control protocol or an SPI control protocol and other modes, but the modes need to occupy 2 to 3 interfaces of each system to transmit clock signals, control signals or data signals and chip selection signals, and the transmission modes not only occupy too many interface resources, but also have very complex control modes and increase communication cost.
Disclosure of Invention
The invention aims to provide a simple, flexible, convenient and reliable system and a method for transmitting control signals between systems, which can greatly save resources and reduce communication cost.
In order to achieve the above object, the present invention provides a control signal transmission unit, including: the device comprises a high level detection and pulse counting module, a high level delay detection module, a pulse counting module, a control register and a control register setting completion judgment module;
the high level detection and pulse counting module is used for detecting and counting high level pulses of the control pin and comparing the high level pulses with the number of pulses entering a control mode preset by a system;
the high level delay detection module is used for detecting the high level duration of the control signal and comparing the high level duration with the write permission time of an enable control register set by a system;
the pulse counting module is used for counting the number of pulses sent after the control signal keeps the high level time to exceed the write permission time of an enable control register set by a system, and setting the number of the pulses as the value of the control register;
the control register setting completion judging module is used for generating a high-level setting completion signal and shielding the counting function of the pulse counting module.
Optionally, the method further includes: and the low level delay detection module is used for detecting the level change of a control signal of the control pin during the normal operation of the system.
The invention also provides a control signal transmission method, which adopts the control signal transmission unit and comprises the following steps:
the subsystem detects and counts high-level pulses of the control pin, and compares the high-level pulses with a preset pulse number; if the detected number of the high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the detection is carried out again;
the pin of an enabling control register of the subsystem entering the control mode is connected with a fixed high level, the subsystem detects the duration time of the high level of the control signal and compares the duration time with the preset time of the write permission of the control register in the enabling subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, repeating the steps; and after the setting is finished, a high-level setting finishing signal is generated and is connected to a control state latch pin, the subsystem controls the register value to be locked, and the system enters a normal operation mode.
The present invention also provides a control signal transmission system, which adopts the above control signal transmission unit, comprising: the control pins of the N subsystems receive the same control signal, the pin of an enable control register of the 1 st subsystem is connected with a high level, a setting completion signal output by the ith subsystem is connected to the pin of an enable control register of the next subsystem, and the setting completion signal of the Nth subsystem is connected to the control state latch pins of all the subsystems, wherein i is more than or equal to 1 and less than N.
Optionally, the control signals of the N subsystems are shared.
The invention also provides a control signal transmission method, which adopts the control signal transmission system and comprises the following steps:
the subsystem detects the high level pulse of the control pin, counts and compares the high level pulse with the preset pulse number; if the detected number of the high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the detection is carried out again;
in a subsystem entering a control mode, a pin of an enable control register of a 1 st subsystem is connected with a fixed high level, and the subsystem detects the duration time of the high level of a control signal and compares the duration time with the preset time of the write permission of the control register in the enable subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, repeating the steps; after the 1 st subsystem is set, generating a high-level setting completion signal to be connected to an input pin of an enable control register of the 2 nd subsystem, and shielding the counting function of a pulse counting module of the 1 st subsystem;
the 1 st subsystem completes the setting of the high level of the signal to enable the control register of the 2 nd subsystem, and the 2 nd subsystem detects the duration time of the high level of the control signal and compares the duration time with the time of the write permission of the control register in the preset enabling subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, continuously detecting the duration time of the high level of the control signal by the subsystem; after the 2 nd subsystem is set, generating a high-level setting completion signal and connecting the high-level setting completion signal to an input pin of an enable control register of the next subsystem, and shielding the counting function of a pulse counting module of the 2 nd subsystem; in the same way, a high-level setting completion signal is generated until the Nth subsystem is set;
and the Nth subsystem outputs a high-level setting completion signal and inputs the high-level setting completion signal to the control state latch pins of all the subsystems, all the subsystems control the register value to be locked, and the system enters a normal operation mode.
Optionally, the method further includes: and when the duration time exceeds the preset time, the subsystem counts the number of subsequent high-level pulses, and sets the value of an internal control register of the subsystem according to the number of the subsequent high-level pulses.
Optionally, the method further includes: after normal operation, the subsystem continuously detects the control signal level of the control pin, when the control signal level becomes low, the subsystem detects the duration of low level, if the duration of low level is less than the preset turn-off time of the system, the normal operation mode is continued, if the duration of low level reaches the preset turn-off time, the subsystem resets an internal control register, and the subsystem enters the turn-off mode.
Optionally, the method further includes: after the subsystem enters the shutdown mode, the subsystem continues to detect the control pin high level pulse and continues to enter the control mode.
Compared with the prior art, the control signal controls a plurality of subsystems, control pins of the subsystems are connected and receive the same control signal, a VDD signal with fixed high level enables a control register of the 1 st subsystem, a setting completion signal with high level output by the previous subsystem enables a control register of the next subsystem, a setting completion signal with high level of the last subsystem is connected back to control state latch pins of all the subsystems, the control register values of all the subsystems are locked, and the system enters a normal operation mode.
The method comprises the steps that a strict judgment mechanism is set for limiting, the number of pulses entering a system control mode is preset, and high level holding time enabling write permission of a register inside a subsystem is ensured, so that the subsystem can enter the control mode correctly and control register setting correctly only when a control signal strictly meets conditions; the transmission of various complex control signals between systems can be conveniently and reliably realized only by one control pin, the system can comprise at least one subsystem or a plurality of subsystems, the application is very simple and flexible, the system resources are saved, and the system cost is reduced.
Drawings
FIG. 1 is a diagram of a control signal transmission unit according to an embodiment of the present invention;
FIG. 2 is a first flowchart illustrating a control signal transmission method according to an embodiment of the present invention;
FIG. 3 is a diagram of a control signal transmission system according to an embodiment of the present invention;
FIG. 4 is a second flowchart illustrating a control signal transmission method according to an embodiment of the present invention;
fig. 5 is a logic flow diagram illustrating a control signal transmission method according to an embodiment of the present invention.
Detailed Description
A more detailed description of a control signal transmission unit, system and method of the present invention will now be given with reference to the accompanying schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that those skilled in the art may modify the invention herein described while still achieving the advantageous effects thereof. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The present invention provides a control signal transmission unit, please refer to fig. 1, including: the device comprises a high level detection and pulse counting module, a high level delay detection module, a pulse counting module, a control register and a control register setting completion judgment module;
specifically, the high level detection and pulse counting module is used for detecting and counting high level pulses of the control pin and comparing the high level pulses with the number of pulses which enter a control mode and are preset by a system; in particular for limiting the conditions under which the subsystem enters the control mode.
The high level delay detection module is used for detecting the high level duration of the control signal and comparing the high level duration with the write permission time of an enable control register set by a system; in particular for limiting the conditions for entering the control mode, preventing the subsystem from setting the internal control registers erroneously.
The pulse counting module is used for counting the number of pulses sent after the high level time kept by the control signal exceeds the write permission time of the enable control register set by the system, and setting the value of the control register.
The control register setting completion judging module is used for generating a high-level setting completion signal and shielding the counting function of the pulse counting module.
In other embodiments, the control signal transmission unit further includes: the low level delay detection module is used for detecting the level change of a control signal of a control pin during the normal operation of the system; particularly for monitoring level changes during normal operation of the system.
In addition, the subsystem entering the normal operation mode carries out data transmission with other modules.
An embodiment of the present invention further provides a method for transmitting a control signal, including only one subsystem, please refer to fig. 2, including the following steps:
the subsystem detects the high level pulse of the control pin, counts and compares the high level pulse with the preset pulse number; if the detected number of the high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the detection is carried out again;
enabling a system control register pin of a subsystem entering a control mode to be at a high level, detecting the duration time of the high level of a control signal, and comparing the duration time with the preset time of the write permission of a control register in the enabling subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, repeating the steps; and after the setting is finished, a high-level setting finishing signal is generated and is connected to the control state latch pin, the subsystem controls the register value to be locked, and the system enters a normal operation mode.
An embodiment of the present invention further provides a control signal transmission system, including: the control pins of the N subsystems receive the same control signal, the pin of an enable control register of the 1 st subsystem is connected with a fixed high level signal, a setting completion signal output by the ith subsystem is connected with the pin of the enable control register of the next subsystem, and the setting completion signal of the Nth subsystem is connected with the control state latch pins of all the subsystems, wherein i is more than or equal to 1 and less than N.
Referring to fig. 3, the control pins of the subsystems are connected to receive the same control signal, the VDD signal of a fixed high level enables the control register of the 1 st subsystem, the setting completion signal of a high level output by the previous subsystem enables the control register of the next subsystem, and the setting completion signal of a high level of the last subsystem is connected back to the control state latch pins of all the subsystems.
An embodiment of the present invention further provides a control signal transmission method, please refer to fig. 4-5, including the following steps:
s1, detecting high-level pulses of a control pin by a subsystem, counting the high-level pulses, and comparing the high-level pulses with a preset number of pulses; if the detected number of the high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the detection is carried out again;
s2, in the subsystem entering the control mode, connecting a pin of an enable control register of the 1 st subsystem with a fixed high level, detecting the duration time of the high level of a control signal by the subsystem, and comparing the duration time with the write permission time of the control register in a preset enable subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, repeating the steps;
s3, after the 1 st subsystem is set, generating a high-level setting completion signal to be connected to an input pin of an enable control register of the 2 nd subsystem, and simultaneously shielding the counting function of a pulse counting module of the 1 st subsystem;
s4, enabling a control register of the 2 nd subsystem by a high-level setting completion signal of the 1 st subsystem, detecting the duration time of the high level of the control signal by the 2 nd subsystem, and comparing the duration time with the preset time for enabling the write permission of the control register in the subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, continuously detecting the duration time of the high level of the control signal by the subsystem;
s5, generating a high-level setting completion signal after the 2 nd subsystem is set, connecting the high-level setting completion signal to an input pin of an enable control register of the next subsystem, and shielding the counting function of a pulse counting module of the 2 nd subsystem;
s6, repeating S4-S5 until the Nth subsystem is set, and generating a high-level setting completion signal;
and S7, outputting a high-level setting completion signal by the Nth subsystem, inputting the high-level setting completion signal to the control state latch pins of all the subsystems, locking the values of the control registers of all the subsystems, and enabling the system to enter a normal operation mode.
In S1, specifically, if the number of pulses set to enter the control mode is 16 high-level pulses, the control pin is required to transmit 16 high-level pulses, and the subsystem enters the control mode. If interference or noise causes accidental high-level burr signals to appear on a control pin, the pulse number of the burr signals hardly meets the requirement of 16 pulse numbers, so that the high-level burr pulses generated by the interference or the noise hardly make a subsystem enter a control mode wrongly, and in addition, if the pulse number is not more than 16 wrong pulse signals, the subsystem cannot enter the control mode, so that the subsystem is prevented from entering the control mode wrongly by the high-level burr signals or the wrong high-level pulse signals to a great extent.
Specifically, by comparing the duration of the high level of the control signal with the preset time for enabling the write permission of the control register in the subsystem in S2, the condition for entering the setting mode can be limited, and the disturbance signal or the wrong pulse can be prevented from causing the subsystem to set the internal control register incorrectly.
In S2, the setting the subsystem internal control register further includes step S201: after the control signal keeps the high level time to exceed the preset time for enabling the write permission of the control register in the subsystem, the pulse counting module of the 1 st subsystem continues to count the number of high level pulses of the subsequent control signal, and sets the value of the control register in the 1 st subsystem according to the number of the pulses.
Specifically, in S4, the setting of the subsystem internal control register further includes step S401: and after the high level time of the control signal exceeds the preset time, the pulse counting module of the 2 nd subsystem continues to count the number of high level pulses of the subsequent control signal, and the value of a control register in the subsystem is set according to the number of the pulses.
In addition, the method also comprises a step S8, the subsystem after normal operation continuously detects the control signal level of the control pin, when the control signal level becomes low, the subsystem detects the low level duration, if the low level duration is less than the preset turn-off time of the system, the subsystem regards as an interference signal and continues the normal operation mode, if the low level duration reaches the preset turn-off time, the subsystem resets all internal control registers, each subsystem enters the turn-off mode, and the system entering the turn-off mode returns to the step S1.
In summary, in the technical solution of the present invention, a control signal controls multiple subsystems, control pins of the multiple subsystems are connected to receive the same control signal, a fixed high-level VDD signal enables a control register of the 1 st subsystem, a high-level setup completion signal output by a previous subsystem enables a control register of a next subsystem, and a high-level setup completion signal of a last subsystem is received back to control state latch pins of all subsystems, all subsystems control register values are locked, and the system enters a normal operation mode.
The method comprises the steps that a strict judgment mechanism is set for limitation, the number of pulses entering a system control mode is preset, high level holding time enabling write permission of a register in a subsystem is also set, and low level holding time enabling the system to enter a turn-off mode when a control signal becomes low level is guaranteed, so that the subsystem can be enabled to enter the control mode correctly and control register setting and normal operation correctly can be guaranteed only when the control signal meets the strict condition; the transmission of various complex control signals between systems can be conveniently and reliably realized only by one control pin, the system can comprise at least one subsystem or a plurality of subsystems, the application is very simple and flexible, the system resources are saved, and the system cost is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A control signal transmission unit, comprising: the device comprises a high level detection and pulse counting module, a high level delay detection module, a pulse counting module, a control register and a control register setting completion judgment module;
the high level detection and pulse counting module is used for detecting and counting high level pulses of the control pin and comparing the high level pulses with the number of pulses which are preset by a system and enter a control mode;
the high level delay detection module is used for detecting the high level duration of the control signal and comparing the high level duration with the write permission time of an enable control register set by a system;
the pulse counting module is used for counting the number of pulses sent after the control signal keeps the high level time to exceed the write permission time of an enable control register set by a system, and setting the number of the pulses as the value of the control register;
the control register setting completion judging module is used for generating a high-level setting completion signal and shielding the counting function of the pulse counting module.
2. The control signal transmission unit of claim 1, further comprising: and the low level delay detection module is used for detecting the level change of a control signal of the control pin during the normal operation of the system.
3. A control signal transmission method, characterized in that the control signal transmission unit according to claim 1 or 2 is used, comprising the steps of:
the subsystem detects and counts high-level pulses of the control pin, and compares the high-level pulses with a preset pulse number; if the detected number of the high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the detection is carried out again;
enabling a system control register pin of a subsystem entering a control mode to be at a high level, detecting the duration time of the high level of a control signal by the subsystem, and comparing the duration time with the preset time of the write permission of a control register in the enabling subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, repeating the steps; and after the setting is finished, a high-level setting finishing signal is generated and is connected to the control state latch pin, the subsystem controls the register value to be locked, and the system enters a normal operation mode.
4. A control signal transmission system using the control signal transmission unit according to claim 1 or 2, comprising: the control pins of the N subsystems receive the same control signal, the pin of an enable control register of the 1 st subsystem is connected with a high level, a setting completion signal output by the ith subsystem is connected to the pin of an enable control register of the next subsystem, and the setting completion signal of the Nth subsystem is connected to the control state latch pins of all the subsystems, wherein i is more than or equal to 1 and less than N.
5. The control signal transmission system according to claim 4, wherein the control signals of the N subsystems are one shared.
6. A control signal transmission method characterized by employing the control signal transmission system according to claim 4 or 5, comprising the steps of:
the subsystem detects and counts high-level pulses of the control pin, and compares the high-level pulses with a preset pulse number; if the detected number of the high-level pulses is equal to the preset number of the pulses, the subsystem enters a control mode, otherwise, the detection is carried out again;
in a subsystem entering a control mode, a pin of an enable control register of a 1 st subsystem is connected with a fixed high level, and the subsystem detects the duration time of the high level of a control signal and compares the duration time with the preset time of the write permission of the control register in the enable subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, repeating the steps; after the 1 st subsystem is set, generating a high-level setting completion signal to be connected to an input pin of an enable control register of the 2 nd subsystem, and shielding the counting function of a pulse counting module of the 1 st subsystem;
the 1 st subsystem completes the setting of the high level of the signal to enable the control register of the 2 nd subsystem, and the 2 nd subsystem detects the duration time of the high level of the control signal and compares the duration time with the time of the write permission of the control register in the preset enabling subsystem; when the duration time exceeds the preset time, setting a subsystem internal control register, otherwise, the subsystem continuously detects the duration time of the high level of the control signal; after the setting of the 2 nd subsystem is finished, generating a high-level setting finishing signal and connecting the high-level setting finishing signal to an input pin of an enable control register of the next subsystem, and simultaneously shielding the counting function of a pulse counting module of the 2 nd subsystem; in the same way, a high-level setting completion signal is generated until the Nth subsystem is set;
and the Nth subsystem outputs a high-level setting completion signal and inputs the high-level setting completion signal to the control state latch pins of all the subsystems, all the subsystems control the register value to be locked, and the system enters a normal operation mode.
7. The control signal transmission method of claim 6, further comprising: and when the duration time exceeds the preset time, the subsystem counts the number of subsequent high-level pulses, and sets the value of an internal control register of the subsystem according to the number of the subsequent high-level pulses.
8. The control signal transmission method of claim 6, further comprising: after normal operation, the subsystem continuously detects the control signal level of the control pin, when the control signal level becomes low, the subsystem detects the duration of low level, if the duration of low level is less than the preset turn-off time of the system, the normal operation mode is continued, if the duration of low level reaches the preset turn-off time, the subsystem resets an internal control register, and the subsystem enters the turn-off mode.
9. The control signal transmission method of claim 8, further comprising: after the subsystem enters the shutdown mode, the subsystem continues to detect the control pin high level pulse and continues to enter the control mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310005115.9A CN115691088B (en) | 2023-01-04 | 2023-01-04 | Control signal transmission unit, system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310005115.9A CN115691088B (en) | 2023-01-04 | 2023-01-04 | Control signal transmission unit, system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115691088A true CN115691088A (en) | 2023-02-03 |
| CN115691088B CN115691088B (en) | 2023-05-02 |
Family
ID=85057063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310005115.9A Active CN115691088B (en) | 2023-01-04 | 2023-01-04 | Control signal transmission unit, system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115691088B (en) |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3723971A (en) * | 1971-12-14 | 1973-03-27 | Ibm | Serial loop communications system |
| US3820073A (en) * | 1972-09-22 | 1974-06-25 | Westinghouse Electric Corp | Solid state remote meter reading system having non-volatile data accumulation |
| US4104694A (en) * | 1974-11-04 | 1978-08-01 | Hargrove Daniel J | Asynchronous digital locking system |
| EP0443589A2 (en) * | 1990-02-23 | 1991-08-28 | Canon Kabushiki Kaisha | Unit control oriented communication device |
| JPH09212453A (en) * | 1995-11-28 | 1997-08-15 | Fujitsu Ltd | Bus extension adaptive type control system |
| JPH11288399A (en) * | 1999-03-03 | 1999-10-19 | Sony Corp | Address setting method |
| CN1362651A (en) * | 2000-12-26 | 2002-08-07 | Lg电子株式会社 | Apparatus and method for exchanging state information between circuit boards |
| JP2003008595A (en) * | 2001-06-19 | 2003-01-10 | Yaskawa Electric Corp | Optical digital signal relay transmission device |
| GB0415982D0 (en) * | 2003-08-06 | 2004-08-18 | Agilent Technologies Inc | Method and apparatus for volume control |
| CN101996584A (en) * | 2009-08-10 | 2011-03-30 | 联咏科技股份有限公司 | Method and structure for setting multi-core chip address and display system for application |
| CN102792265A (en) * | 2010-03-05 | 2012-11-21 | 国际商业机器公司 | Instruction cracking based on machine state |
| CN104579197A (en) * | 2013-10-09 | 2015-04-29 | 无锡华润矽科微电子有限公司 | Audio power amplifying circuit and mode control circuit thereof |
| CN108897712A (en) * | 2018-07-09 | 2018-11-27 | 北京集创北方科技股份有限公司 | Single line transmission method, chip and communication system |
| CN208796234U (en) * | 2018-08-22 | 2019-04-26 | 同源微（北京）半导体技术有限公司 | Control the Transmission system and its subsystem of data |
| CN112654109A (en) * | 2020-12-30 | 2021-04-13 | 深圳市天微电子股份有限公司 | Light-emitting module, display screen and control method for signal transmission among light-emitting chips |
-
2023
- 2023-01-04 CN CN202310005115.9A patent/CN115691088B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3723971A (en) * | 1971-12-14 | 1973-03-27 | Ibm | Serial loop communications system |
| US3820073A (en) * | 1972-09-22 | 1974-06-25 | Westinghouse Electric Corp | Solid state remote meter reading system having non-volatile data accumulation |
| US4104694A (en) * | 1974-11-04 | 1978-08-01 | Hargrove Daniel J | Asynchronous digital locking system |
| EP0443589A2 (en) * | 1990-02-23 | 1991-08-28 | Canon Kabushiki Kaisha | Unit control oriented communication device |
| JPH09212453A (en) * | 1995-11-28 | 1997-08-15 | Fujitsu Ltd | Bus extension adaptive type control system |
| JPH11288399A (en) * | 1999-03-03 | 1999-10-19 | Sony Corp | Address setting method |
| CN1362651A (en) * | 2000-12-26 | 2002-08-07 | Lg电子株式会社 | Apparatus and method for exchanging state information between circuit boards |
| JP2003008595A (en) * | 2001-06-19 | 2003-01-10 | Yaskawa Electric Corp | Optical digital signal relay transmission device |
| GB0415982D0 (en) * | 2003-08-06 | 2004-08-18 | Agilent Technologies Inc | Method and apparatus for volume control |
| CN101996584A (en) * | 2009-08-10 | 2011-03-30 | 联咏科技股份有限公司 | Method and structure for setting multi-core chip address and display system for application |
| CN102792265A (en) * | 2010-03-05 | 2012-11-21 | 国际商业机器公司 | Instruction cracking based on machine state |
| CN104579197A (en) * | 2013-10-09 | 2015-04-29 | 无锡华润矽科微电子有限公司 | Audio power amplifying circuit and mode control circuit thereof |
| CN108897712A (en) * | 2018-07-09 | 2018-11-27 | 北京集创北方科技股份有限公司 | Single line transmission method, chip and communication system |
| CN208796234U (en) * | 2018-08-22 | 2019-04-26 | 同源微（北京）半导体技术有限公司 | Control the Transmission system and its subsystem of data |
| CN112654109A (en) * | 2020-12-30 | 2021-04-13 | 深圳市天微电子股份有限公司 | Light-emitting module, display screen and control method for signal transmission among light-emitting chips |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115691088B (en) | 2023-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10108578B2 (en) | Single wire communications interface and protocol | |
| US7714619B2 (en) | High-frequency clock detection circuit | |
| US8103896B2 (en) | Method and system for I2C clock generation | |
| US9645898B2 (en) | Storage control device and control device for detecting abnormality of signal line | |
| US20050195677A1 (en) | Method and apparatus for optimizing timing for a multi-drop bus | |
| US20150286607A1 (en) | Determination of the state of an i2c bus | |
| US11133802B2 (en) | Repeater for an open-drain communication system using a current detector and a control logic circuit | |
| CN109871344B (en) | Communication system, interface circuit and signal transmission method thereof | |
| US4985890A (en) | Data transmission unit | |
| CN115691088B (en) | Control signal transmission unit, system and method | |
| US5315597A (en) | Method and means for automatically detecting and correcting a polarlity error in twisted-pair media | |
| US6389568B1 (en) | Method and apparatus for detecting handshaking protocol errors on an asynchronous data bus | |
| JP3465889B2 (en) | Serial data transfer device, control method therefor, and communication device | |
| US7848856B2 (en) | Communication system and electronic control unit including communication system for vehicle control | |
| CN115880883B (en) | System and method for selectively transmitting control signals between systems | |
| CN116303203A (en) | Control signal transmission system and method | |
| CN107368439B (en) | Master control element and data transmission method | |
| CN115657567B (en) | Method and control system for transmitting control signal by single pin | |
| TW202207044A (en) | Enhanced serial peripheral interface transmission control device and method | |
| CN112445744A (en) | I2C communication | |
| CN113190479B (en) | Data interaction method of processor and 1553B bus controller | |
| US11416439B2 (en) | USB-C connection line and USB-C connection line signal judgement method thereof | |
| CN116827714A (en) | Communication anti-interference method, device, system and storage medium | |
| CN117608909A (en) | MIPI data line conflict logic detection circuit | |
| CN118012811A (en) | Bus circuit and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 201203 No. 10, Lane 36, Xuelin Road, Pudong New Area, Shanghai Applicant after: Shanghai hailichuang Technology Co.,Ltd. Address before: Room 411, 4th floor, main building, No. 835 and 937, Dangui Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200131 Applicant before: Shanghai hailichuang Technology Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |