JP2003008595A - Optical digital signal relay transmission device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical digital signal relay transmission device that can normally conduct data relay operations even when a data transmission rate is increased with respect to the same system clock. SOLUTION: The optical digital signal relay transmission device adopting the HDLC transmission is provided with a change point counter circuit 5671 that counts the number of change points of Q0 data of a reception register circuit 561 and outputs the count to the Q0-OL of the circuit 5671 while a 1 bit pulse width detection circuit 562-CO is at a high level and with an M bit count discrimination circuit 5672 that compares the count of the change point counter circuit 5671 with a specified count of a circuit 565A-CO2, outputs a result from the 5672-Y1 as a matching output when they are matched with each other or provides a reset output from the 5672-Y0 when mismatched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high level data link control procedure HDLC (High Level D).
The present invention relates to a digital signal relay transmission device that receives and reproduces data of an ATA Control Procedure (frame) frame, and relays and transmits the data.

[0002]

2. Description of the Related Art FIG. 1 shows the configuration of a half-duplex transmission system to which an optical digital signal relay transmission device is connected. In FIG. 1, this half-duplex transmission system is a two-wire type electric transmission line 7,
Stations 1, 2 connected to 8 and transmitting data
3, 4 and optical digital signal transmission repeaters 5 and 6 provided for optical transmission between the stations 2 and 3, an upstream optical transmission line 9, and a downstream optical transmission line 10. Figure 1
Station 2 to station 3 and station 3
The relay operation from the mobile station to the station 2 is described. In this half-duplex transmission system, station 2
The transmission data from (or 3) is received at the port A (or D) of the optical digital signal transmission repeater 5 (or 6) through the electric transmission line 7 (or 8), and the received data is the port B (or E). Is relayed from the optical fiber to be converted into an optical signal and transmitted to the upstream optical transmission line 9 (or the downstream optical transmission line 10). Upstream optical transmission line 9 (or downstream optical transmission line 1
The optical signal from 0) is converted into an electrical signal at the port C (or F) of the optical digital signal transmission repeater 6 (or 5), and is relayed from the port D (or A) to the electrical transmission line 8
The data sent to (or 7) is received by the station 3 (or 2). The transmission data from the station 2 (or 3) can be simultaneously received by the stations 1 and 4.

In half-duplex transmission, data cannot be simultaneously transmitted from two or more stations. After each station and the optical digital signal transmission repeater have completed transmission of the transmission data or relay data, during the transmission stop period so as not to disturb the transmission line, the electric bus is put in a floating state,
Optical modulation is stopped on the optical bus. When noise above the reception detection level of the receiving circuit enters in the transmission halt state,
Wrong data will be received and normal transmission will not be possible.

It is generally known that in an electric transmission system, a transmission cable is easily affected by external noise, and in an optical transmission system, an optical / electrical converter is more easily affected by external noise than an optical fiber cable. . In particular, the optical reception level is much smaller than the electrical reception level and is easily affected by noise. FIG. 2 is an example of a functional block diagram of the optical digital signal relay transmission device shown in FIG. Each function of FIG. 2 will be described. In the port A (or D), an electric receiver 51 that outputs received data by receiving a low-level control signal OEB, and an electric transmitter that outputs transmitted data (relay data) by inputting a high-level control signal OEB. It is a bidirectional port having 52. The port B (or E) is a port having an optical transmitter that converts an electric signal into an optical signal. The port F (or C) is a port having an optical receiver that converts an optical signal into electricity.

After detecting that the preamble bit at the head of the reception data has a regular pulse width, the change point of the reception data is detected, and during that period, the status signal is turned ON and output, and the reception change point is detected. Turns off the status signal after Tcd bits or when the pulse width of the received data violates
The received carrier detection circuits 56 and 57, which are output in the following manner, and the status signals of the received carrier detection circuits 56 and 57 are input to determine the port that received first, and the first arrival priority determination circuit 58 that outputs as a status signal while the input is valid. , A data selector 55 that inputs the status signal of the first-arrival priority determination circuit 58 to select and output the received data from the port A or port C, and inputs a preamble of the received data to extract a clock signal synchronized with the received data And a re-timing circuit 510 for sampling the received data from the data selector 55 with the clock signal from the DPLL 59 and outputting it.
Transmission control circuit 511 for controlling transmission / reception output of the bidirectional electric receiver 51 and electric transmitter 52 on the side and switching control of transmission data on the port B side, the system clock input to the reception carrier detection circuits 56 and 57 and the DPLL 59. There is 512: fs (Hz). In the optical digital transmission repeater shown in FIG. 2, the reception carrier detection circuits 56 and 57 make a request to start the reception data relay operation.

FIG. 3 shows a detailed functional block diagram of a conventional received carrier detection circuit. Each function of FIG. 3 will be described. The reception register circuit 561 is a register for synchronizing the reception data with the system clock. The 1-bit pulse width detection circuit 562 is an N-ary up counter with a synchronous preset function so that the count value counted up to D0 to D3 of 562 is 1 bit or less so that the preset value: P
Input DA0 to PDAn. The period in which the / PRE of 562 is low is during the preset period. 562 /
When PRE becomes high level, it counts up, and when it counts over, 562-CO becomes high level, counting up, stopping the presetting operation, and requesting the start of relay operation. The change point detection circuit 563 detects a rising / falling change point of received data and outputs a pulse to the carrier signal gate circuit 564. The carrier signal gate circuit outputs a change-point pulse from 563-OUT after 562-CO goes high. Carrier sense timer 5
Reference numeral 65 is an L-advanced up counter with a synchronous preset function, and 565-CO1 becomes high level at count-over after Tcs after the change point of the received data disappears, and the count-up and the preset operation are stopped. Tcs should be larger than the interval of the longest change point of received data.
The preset value: PDA0 to PDAn is input to D0 to D3 of 5.

When either the 565-CO output or the RESET input is at a high level, the reset circuit 566 inputs it to the 1-bit pulse width detection circuit 562-CLR to clear the counter and perform count-up and preset stop operations. To release. It is necessary to raise the system clock frequency: fs (Hz) of the receiving circuit to cope with the increase in transmission speed, but the operating frequency of the system clock cannot be increased due to the operating limit of the device used. The detection capability of the 1-bit pulse width detection circuit 2 when the data transmission rate is increased with respect to the same system clock will be described. FIG. 4 shows the operation timing of the 1-bit pulse width detection circuit 2. Here, a hexadecimal counter is used. Fig. 4- (a)
Indicates the operation timing when a system clock N = 16 times the data transmission rate is used. If the allowable pulse width is 12 clocks, preset value = 15-
Set 12 = 3. Received pulses of 12 clocks or less are not detected. That is, it has the ability to remove noise pulses of 12 clocks or less. Fig. 4- (b) is Fig. 4-
The transmission speed is 4 for the same system clock as in (a).
The operation timing when the speed is doubled is shown. When the allowable pulse width is 3 clocks, the presett value = 15-2 =
Set to 13 (D: hexadecimal). Received pulses of 2 clocks or less are not detected. That is, since it has the ability to remove only noise pulses of 2 clocks or less,
This means that the noise margin is reduced as compared with (a).

[0008]

As described above, in the reception carrier detection circuit system of the digital signal relay transmission device, when the data transmission rate is increased with respect to the same system clock, the removable pulse width becomes narrow. Therefore, it is easily affected by noise, and normal data relay operation cannot be performed. Therefore, according to the present invention, even if the data transmission rate is increased with respect to the same system clock, the pulse width that can be removed is increased and is less susceptible to noise,
An object of the present invention is to provide a digital signal relay / transmission device of a reception carrier detection system, in which data relay operation is normally performed.

[0009]

In order to solve the above-mentioned drawbacks, the present invention provides a reception register circuit 561 for synchronizing reception data with a system clock, a 1-bit pulse width detection circuit 562, and a rise / reception of reception data. A change point detection circuit 563 that detects a falling change point and outputs a pulse to the carrier signal gate circuit 564 and an L-advance up counter with a synchronous preset function are used to count out 565 after Tcs after the change point of received data disappears. -C
In the digital signal relay transmission apparatus connected to the LAN using HDLC transmission, which comprises a carrier sense timer 565 that counts up and stops the presetting operation when O1 becomes high level, a period of M bits from the beginning of the received data. When the data change points are counted and the specified count value does not match, the re-detection operation is repeated, and only when they match, a reception carrier detection circuit for requesting the start of the relay operation is provided.

Further, a reception register circuit 561 for synchronizing the reception data with the system clock, a 1-bit pulse width detection circuit 562, a rising / falling change point of the reception data is detected, and a carrier signal gate circuit 564.
The change point detection circuit 563 that outputs a pulse to and the L-type up counter with the synchronous preset function counts up 56 times after Tcs after the change point of the received data disappears.
The 1-bit pulse width detection circuit 562 in the digital signal relay transmission device connected to the LAN using HDLC transmission, which includes a carrier sense timer 565 that counts up and stops the presetting operation when 5-CO1 becomes high While CO is at a high level, the change point counting circuit 5671 that counts the change points of the reception register circuit 561-Q0 data and outputs the count value to 5671-Q0 to QL, and the change point counting circuit 5671. Count value and 5
It is provided with an M-bit count discriminating circuit 5672 which compares the specified count value of 65A-CO2 and outputs a match from the 5672-Y1 only when they match and outputs a reset from the 5672-Y0 when they do not match. .

The digital signal transmission repeater of the present invention having such a function is capable of removing noise during a transmission suspension period even if an electric receiver or an optical receiver applied to a high speed transmission system malfunctions due to external noise. As a result, the normal operation of relaying received data becomes possible even if the data transmission rate is increased for the same system clock.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 5 shows a functional block diagram of the optical digital signal relay transmission apparatus of the present invention. The function different from the conventional one will be described with reference to FIG. The carrier signal gate circuit 564A is connected to the high level of 562-CO and then 5672-.
Outputs a change point pulse of data after the input becomes high level to Y. Carrier sense timer 565A is 562-
When (M-1) bits are counted after CO becomes high level, 565A-CO2 outputs high level. The reset circuit 566A outputs reset even when 5672-Y0 is at a high level. The Mbit pulse width detection circuit is composed of a change point counting circuit 5671 and an Mbit counting determination circuit 5672. The change point counting circuit 5671 counts the change points of the reception data 561-Q0 while the level of 562-CO is high and outputs the count value to 5671-Q0 to QL. The Mbit counting determination circuit 5672 in the subsequent stage compares the count value of the change point counting circuit 5671 with the specified count value of 565A-CO2, and outputs a match from 5672-Y1 only when they match. If they do not match, a reset output is output from 5672-Y0. 6 to 8 show the Mbit pulse width detection circuit 5
An example of operation timing of is shown. Here, an example of operation timing when the transmission speed is increased four times with respect to the same system clock as in FIG. 4A will be described. However, the 1-bit pulse width detection circuit 562 is a hexadecimal counter,
The preset value of PDA0 to PDA3 is D (hexadecimal number). The carrier sense timer 566A is a 32-bit counter, and the preset values of PDB0 to PDB4 are B (hexadecimal number). The change point counting circuit 5671 uses a 5-bit serial / parallel conversion register.

FIG. 6 shows an example of operation timing when normal received data is input. The detection accuracy of the pulse width of 5 bits from the beginning of the received data is 20 ± 2 seconds. That is, in the state of waiting for reception, there is the ability to remove except for the received data which has five changing points and the pulse width of 5 bits is within 18 to 22 clocks. 7 and 8 show examples of operation timing when abnormal reception data is input. FIG. 7 shows an example in which an abnormal pulse of about twice the normal reception data frequency: fd is input, and the fifth change point (71-Q) earlier than the normal time.
Since 4) is detected, it is cleared to the initial state. FIG. 8 shows an example in which an abnormal pulse of about ½ times the normal reception data frequency: fd is input. Even if the normal time elapses, the fifth change point (71-Q4) does not come and the initial state is set. Cleared.

[0014]

As described above, according to the digital signal relaying / transmitting apparatus of the present invention, when the data change points are counted during the period of M bits from the beginning of the received data and the count value does not match the specified count value. , By repeating the re-detection operation and providing the reception carrier detection circuit that requests the start of the relay operation only when they match, even if the electrical receiver or the optical receiver applied to the high-speed transmission system malfunctions due to external noise, Since the noise removal capability of the reception carrier detection circuit waiting for a no-signal state is improved, normal reception data detection and relay operation are possible even if the data transmission rate is increased for the same system clock.

[Brief description of drawings]

FIG. 1 shows a configuration of a half-duplex transmission system to which an optical digital signal transmission repeater is connected.

FIG. 2 shows a functional block diagram of a conventional digital signal transmission relay device.

FIG. 3 shows a detailed functional block diagram of a conventional received carrier detection circuit.

FIG. 4 shows a timing example of a conventional received carrier detection circuit.

FIG. 5 shows a detailed functional block diagram of a reception carrier detection circuit of the present invention.

FIG. 6 shows an example of operation timing when the reception carrier detection circuit of the present invention inputs normal reception data.

FIG. 7 shows an example of operation timing when abnormal reception data is input to the reception carrier detection circuit of the present invention.

FIG. 8 shows an example of operation timing when the reception carrier detection circuit of the present invention inputs abnormal reception data.

[Explanation of symbols]

1,2,3,4 station 5,6 Optical digital signal transmission repeater 7.8 Electrical transmission line 9 upstream optical transmission line 10 Downstream optical transmission line 51 electric receiver 52 Electric transmitter 53 Optical transmitter 54 Optical receiver 55 Data selector 56, 57 Carrier detection circuit 58 First-come-first-served priority determination circuit 59 DPLL 510 retiming circuit 511 Transmission control circuit 512 system clock 561 reception register 562 1-bit pulse width detection circuit 563 Change point detection circuit 564, 564A carrier signal gate circuit 565,565A Carrier sense timer circuit 566,566A reset circuit 567 Mbit pulse width detection circuit 5671 change point counting circuit 5672 Mbit counting discrimination circuit

Claims (2)

[Claims] 1. A reception register circuit 561 for synchronizing reception data with a system clock, a 1-bit pulse width detection circuit 562, a rising / falling change point of the reception data is detected, and a pulse is sent to a carrier signal gate circuit 564. The change point detection circuit 563 that outputs and the L-advanced up counter with the synchronous preset function count up after Tcs after the change point of the received data disappears 565-
In the digital signal relay transmission apparatus connected to the LAN using HDLC transmission, which comprises a carrier sense timer 565 that counts up and stops the presetting operation when CO1 becomes high level, a period of M bits from the beginning of the received data. An optical digital device equipped with a receive carrier detection circuit that counts the data change points in the medium and repeats the re-detection operation when the count value does not match, and requests the start of the relay operation only when the count values match. Signal relay transmission equipment. 2. A reception register circuit 561 for synchronizing reception data with a system clock, a 1-bit pulse width detection circuit 562, a rising / falling change point of the reception data is detected, and a pulse is sent to a carrier signal gate circuit 564. The change point detection circuit 563 that outputs and the L-advanced up counter with the synchronous preset function count up after Tcs after the change point of the received data disappears 565-
In a digital signal relay transmission device connected to a LAN using HDLC transmission, which comprises a carrier sense timer 565 for counting up and stopping presetting operation when CO1 becomes high level, the 1-bit pulse width detection circuit 562-CO During a high level, the change point counting circuit 5671 that counts the change points of the reception register circuit 561-Q0 data and outputs the count value to 5671-Q0 to QL; and the count value of the change point counting circuit 5671. And 565A-CO
Compared with the specified count value of 2, only 567 if they match
2-Y1 outputs coincidence output, and if they do not coincide, 5672-
M-bit counting discrimination circuit 567 for resetting output from Y0
2. An optical digital signal relay / transmission device comprising: