CN115666212B - Preparation method of superconducting quantum Josephson junction and related device - Google Patents
Preparation method of superconducting quantum Josephson junction and related device Download PDFInfo
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Abstract
The invention discloses a preparation method and a related device of a superconducting quantum Josephson junction, which are applied to the technical field of quantum chips and comprise the steps of etching a groove with a preset depth in a preset area on the surface of a substrate; filling a first superconducting layer in the groove; arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate; a second superconducting layer is provided on the surface of the substrate to cover the insulating layer. By firstly arranging a groove on the surface of a substrate and then filling a first superconducting layer in the groove, the first superconducting layer is designed to be sunken, so that for a Josephson junction of SIS, the overlapped surface of the second superconducting layer and the first superconducting layer is a plane, rather than an annular curved surface; meanwhile, due to the advantages, the thicknesses of the first superconducting layer and the second superconducting layer are not limited, namely, the limitation of the thickness relation of the first superconducting layer and the second superconducting layer is eliminated, and the large-scale preparation of the superconducting circuit is facilitated.
Description
Technical Field
The invention relates to the technical field of quantum chips, in particular to a preparation method of a superconducting quantum Josephson junction, a superconducting quantum chip and a superconducting quantum computer.
Background
The superconducting quantum technology realizes the crossover development in nearly twenty years, the coherence time is increased to 100us level from the initial ns level, the fidelity of single/double bits reaches the minimum threshold, the bit quantity breaks through 100 orders, and the superconducting quantum technology is one of the most possible fault-tolerant quantum computer schemes at present. Compared with other quantum computing schemes, the superconducting quantum has the advantages that the preparation of the bit is good in compatibility with the traditional semiconductor technology, and the expandability is strong. The josephson junction is used as a core device in a superconducting circuit, and a traditional preparation scheme of lift-off technology and double-angle evaporation technology is adopted, so that a plurality of problems exist, such as difficulty in controlling the dimension and shape of the evaporation josephson junction, expansion of special limitation processing preparation of double-angle evaporation equipment, reduction of device performance caused by residual glue between a substrate and superconducting metal, reduction of device performance caused by damage of ion mill to the substrate, limitation of large-scale preparation and the like. In order to solve the problems of the conventional preparation scheme, and meanwhile, the preparation method is more compatible with CMOS (Complementary Metal Oxide Semiconductor ) process equipment, scientific researchers propose a scheme for preparing Josephson junctions by adopting an etching process. The main process steps are as follows: firstly, evaporating a superconducting metal layer on a substrate, defining a first superconducting layer pattern by utilizing photoetching and etching processes, secondly, growing an insulating layer on the defined first superconducting metal layer by utilizing oxidation or other methods, then covering the first superconducting metal layer, and finally, preparing the Josephson junction with an SIS (superconducting-insulator-superconducting) structure by utilizing photoetching and etching processes.
However, in the prior art, because the first superconducting layer close to the substrate exists and protrudes out of the substrate by a certain height, the thickness of the second superconducting layer is larger than that of the first layer when the second superconducting layer is deposited, and the thickness of the second superconducting layer is generally required to be more than 2 times that of the first layer, so that breakage and disconnection at the lap joint of the second superconducting layer can be avoided; meanwhile, the contact surface of the first and second superconducting layers is an annular surface, and is not a single plane;
meanwhile, the thickness of the overlapped area of the first layer metal and the second layer metal, namely the Josephson junction area is larger than that of other areas, so that the plane of the substrate is uneven, and certain deviation exists in the size and the shape when the pattern of the second layer is defined by photoetching, so that the performance of the superconducting circuit is lower.
It is an urgent problem to be solved by those skilled in the art how to provide a solution that eliminates the first and second layer superconductive layer thickness relation limitations while being compatible with conventional CMOS process equipment and enabling large scale industrial production.
Disclosure of Invention
The invention aims to provide a preparation method of a superconducting quantum Josephson junction, which can eliminate the limitation of the relation between the thickness of a first layer and a second layer of superconducting layers; it is a further object of the invention to provide a superconducting quantum josephson junction, a superconducting quantum chip and a superconducting quantum computer that can eliminate the limitations of the first and second layer superconducting layer thickness relationship.
In order to solve the technical problems, the invention provides a preparation method of a superconducting quantum Josephson junction, which comprises the following steps:
etching a groove with a preset depth in a preset area on the surface of the substrate;
filling a first superconducting layer in the groove;
arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate;
providing a second superconducting layer covering the insulating layer on the surface of the substrate;
and etching the second superconducting layer to form a Josephson junction in the preset area.
Optionally, the etching the second superconducting layer to form a josephson junction in the preset area includes:
etching the second superconducting layer at the first preset position in the preset area to the first superconducting layer, and exposing the first superconducting layer at the first preset position;
and etching a second superconducting layer around a second preset position in the preset region, and forming a Josephson junction at the second preset position.
Optionally, the etching the second superconducting layer to form a josephson junction in the preset area includes:
and etching the second superconducting layer to form a Josephson junction and simultaneously form an additional circuit structure.
Optionally, after etching the second superconducting layer at the first preset position in the preset area to the first superconducting layer, exposing the first superconducting layer at the first preset position, the method further includes:
filling superconducting materials at the first preset positions;
etching the second superconducting layer around the second preset position in the preset area, and forming the Josephson junction at the second preset position comprises the following steps:
and after filling the superconducting materials, simultaneously etching the superconducting materials positioned around the first preset position in the second superconducting layer and the second superconducting layers positioned around the second preset position to form an additional circuit structure positioned at the first preset position and a Josephson junction positioned at the second preset position.
Optionally, filling the superconducting material at the first preset position includes:
growing a superconducting material on the surface of a sample formed after etching the second superconducting layer to the first superconducting layer;
polishing the surface of the sample after growing the superconducting material.
Optionally, after filling the superconducting material, etching the superconducting material around the first preset position in the second superconducting layer and the second superconducting layer around the second preset position at the same time, to form an additional circuit structure located at the first preset position and a josephson junction located at the second preset position includes:
After filling the superconducting materials, simultaneously etching the superconducting materials around the first preset position, the second superconducting layers around the second preset position and the second superconducting layers around the third preset position in the second superconducting layer to form an additional circuit structure at the first preset position, an additional circuit structure at the third preset position and a Josephson junction at the second preset position; the third preset position is located outside the preset area.
Optionally, the etching the second superconducting layer around the second preset position in the preset area, and forming the josephson junction at the second preset position includes:
and simultaneously etching a second superconducting layer positioned around the second preset position in the second superconducting layer and a second superconducting layer positioned around a third preset position outside the preset area to form a Josephson junction positioned at the second preset position and an additional circuit structure positioned at the third preset position.
Optionally, after etching the second superconducting layer around the second preset position in the second superconducting layer and the second superconducting layer around the third preset position outside the preset area at the same time, forming a josephson junction at the second preset position and an additional circuit structure at the third preset position, the method further includes:
Etching the insulating layer at the first preset position through a mask;
growing superconducting material at the first preset position through the mask;
stripping the mask to form an additional circuit structure at the first preset position; the additional circuit structure at the first preset position is electrically connected with the Josephson junction through the first superconducting layer.
Optionally, the etching the second superconducting layer around the second preset position in the preset area, and forming the josephson junction at the second preset position includes:
and etching a second superconducting layer around a second preset position in the preset region, and forming an additional circuit structure at the second preset position while forming the Josephson junction at the second preset position.
The invention also provides a superconducting quantum Josephson junction, which is prepared by the preparation method of the superconducting quantum Josephson junction.
The invention also provides a superconducting quantum chip, which comprises the Josephson junction prepared by the preparation method of the superconducting quantum Josephson junction.
The invention also provides a superconducting quantum computer, which comprises the superconducting quantum chip.
The invention provides a preparation method of a superconducting quantum Josephson junction, which comprises the following steps: etching a groove with a preset depth in a preset area on the surface of the substrate; filling a first superconducting layer in the groove; arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate; providing a second superconducting layer covering the insulating layer on the surface of the substrate; and etching the second superconducting layer to form a Josephson junction in a preset area.
By arranging the grooves on the surface of the substrate, the grooves are filled with the first superconducting layer, and the first superconducting layer is designed to be sunken, so that for Josephson junctions of SIS, the overlapped surface of the second superconducting layer and the first superconducting layer is a plane, rather than a circular curved surface; meanwhile, due to the advantages, the thickness of the first superconducting layer and the thickness of the second superconducting layer are not limited, namely, the limitation of the thickness relation of the first superconducting layer and the second superconducting layer is eliminated, so that the superconducting circuit is convenient to prepare.
The invention also provides a superconducting quantum Josephson junction, a superconducting quantum chip and a superconducting quantum computer, which have the same beneficial effects and are not repeated here.
Drawings
For a clearer description of embodiments of the invention or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
Fig. 1 to 7 are process flow diagrams of a preparation method of a superconducting quantum josephson junction according to an embodiment of the present invention;
fig. 8 to 12 are process flow diagrams of a method for fabricating a specific superconducting quantum josephson junction according to an embodiment of the present invention;
fig. 13 to 17 are process flow diagrams of another specific method for preparing a superconducting quantum josephson junction according to an embodiment of the present invention.
In the figure: 1. substrate, 2, first superconductive layer, 3, insulating layer, 4, second superconductive layer, 5, josephson junction, 6, additional circuit structure, 7, mask.
Detailed Description
The core of the invention is to provide a preparation method of a superconducting quantum Josephson junction. In the prior art, the thickness of the first layer of superconducting layer close to the substrate and protruding out of the substrate by a certain height is larger than that of the first layer when the second layer of superconducting layer is deposited, and the thickness of the second layer is generally required to be more than 2 times that of the first layer, so that the joint of the second layer of superconducting layer is ensured not to be broken; meanwhile, the contact surface of the first and second superconducting layers is an annular surface, and is not a single plane;
Meanwhile, the thickness of the overlapped area of the first layer metal and the second layer metal, namely the Josephson junction area is larger than that of other areas, so that the plane of the substrate is uneven, and certain deviation exists in the size and the shape when the pattern of the second layer is defined by photoetching, so that the performance of the superconducting circuit is lower.
The preparation method of the superconducting quantum Josephson junction provided by the invention comprises the following steps: etching a groove with a preset depth in a preset area on the surface of the substrate; filling a first superconducting layer in the groove; arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate; providing a second superconducting layer covering the insulating layer on the surface of the substrate; and etching the second superconducting layer to form a Josephson junction in a preset area.
By firstly arranging a groove on the surface of a substrate and then filling a first superconducting layer in the groove, the first superconducting layer is designed to be sunken, so that for a Josephson junction of SIS, the overlapped surface of the second superconducting layer and the first superconducting layer is a plane, rather than an annular curved surface; meanwhile, due to the advantages, the thickness of the first superconducting layer and the thickness of the second superconducting layer are not limited, namely, the limitation of the thickness relation of the first superconducting layer and the second superconducting layer is eliminated, so that the superconducting circuit is convenient to prepare.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 to 7, fig. 1 to 7 are process flow diagrams of a preparation method of a superconducting quantum josephson junction according to an embodiment of the present invention.
Referring to fig. 1, in an embodiment of the present invention, a method for preparing a superconducting quantum josephson junction includes:
s101: and etching a groove with a preset depth in a preset area of the surface of the substrate.
Referring to fig. 2, the specific structure of the josephson junction 5 to be prepared, e.g. the dimensions of the individual layers, etc., including the design thickness of the first superconductive layer 2 immediately adjacent to the substrate 1, needs to be predetermined prior to this step. Correspondingly, in this step, a groove corresponding to a preset depth is etched from a preset area on the surface of the substrate 1 according to the design thickness of the first superconducting layer 2, where the preset depth is the same as the design thickness of the first superconducting layer 2.
The above-mentioned predetermined area is an area where the josephson junction 5 is arranged and where the additional circuit structure 6 is subsequently needed to communicate with the josephson junction 5 via the first superconductive layer 2, which area may in particular be prepared by lithography or other process etching, where it is usually necessary to remove the native oxide layer of the substrate 1 before etching the substrate 1, in particular by a BOE (buffer oxide etch) cleaning process. The substrate 1 may be a silicon substrate 1, and the material of the substrate 1 is not particularly limited in the embodiment of the present invention, and may be any material as appropriate.
Specifically, in the step, the groove can be etched through a photoetching process, and the photoetching process firstly needs to carry out photoresist homogenizing photoetching to define a required pattern; and then etching the substrate 1 by adopting an etching process to form a groove with a required depth. Of course, the step of defining the required pattern by photoresist is a mask setting process, and other hard masks can be used for replacing the mask setting process.
S102: and filling the first superconducting layer in the groove.
Before this step, the removal of the substrate 1 and the native oxide layer on the surface of the groove may be continued, and specifically, the removal of the substrate 1 and the native oxide layer on the surface of the groove may be performed by a BOE cleaning process.
In this step, the first superconducting layer 2 is filled in the groove, the first superconducting layer 2 may be an aluminum film, and the thickness of the first superconducting layer 2 after filling the first superconducting layer 2 is generally equal to the depth of the groove. In this step the first superconductive layer 2 may be grown in the recess, in particular by a growth process.
Referring to fig. 3 and 4, in particular, in this step, the first superconducting layer 2 may be deposited on the surface of the substrate 1 to a thickness greater than the depth of the groove, and then the surface of the substrate 1 may be polished, for example, by planarizing the sample using a CMP (chemical mechanical polishing) process, to remove the first superconducting layer 2 on the surface of the substrate 1 until only the first superconducting layer 2 in the groove remains, so that the first superconducting layer 2 is filled in the groove, and the thickness of the first superconducting layer 2 is equal to the depth of the groove. Of course, in the embodiment of the present invention, the first superconductive layer 2 may be filled in the groove by other processes, and the specific content thereof is not limited herein.
S103: and arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate.
In this step, the insulating layer 3 is disposed on the surface of the first superconducting layer 2, and at this time, due to the submerged design of the first superconducting layer 2, the contact surface between the first superconducting layer 2 and the insulating layer 3 is a flat surface, and the upper surface of the insulating layer 3 is flush with the surface of the substrate 1, i.e. the upper surface of the insulating layer 3 is flush with the edge of the groove, so that after this step, the surface of the substrate 1 is a flat surface, and the first superconducting layer 2 and the insulating layer 3 can fill the groove.
Referring to fig. 5 and fig. 6, specifically, the insulating layer 3 may be an oxide layer, and the corresponding step may specifically include: the substrate 1 provided with the first superconductive layer 2 is oxidized to obtain an oxide layer as the insulating layer 3. Namely, in the step, the sample filled with the first superconducting layer 2 can be processed for a period of time in a high-purity high-pressure oxygen environment, so that an oxide layer is formed on the surfaces of the substrate 1 and the first superconducting layer 2; thereafter, the above sample may be treated with a dry HF gas to remove the oxide layer on the surface of the substrate 1 while leaving the oxide layer on the surface of the first superconducting layer 2 as the above insulating layer 3. And here the oxide layer on the surface of the substrate 1 is removed, for example the silicon oxide layer is removed to a thickness of typically around 2 nm. Firstly, the thickness of the oxide layer is very thin, and secondly, in this step, the sample filled with the first superconducting layer 2 is processed under the high-purity high-pressure oxygen environment, the processing process is equivalent to extruding oxygen atoms into the surface of the first superconducting layer 2, the material with a certain thickness on the surface of the first superconducting layer is oxidized into the protective layer, and the process of extruding oxygen atoms hardly causes the thickness increase of the oxidized material, so that the upper surface of the insulating layer 3 can be ensured to be level with the surface of the substrate 1.
S104: a second superconducting layer is provided on the surface of the substrate to cover the insulating layer.
Referring to fig. 7, in this step, the second superconducting layer 4 covering the insulating layer 3 may be grown on the surface of the substrate 1 based on a growth process in particular. Before growth, the sample treated by S103 is transferred into a vacuum chamber through a vacuum pipeline and is subjected to high-purity N 2 After the purge cleaning, a second aluminum film, i.e., a second superconducting layer 4, is grown, and the thickness of the second superconducting layer 4 may be H2. It should be noted that in this step, the second superconductive layer 4 covers not only the film layer within the recess, but also other areas of the surface of the substrate 1, so as to facilitate the subsequent preparation of the additional circuit structure 6.
S105: and etching the second superconducting layer to form a Josephson junction in a preset area.
In this step, the preparation of the josephson junction 5 may be completed by etching the predetermined area, i.e. the area where the recess is located, based on the second superconducting layer 4 to form the josephson junction 5. The details of this step will be described in detail in the following embodiments of the present invention, and will not be described herein.
Specifically, the step may specifically include: etching the second superconducting layer at the first preset position in the preset area to the first superconducting layer, and exposing the first superconducting layer at the first preset position; and etching a second superconducting layer around a second preset position in the preset region, and forming a Josephson junction at the second preset position.
The step of etching the second superconducting layer at the first preset position in the preset area to the first superconducting layer to expose the first superconducting layer at the first preset position is mainly used for removing the insulating layer at the first preset position to expose the first superconducting layer at the first preset position. This first preset position mainly serves as a junction outside the pair of josephson junctions, so that it is necessary to expose the first superconductive layer of the first preset position. Of course, an additional circuit structure may be further disposed at the first preset position, and its specific details will be described in the following embodiments of the invention. If an additional circuit configuration is provided at the first predetermined location, the additional circuit configuration at this location, in addition to its own function, also serves as a junction outside the pair of josephson junctions.
And etching the second superconducting layer around the second preset position in the preset area, and forming a Josephson junction at the second preset position, wherein the second superconducting layer around the second preset position is etched, and the second superconducting layer at the second preset position is reserved as one end of the Josephson junction to form the Josephson junction. At this time, the second superconducting layer at the second preset position is used as another connecting terminal of the josephson junction and is connected with other additional circuit structures.
It should be noted that, there is no sequence between the two steps, that is, the insulating layer at the first preset position is removed first, and then the josephson junction is formed at the second preset position; or forming the josephson junction at the second preset position and then etching at the first preset position, the specific content of which will be described in detail in the following embodiments of the invention.
Specifically, the step of etching the second superconducting layer to form the josephson junction in the preset area may specifically include: and etching the second superconducting layer to form a Josephson junction and simultaneously form an additional circuit structure. I.e. based on said second superconducting layer 4, additional circuit structures 6 and josephson junctions 5 can be formed simultaneously; the additional circuit structure 6 may be electrically connected to the josephson junction 5. Namely, in this step, the josephson junction 5 and other additional circuit structures 6 can be prepared simultaneously based on the second superconducting layer 4, so that the synchronous preparation and connection of the josephson junction 5 and other structural devices of the superconducting circuit can be realized, and the occurrence of parasitic junction conditions can be avoided.
Specifically, the preparation of the josephson junction 5 and the additional circuit structure 6 may be performed by an etching process or by a lift-off process. The details of the two preparation processes will be described in detail in the following embodiments of the invention, and will not be described here again.
The additional circuit structure 6 may be a capacitor, a resistor, or other components possibly arranged in the chip, or even a part of components, and the additional circuit structure 6 may even be just a connection end, or a section of wire, where appropriate, and is not specifically limited herein.
The preparation method of the superconducting quantum Josephson junction provided by the embodiment of the invention comprises the following steps: etching a groove with a preset depth in a preset area on the surface of the substrate 1; filling a first superconducting layer 2 in the groove; arranging an insulating layer 3 on the surface of the first superconducting layer 2, so that the contact surface between the first superconducting layer 2 and the insulating layer 3 is a flat surface, and the upper surface of the insulating layer 3 is flush with the surface of the substrate 1; a second superconducting layer 4 covering the insulating layer 3 is arranged on the surface of the substrate 1; the second superconductive layer 4 is etched to form a josephson junction 5 in a predetermined region.
By firstly arranging a groove on the surface of the substrate 1 and then filling the first superconducting layer 2 in the groove, the first superconducting layer is designed to be sunken, so that for the Josephson junction 5 of SIS, the overlapped surface of the second superconducting layer and the first superconducting layer is a plane, rather than an annular curved surface; meanwhile, due to the advantages, the thicknesses of the first superconducting layer 2 and the second superconducting layer are not limited, namely, the limitation of the thickness relation of the first superconducting layer and the second superconducting layer is eliminated, so that the superconducting circuit is convenient to manufacture.
The specific details of the preparation method of the superconducting quantum josephson junction provided by the invention are described in the following embodiments of the invention.
Referring to fig. 8 to 12, fig. 8 to 12 are process flow diagrams of a specific preparation method of a superconducting quantum josephson junction according to an embodiment of the present invention.
In the invention, two specific preparation methods of the superconducting quantum Josephson junction are provided together, and synchronous preparation of the Josephson junction 5 and other structural devices of a superconducting circuit can be realized. The preparation method of the superconducting quantum Josephson junction provided by the embodiment of the invention is specifically prepared based on an etching process, and can realize synchronous preparation and connection of the Josephson junction 5 and other structural devices of a superconducting circuit.
Referring to fig. 8, in an embodiment of the invention, a method for preparing a superconducting quantum josephson junction includes:
s201: and etching a groove with a preset depth in a preset area of the surface of the substrate.
S202: and filling the first superconducting layer in the groove.
S203: and arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate.
S204: a second superconducting layer is provided on the surface of the substrate to cover the insulating layer.
The above S201 to S204 are substantially identical to S101 to S104 in the above embodiment of the present invention, and reference is made to the above embodiment of the present invention for details, which are not described herein.
S205: etching the second superconducting layer at the first preset position in the preset area to the first superconducting layer, and exposing the first superconducting layer at the first preset position.
Referring to fig. 9, it is first necessary to determine the position where the additional circuit structure 6 is formed in the above-described preset area, i.e., the first preset position, before this step. In this step, however, the insulating layer 3 at the first predetermined position is removed, so that the additional circuit structure 6 at the first predetermined position can be electrically connected to the first superconductive layer 2. In this step, the first preset position may be etched by a photolithography process, from the second superconducting layer 4 to the first superconducting layer 2, so as to remove the insulating layer 3 at the first preset position.
The photoetching process in the step specifically comprises the following steps: carrying out spin coating treatment on the sample provided with the second superconducting layer 4; photoetching the sample to define a required pattern; then, etching the second superconducting layer 4 at a first preset position by using an etching process until the first superconducting layer 2 is exposed, wherein the etching depth H2 of the step is required to meet the requirement that H2 is more than H2; and finally, removing the photoresist to complete the photoetching process.
S206: filling superconducting material at a first preset position.
The oxide layer exposed on the surface of the sample needs to be removed again before this step, so as to expose the second superconductive layer 4 and the first superconductive layer 2 at the predetermined position. Thereafter, a superconducting material is filled in the first predetermined position, and the specific material of the superconducting material is generally the same as that of the second superconducting layer 4 and the first superconducting layer 2. Specifically, the process of removing the exposed oxide layer on the surface of the sample may specifically be to send the sample into a high vacuum chamber, and clean the sample by using ion milling (ion milling) to completely remove the alumina layer on the surface of the aluminum layer.
Referring to fig. 10 and 11, specifically, this step generally includes: growing a superconducting material on the surface of a sample formed after etching the second superconducting layer to the first superconducting layer; polishing the surface of the sample after growing the superconducting material. Specifically, the step can grow the superconducting material on the whole surface of the sample, the thickness H3 of the superconducting material is required to meet the requirement that H3> H2+H2-H2, namely, the grown superconducting material at least can fill the concave etched when the second superconducting layer 4 to the first superconducting layer 2 are etched.
And then, carrying out planarization treatment on the sample growing with the superconducting material by utilizing a CMP process until the surface of the sample is completely flat, and enabling the thickness of the second superconducting layer 4 to reach a thickness value H4 designed for preparing structures such as electronic components and the like so as to facilitate the setting of subsequent structures. The specific value of H4 is not specifically limited in the embodiment of the present invention, and may be equal to H2.
S207: after filling the superconducting material, simultaneously etching the superconducting material around the first preset position in the second superconducting layer and the second superconducting layer around the second preset position to form an additional circuit structure at the first preset position and a Josephson junction at the second preset position.
In particular, in this step, the second superconducting layer 4 reaching H4 based on the thickness value may be formed by a photolithography process or other process, the josephson junction 5 at the second preset position and the additional circuit structure 6 at the first preset position in the preset region may be simultaneously formed in one etching process, and the josephson junction 5 and the additional circuit structure 6 at the preset position may be electrically connected to each other based on the first superconducting layer 2.
Referring to fig. 12, specifically, since the above step is outside the preset area, the second superconductive layer 4 is also disposed on the surface of the substrate 1, the step may be specifically: after filling the superconducting materials, simultaneously etching the superconducting materials around the first preset position, the second superconducting layers around the second preset position and the second superconducting layers around the third preset position in the second superconducting layer to form an additional circuit structure at the first preset position, an additional circuit structure at the third preset position and a Josephson junction at the second preset position; the third preset position is located outside the preset area. I.e. the additional circuit structure 6 at the third preset position outside the preset area, the josephson junction 5 at the second preset position inside the preset area and the additional circuit structure 6 at the first preset position can be formed simultaneously, so as to simplify the manufacturing process.
The above-mentioned process of etching the additional circuit structure 6 and the josephson junction 5 may be a photolithographic process, which may specifically be: carrying out spin coating treatment on the sample filled with the superconducting material; defining a required pattern by photoetching; the excess second superconductive layer 4 is removed by means of an etching process based on the defined pattern, until no excess second superconductive layer 4 is present on the surface of the substrate 1.
It should be noted that, in the embodiment of the present invention, the lower end of the josephson junction 5 may be connected to the additional circuit structure 6 located at the first preset position through the first superconducting layer 2, where the additional circuit structure 6 located at the first preset position corresponds to an external connection end of the josephson junction 5; the structure formed by the second superconducting layer 4 at the upper end of the josephson junction 5 also needs to be connected with other additional circuit structures 6, for example, the structure formed by the second superconducting layer 4 at the upper end of the josephson junction 5 can form a capacitor with other additional circuit structures 6, and the structure corresponds to the connection of a capacitor at the upper end of the josephson junction 5; the structure formed by the second superconducting layer 4 at the upper end of the josephson junction 5 can also be used as other additional circuit structures 6, such as resistors, wires, etc., which all represent that the josephson junction 5 is connected with other structures, so that the upper end of the josephson junction 5 is connected with the other additional circuit structures 6 to form a complete circuit structure. That is, the step of forming the josephson junction in the embodiments of the present invention may specifically include: and etching a second superconducting layer around a second preset position in the preset region, and forming an additional circuit structure at the second preset position while forming the Josephson junction at the second preset position. The structure formed in the second predetermined position can then be used as an end of the josephson junction, and can be used as an entire or part of the additional circuit structure 6 to form a complete circuit, depending on the specific shape. Of course, the additional circuit structure 6 at the second preset position and the additional circuit structure 6 at the first preset position and the third preset position may be prepared simultaneously in the same etching step.
According to the preparation method of the superconducting quantum Josephson junction, provided by the embodiment of the invention, a partial circuit sinking design is adopted, a structural design mode that a circuit is embedded in a substrate 1 is adopted, an insulating layer 3 in the SIS structure of the Josephson junction 5 is a single plane, but not an annular curved surface, and the thickness of a first superconducting layer and a second superconducting layer can be omitted without relation limitation; meanwhile, the Josephson junction 5 and other circuit structure devices of the superconducting circuit are synchronously prepared, so that the defect that the traditional method can only be used for preparing the devices independently is avoided; the Josephson junctions 5 prepared in the embodiment of the invention are all target junctions, and parasitic junctions cannot occur in the preparation process of the superconducting circuit, so that other processes are not needed to eliminate the parasitic junctions; the preparation method and the equipment provided by the embodiment of the invention are completely compatible with the existing CMOS processing preparation technology, and can realize large-scale industrialized preparation.
The specific details of another preparation method of the superconducting quantum josephson junction provided by the invention are described in the following examples of the invention.
Referring to fig. 13 to 17, fig. 13 to 17 are process flow diagrams of another specific method for preparing a superconducting quantum josephson junction according to an embodiment of the present invention.
The preparation method of the superconducting quantum Josephson junction provided by the embodiment of the invention is specifically based on stripping technology preparation, and can realize synchronous preparation of the Josephson junction 5 and other structural devices of a superconducting circuit.
Referring to fig. 3, in an embodiment of the invention, a method for preparing a superconducting quantum josephson junction includes:
s301: and etching a groove with a preset depth in a preset area of the surface of the substrate.
S302: and filling the first superconducting layer in the groove.
S303: and arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate.
S304: a second superconducting layer is provided on the surface of the substrate to cover the insulating layer.
The above S301 to S304 are substantially identical to S101 to S104 in the above embodiment of the present invention, and reference is made to the above embodiment of the present invention for details, which are not described herein.
S305: and etching the second superconducting layer around the second preset position in the second superconducting layer and the second superconducting layer around the third preset position outside the preset area to form a Josephson junction at the second preset position and an additional circuit structure at the third preset position.
Referring to fig. 14, in this step, first, based on one etching process, the device structure may be simultaneously prepared on the second superconducting layer 4 at a third preset position outside the preset area, that is, the third preset position on the surface of the substrate 1, in the second superconducting layer 4 at the second preset position in the preset area, that is, the area where the groove is located, specifically, the additional circuit structure 6 may be prepared at the third preset position outside the preset area, and meanwhile, the josephson junction 5 may be prepared at the second preset position in the preset area, so that synchronous preparation of the additional circuit structure 6 and the josephson junction 5 may be realized.
The step of forming the josephson junction in the embodiment of the present invention may specifically include: and etching a second superconducting layer around a second preset position in the preset region, and forming an additional circuit structure at the second preset position while forming the Josephson junction at the second preset position. The structure formed in the second predetermined position can then be used as an end of the josephson junction, and can be used as an entire or part of the additional circuit structure 6 to form a complete circuit, depending on the specific shape. Of course, the additional circuit structure 6 at the second preset position and the additional circuit structure 6 at the third preset position may be prepared simultaneously in the same etching step.
The etching process may specifically be a photolithography process, where the photolithography process specifically includes: carrying out spin coating treatment on the sample provided with the second superconducting layer 4; photoetching the sample to define a required pattern; and then etching to form the additional circuit structure 6 at the third preset position outside the preset area and the Josephson junction 5 at the second preset position in the preset area by using an etching process so as to remove the redundant second superconducting layer 4 on the surface of the sample.
S306: and etching the insulating layer at a first preset position through a mask.
Referring to fig. 15, it is first necessary to determine the position where the additional circuit structure 6 is formed in the above-described preset area, i.e., the first preset position, before this step. In this step, however, the insulating layer 3 at the first predetermined position is removed, so that the additional circuit structure 6 at the first predetermined position can be electrically connected to the first superconductive layer 2.
In this step, it is first necessary to provide a mask 7 on the surface of the sample etched with the josephson junction 5, and the mask 7 may be specifically provided by photoresist based on a photolithography process and exposing to light to provide the mask 7, or the mask 7 may be provided by other means, which is not specifically limited herein. When the mask 7 is provided based on a photolithography process, this may include in particular: carrying out spin coating treatment on the sample etched with the Josephson junction 5; photolithography defines the desired pattern area, forming mask 7.
In this step, the insulating layer 3 is etched at the first preset position through the mask 7 to remove the insulating layer 3 at the first preset position. Specifically, the step may specifically include etching the exposed photoresist based on an etching process to expose the insulating layer 3 at the first preset position, and further etching the insulating layer 3 to remove the insulating layer 3 at the first preset position. The step may specifically remove the exposed insulating layer 3 using ion milling in a high vacuum chamber.
S307: and growing superconducting materials at the first preset position through the mask.
Referring to fig. 16, in this step, a superconducting material, which is generally the same as the above-described second superconducting layer 4 and first superconducting layer 2, is grown on the surface of the sample from which the insulating layer 3 at the first preset position is removed based on the growth process. In this step it is generally necessary to grow the superconducting material in a high vacuum chamber, which is in communication with the first superconducting layer 2 at a first preset position.
S308: the mask is stripped to form additional circuit structures at the first predetermined locations.
Referring to fig. 17, in an embodiment of the invention, the additional circuit structure 6 at the first preset position is electrically connected to the josephson junction 5 via the first superconductive layer 2. In this step the mask 7 may be stripped off based on a stripping process to remove excess superconducting material, forming additional circuit structures 6 at the first preset locations, which additional circuit structures 6 and josephson junctions 5 may be electrically connected by the first superconducting layer 2.
It should be noted that, in the embodiments of the present invention and the embodiments of the present invention described above, the additional circuit structure 6 is other structures except the josephson junction 5 in the quantum chip; the substrate 1 can be high-resistance silicon or sapphire, and the sapphire does not need BOE or HF treatment, so that the preparation process can be further simplified; the materials of the first superconducting layer 2 and the second superconducting layer 4 may be Al, ta, nb, tiN and other superconducting metals and metal compounds, and the insulating layer 3 may be oxide of the metals or other insulating materials; the superconductive layers of different layers can be made of the same material or different materials; the photolithography patterns in the above figures are only schematic, and can be designed into other patterns according to design requirements, the number of the josephson junctions 5 can be 1 or more, the josephson junctions 5 can be in a serial or parallel form, and the sizes of the josephson junctions 5 can be inconsistent; the photoresist is a term of mask, not necessarily a photoresist, but may be in the form of other hard masks. The film thickness at the different josephson junctions 5 may be different and set independently, depending on design requirements.
According to the preparation method of the superconducting quantum Josephson junction, provided by the embodiment of the invention, a partial circuit sinking design is adopted, a structural design mode that a circuit is embedded in a substrate 1 is adopted, an insulating layer 3 in the SIS structure of the Josephson junction 5 is a single plane, but not an annular curved surface, and the thickness of a first superconducting layer and a second superconducting layer can be omitted without relation limitation; meanwhile, the Josephson junction 5 and other circuit structure devices of the superconducting circuit are synchronously prepared, so that the defect that the traditional method can only be used for preparing the devices independently is avoided; the Josephson junctions 5 prepared in the embodiment of the invention are all target junctions, and parasitic junctions cannot occur in the preparation process of the superconducting circuit, so that other processes are not needed to eliminate the parasitic junctions; the preparation method and the equipment provided by the embodiment of the invention are completely compatible with the existing CMOS processing preparation technology, and can realize large-scale industrialized preparation.
The invention also provides a superconducting quantum Josephson junction, which is in particular a quantum chip structure prepared by the preparation method of the superconducting quantum Josephson junction provided by any one of the embodiments of the invention.
The preparation method of the superconducting quantum Josephson junction provided by the embodiment of the invention can cancel the limitation of the relation between the thickness of the first layer and the thickness of the second layer superconducting layer, and is convenient for setting a superconducting circuit, so that the superconducting quantum Josephson junction has lower preparation cost. The specific structure and preparation process of the superconducting quantum josephson junction provided by the invention are described in detail in the above embodiments of the invention, and are not described here again.
The invention also provides a superconducting quantum chip, which specifically comprises a quantum chip structure prepared by the preparation method of the superconducting quantum Josephson junction provided by any one of the embodiments of the invention.
The preparation method of the superconducting quantum Josephson junction provided by the embodiment of the invention can cancel the limitation of the relation between the thickness of the first layer and the thickness of the second layer superconducting layer, and is convenient for setting a superconducting circuit, so that the superconducting quantum chip has lower preparation cost. The specific structure and preparation process of the josephson junction in the superconducting quantum chip provided by the invention are described in detail in the above embodiments of the invention, and are not described here again. Other structures related to the superconducting quantum chip may refer to the prior art, and again are not particularly limited.
The invention also provides a superconducting quantum computer, which particularly comprises the superconducting quantum chip provided by any one of the embodiments of the invention.
The preparation method of the superconducting quantum chip by using the superconducting quantum Josephson junction can cancel the limitation of the relation of the thickness of the first layer and the second layer superconducting layers, and is convenient for setting a superconducting circuit, so that the superconducting quantum computer has lower preparation cost in the embodiment of the invention. The specific structure and preparation process of the josephson junction in the superconducting quantum computer provided by the invention are described in detail in the above embodiments of the invention, and are not described here again. Other structures related to superconducting quantum computers can refer to the prior art, and again are not particularly limited.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The preparation method of the superconducting quantum Josephson junction provided by the invention is described in detail. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (12)
1. A method for preparing a superconducting quantum josephson junction, comprising:
etching a groove with a preset depth in a preset area on the surface of the substrate;
filling a first superconducting layer in the groove;
arranging an insulating layer on the surface of the first superconducting layer, so that the contact surface between the first superconducting layer and the insulating layer is a flat surface, and the upper surface of the insulating layer is flush with the surface of the substrate;
providing a second superconducting layer covering the insulating layer on the surface of the substrate;
and etching the second superconducting layer to form a Josephson junction in the preset area.
2. The method of claim 1, wherein the etching the second superconducting layer to form a josephson junction in the predetermined region comprises:
etching the second superconducting layer at the first preset position in the preset area to the first superconducting layer, and exposing the first superconducting layer at the first preset position;
and etching a second superconducting layer around a second preset position in the preset region, and forming a Josephson junction at the second preset position.
3. The method of claim 2, wherein the etching the second superconducting layer to form a josephson junction in the predetermined region comprises:
and etching the second superconducting layer to form a Josephson junction and simultaneously form an additional circuit structure.
4. The method of claim 3, further comprising, after etching the second superconducting layer at the first preset location in the preset region to the first superconducting layer, exposing the first superconducting layer at the first preset location:
filling superconducting materials at the first preset positions;
etching the second superconducting layer around the second preset position in the preset area, and forming the Josephson junction at the second preset position comprises the following steps:
And after filling the superconducting materials, simultaneously etching the superconducting materials positioned around the first preset position in the second superconducting layer and the second superconducting layers positioned around the second preset position to form an additional circuit structure positioned at the first preset position and a Josephson junction positioned at the second preset position.
5. The method of claim 4, wherein filling the first predetermined location with superconducting material comprises:
growing a superconducting material on the surface of a sample formed after etching the second superconducting layer to the first superconducting layer;
polishing the surface of the sample after growing the superconducting material.
6. The method of claim 4, wherein simultaneously etching the superconducting material in the second superconducting layer around the first preset location and the second superconducting layer around the second preset location after filling the superconducting material to form the additional circuit structure in the first preset location and the josephson junction in the second preset location comprises:
after filling the superconducting materials, simultaneously etching the superconducting materials around the first preset position, the second superconducting layers around the second preset position and the second superconducting layers around the third preset position in the second superconducting layer to form an additional circuit structure at the first preset position, an additional circuit structure at the third preset position and a Josephson junction at the second preset position; the third preset position is located outside the preset area.
7. The method of claim 3, wherein the etching the second superconducting layer around the second preset location in the preset area, the forming the josephson junction at the second preset location comprising:
and simultaneously etching a second superconducting layer positioned around the second preset position in the second superconducting layer and a second superconducting layer positioned around a third preset position outside the preset area to form a Josephson junction positioned at the second preset position and an additional circuit structure positioned at the third preset position.
8. The method of claim 7, wherein forming josephson junctions at second preset locations and additional circuit structures at third preset locations after simultaneously etching second superconducting layers of the second superconducting layers around the second preset locations and second superconducting layers of the third preset locations outside the preset regions further comprises:
etching the insulating layer at the first preset position through a mask;
growing superconducting material at the first preset position through the mask;
stripping the mask to form an additional circuit structure at the first preset position; the additional circuit structure at the first preset position is electrically connected with the Josephson junction through the first superconducting layer.
9. The method of claim 2, wherein the etching the second superconducting layer around the second preset location in the preset area, the forming the josephson junction at the second preset location comprising:
and etching a second superconducting layer around a second preset position in the preset region, and forming an additional circuit structure at the second preset position while forming the Josephson junction at the second preset position.
10. A superconducting quantum josephson junction, characterized in that it is a josephson junction prepared by the method of preparing a superconducting quantum josephson junction according to any of claims 1 to 9.
11. A superconducting quantum chip comprising a josephson junction prepared by the method of preparing a superconducting quantum josephson junction according to any one of claims 1 to 9.
12. A superconducting quantum computer comprising the superconducting quantum chip of claim 11.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58125880A (en) * | 1982-01-22 | 1983-07-27 | Hitachi Ltd | Josephson junction element |
| CN111937168A (en) * | 2018-03-23 | 2020-11-13 | 国际商业机器公司 | Vertical Josephson junction superconducting devices |
| CN114256407A (en) * | 2020-09-25 | 2022-03-29 | 合肥本源量子计算科技有限责任公司 | Preparation method of two Josephson junctions connected in parallel and quantum bit device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58125880A (en) * | 1982-01-22 | 1983-07-27 | Hitachi Ltd | Josephson junction element |
| CN111937168A (en) * | 2018-03-23 | 2020-11-13 | 国际商业机器公司 | Vertical Josephson junction superconducting devices |
| CN114256407A (en) * | 2020-09-25 | 2022-03-29 | 合肥本源量子计算科技有限责任公司 | Preparation method of two Josephson junctions connected in parallel and quantum bit device |
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