WO2023221311A1

WO2023221311A1 - Semiconductor structure and forming method therefor

Info

Publication number: WO2023221311A1
Application number: PCT/CN2022/111969
Authority: WO
Inventors: 武宏发; 刘忠明; 夏军; 刘淼; 陈龙阳; 于业笑; 占梦丹
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-05-19
Filing date: 2022-08-12
Publication date: 2023-11-23
Also published as: CN117156843A

Abstract

Provided in the present disclosure are a semiconductor structure and a forming method therefor. The forming method for the semiconductor structure comprises: providing a substrate, the substrate comprising an active region and an isolation region; forming a first mask stack layer on the substrate; etching part of the first mask stack layer and the substrate to form a first contact hole in the substrate so as to expose part of the active region; forming a second initial dielectric layer, the second initial dielectric layer filling the first contact hole and covering the top portion of the mask stack layer; removing part of the second initial dielectric layer and the first mask stack layer to form a first dielectric layer and a second dielectric layer, the top portions of the first dielectric layer and the second dielectric layer being flush; forming a bit line stack layer on the first dielectric layer and the second dielectric layer, and performing patterning processing on the bit line stack layer, the first dielectric layer and the second dielectric layer at the same time, so that the bit line stack layer forms a bit line structure, and the first dielectric layer and the second dielectric layer form a bit line contact structure, wherein the bit line structure is electrically connected to the substrate by means of the bit line contact structure.

Description

Semiconductor structures and methods of forming them

This disclosure is based on a Chinese patent application with application number 202210557636.0, application date is May 19, 2022, and the application name is "Semiconductor Structure and Formation Method Thereof", and claims the priority of the Chinese patent application. This disclosure is incorporated by reference in its entirety.

Technical field

The present disclosure relates to, but is not limited to, a semiconductor structure and a method of forming the same.

Background technique

With the development of semiconductor technology, dynamic random access memory has been widely used. This dynamic random access memory has extremely high requirements on the morphology of the bit line structure.

In existing dynamic random access memories, there is usually a height difference on the top surface of the bit line contact structure, which leads to a height difference in the subsequently formed metal layer, affecting the flatness of the bit line structure, and ultimately affecting the electrical properties of the dynamic random access memory. performance.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a semiconductor structure and a method of forming the same:

A first aspect of the present disclosure provides a method of forming a semiconductor structure, including:

providing a substrate, the substrate including an active region and an isolation region;

forming a first mask stack on the substrate;

Etching a portion of the first mask stack and the substrate, forming a first contact hole in the substrate, the first contact hole exposing a portion of the active region;

Forming a second initial dielectric layer that fills the first contact hole and covers the top of the mask stack;

Remove part of the second initial dielectric layer and the first mask stack to form a first dielectric layer and a second dielectric layer, and the tops of the first dielectric layer and the second dielectric layer are flush;

A bit line stack is formed on the first dielectric layer and the second dielectric layer, and the bit line stack, the first dielectric layer and the second dielectric layer are patterned simultaneously so that The bit line stack forms a bit line structure, and the first dielectric layer and the second dielectric layer form a bit line contact structure; wherein the bit line structure is implemented with the substrate through the bit line contact structure. Electrical connection.

Wherein, removing part of the second initial dielectric layer and the first mask stack to form the first dielectric layer and the second dielectric layer includes:

The first mask stack includes a first initial dielectric layer and a first sacrificial layer stacked in sequence, and the top of the second initial dielectric layer is higher than the top of the first sacrificial layer;

Remove the first sacrificial layer, part of the first initial dielectric layer and part of the second initial dielectric layer, and the first initial dielectric layer and the second initial dielectric layer form the first dielectric layer and the second initial dielectric layer respectively. the second dielectric layer.

Wherein, an etching process is used to remove the first sacrificial layer, part of the first initial dielectric layer and part of the second initial dielectric layer; the first sacrificial layer, the first initial dielectric layer and the third initial dielectric layer The etching rates of the two initial dielectric layers are the same.

Wherein, a chemical mechanical polishing process is used to remove the first sacrificial layer, part of the first initial dielectric layer and part of the second initial dielectric layer; in the chemical mechanical polishing process, the polishing liquid has a certain effect on the first sacrificial layer, The selection ratios of the first initial dielectric layer and the second initial dielectric layer are the same.

Wherein, the etching portion of the first mask stack and the substrate, and forming a first contact hole in the substrate includes:

The first mask stack is patterned, and the substrate is etched using the patterned first mask stack as a mask to form the first contact hole.

It also includes a first isolation layer located between the first dielectric layer and the substrate.

Wherein, before forming the first mask stack on the substrate, a first initial isolation layer is formed on the substrate, and part of the first mask stack and part of the first initial isolation layer are etched. and a portion of the substrate, forming a first contact hole in the substrate and simultaneously forming a first isolation layer.

Wherein, the first dielectric layer and the second dielectric layer are made of the same material.

A second aspect of the present disclosure provides a semiconductor structure including:

A substrate including an active region and an isolation region;

The substrate includes a first contact hole, and the bottom of the first contact hole exposes the active area;

A bit line contact structure, part of the bit line contact structure is located in the first contact hole, and the bottom of the bit line contact structure is connected to the active area;

A bit line structure is electrically connected to the substrate through the bit line contact structure.

Wherein, the bit line structure includes a conductive layer, and a top surface of the conductive layer is higher than the substrate surface.

Wherein, the bit line structure includes a second isolation layer located on top of the conductive layer.

Wherein, the bit line structure includes a barrier layer, the barrier layer is located between the conductive layer and the bit line contact structure.

Wherein, the bit line contact structure includes a first contact structure and a second contact structure, the first contact structure is located in the first contact hole, and the second contact structure is located above the substrate.

In the semiconductor structure and its formation method provided by the embodiments of the present disclosure, by simultaneously etching the second initial dielectric layer and the first mask stack, it is helpful to avoid the height difference between the first dielectric layer and the second dielectric layer. , which in turn helps to improve the flatness of the subsequently formed bit lines, thereby improving the overall electrical performance of the device.

Other aspects will be apparent after reading and understanding the drawings and detailed description.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. In the drawings, similar reference numbers are used to identify similar elements. The drawings in the following description are of some, but not all, embodiments of the disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

2-7 are step-by-step structural schematic diagrams of a method for forming a semiconductor structure according to embodiments of the present disclosure;

Figure 8 is a flow chart of step S205 of the method for forming a semiconductor structure provided in Figure 1;

FIG. 9 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.

Reference signs:

1: Substrate: 11: Active area: 12: Isolation area;

2: The first mask stack; 21: The first initial dielectric layer; 22: The first dielectric layer; 23: The first sacrificial layer; 24: The first etching layer; 25: The first barrier layer; 26: The first mask pattern;

3: First contact hole;

4: Second initial dielectric layer; 41: Second dielectric layer;

5: bit line contact structure; 51: first contact structure; 52: second contact structure; 53: first initial isolation layer; 54: first isolation layer;

6: bit line structure; 61: barrier layer; 62: conductive layer; 63: second isolation layer; 64: second etching layer; 65: second barrier layer; 66: second mask pattern.

Detailed ways

The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the disclosed embodiments. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of this disclosure. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments can be arbitrarily combined with each other.

The bit line is a key structure in dynamic random access memory, and the flatness of the bit line can directly affect the electrical performance of the subsequently prepared dynamic random access memory.

As shown in Figure 1, an embodiment of the present disclosure provides a method for forming a semiconductor structure. The method includes the following steps:

S101: Provide a substrate 1, which includes an active area 11 and an isolation area 12. The substrate 1 may include, but is not limited to, semiconductor substrates such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, single crystal silicon substrate, polycrystalline silicon substrate, and gallium nitride substrate. In addition, when the substrate 1 is a single crystal substrate or a polycrystalline substrate, it can also be a silicon substrate or a lightly doped silicon substrate. For example, it can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. There are multiple active areas 11 arranged in an array, and the multiple active areas 11 are parallel to each other and arranged in the same direction. Adjacent active areas 11 are isolated from each other by an isolation area 12 . The isolation area 12 may be a shallow trench isolation structure. The isolation area 12 is used to define the shape of the active area 11 . The isolation region can be formed by forming a trench in the substrate and then filling the trench with an isolation material layer. The material of the isolation region may include silicon nitride or silicon oxide. The isolation area can be several active areas isolated on the substrate in an array distribution or other distribution types.

S102: Form the first mask stack 2 on the substrate 1. The thickness of the first mask stack 2 may be greater than the thickness of the substrate 1 , and the first mask stack 2 may optionally include a first initial dielectric layer 21 and a first sacrificial layer 23 stacked in sequence. The thickness of the first initial dielectric layer 21 is optionally smaller than the thickness of the first sacrificial layer 23 . The first sacrificial layer 23 may optionally include but is not limited to conductive materials such as polysilicon, and the first sacrificial layer 23 may optionally be made of doped polysilicon. As shown in FIG. 2 , a first etching layer 24 , a first barrier layer 25 and a first mask pattern 26 may also be sequentially stacked on the first mask stack 2 . The first mask pattern 26 is used for fabricating Pattern of the first contact hole 3 (refer to FIG. 3). 2 is a schematic structural diagram after sequentially stacking the first etching layer 24, the first barrier layer 25 and the first mask pattern 26 on the first mask stack 2. The first etching layer 24 may include spin-coated carbon. layer, an anti-reflective coating located on the spin-coated carbon layer, and the first barrier layer 25 can be selected from one of silicon oxynitride, silicon nitride carbide, silicon nitride, or any combination thereof. The first mask pattern 26 is optionally made of photoresist material.

In some embodiments of the present disclosure, reference 4 also includes a first isolation layer 54 located between the first dielectric layer 22 and the substrate 1 . The thickness of the first isolation layer 54 is smaller than the thickness of the first dielectric layer 22 , and the first isolation layer 54 is made of an insulating material. Before forming the first mask stack 2 on the substrate 1 , a first initial isolation layer 53 is formed on the substrate 1 .

S103: Etch part of the first mask stack 2 and the substrate 1, form a first contact hole 3 in the substrate 1, and expose part of the active area 11 through the first contact hole 3.

Figure 3 is a schematic structural diagram after forming the first contact hole 3. As shown in Figure 3, the formed first contact hole 3 exposes the active area 11. There can be multiple first contact holes 3. Multiple first contacts can be selected. The holes 3 can be optionally distributed in an array, and the bottom of the first contact hole 3 can be optionally circular, elliptical, square, diamond-shaped or any other irregular shape.

In some embodiments of the present disclosure, referring to FIGS. 2 and 3 , a first initial isolation layer 53 is formed on the substrate 1 before the first mask stack 2 is formed on the substrate 1 . The thickness of the first initial isolation layer 53 is less than the thickness of the first mask stack. The first initial isolation layer 53 is made of insulating material. While etching portions of the first mask stack 2 and the substrate 1 , a portion of the first initial isolation layer 53 is etched to form a first isolation layer 54 .

Referring to FIG. 2 , a first etching layer 24 , a first barrier layer 25 and a mask material are formed above the first mask stack, and the mask material is patterned to form a first mask pattern 26 . Exemplarily, using the first mask pattern 26 as a mask, through exposure and development processes, the first initial dielectric layer 21, the first sacrificial layer 23, the first etching layer 24, the first barrier layer 25, the first The initial isolation layer 53 and the substrate 1 are etched until the active area 11 is exposed and the first contact hole 3 is formed, and then the first mask pattern 26, the first barrier layer 25 and the first etching layer 24 are removed. In more detail, one or more layers of spin-coated carbon oxide are first applied using a photolithographic coating process to make the surface flat, then one or more layers of silicon-containing anti-reflective coatings are applied, and finally, one or more layers of silicon-containing anti-reflective coatings are applied. A layer of photoresist is exposed and exposed to form a first mask pattern 26. A mixed gas is used and the first mask pattern 26 is used for shielding to control the first barrier layer 25, the first etching layer 24 and the first sacrificial layer 23. , the first initial isolation layer 53 is etched in sequence. After the photoresist is consumed, the etching is stopped at a height that exposes the active area, and then the first mask pattern 26 is removed by grinding. The first contact hole 3 can be selected used as bit line contact holes.

S104: Form a second initial dielectric layer 4. The second initial dielectric layer 4 fills the first contact hole 3 and covers the top of the mask stack. Figure 4 is a schematic structural diagram after the second initial dielectric layer 4 is formed. As shown in Figure 4, for example, polysilicon is used to fill the first contact hole 3 and cover the first sacrificial layer 23 to form the second initial dielectric layer 4. The second initial dielectric layer The thickness of 4 is greater than the sum of the thicknesses of the first sacrificial layer 23 and the first initial dielectric layer 21, and the top surface of the second initial dielectric layer 4 is flat. The second initial dielectric layer 4 may be made of polysilicon, and the second initial dielectric layer 4 may be made of the same material as the first initial dielectric layer 21 .

S105: Remove part of the second initial dielectric layer 4 and the first mask stack 2 to form the first dielectric layer 22 and the second dielectric layer 41. The tops of the first dielectric layer 22 and the second dielectric layer 41 are flush. As shown in FIG. 5 , the top surfaces of the first dielectric layer 22 and the second dielectric layer 41 are on the same horizontal plane, and the thickness of the first dielectric layer 22 is smaller than the thickness of the first initial dielectric layer 21 . The thickness of the first dielectric layer 22 can be set according to actual conditions, and can be selected to be half the thickness of the first initial dielectric layer 21 . The first dielectric layer 22 is optionally made of polysilicon.

S106: Form a bit line stack on the first dielectric layer 22 and the second dielectric layer 41, and pattern the bit line stack, the first dielectric layer 22 and the second dielectric layer 41 at the same time, refer to Figures 6 and 7 , so that the bit line stack forms the bit line structure 6, and the first dielectric layer 22 and the second dielectric layer 41 form the bit line contact structure 5; wherein the bit line structure 6 is electrically connected to the substrate 1 through the bit line contact structure 5 . The bit line stack optionally includes a stacked semiconductor layer, a metal layer, and an insulating layer. The semiconductor layer is made of, for example, polysilicon, and the insulating layer is made of, for example, oxide. As shown in FIG. 6 , simultaneously patterning the bit line stack, the first dielectric layer 22 and the second dielectric layer 41 includes sequentially stacking a second etching layer 64 and a second barrier layer 65 on the bit line stack. and the second mask pattern 66. FIG. 7 is a schematic structural diagram after sequentially stacking the second etching layer 64, the second barrier layer 65 and the second mask pattern 66 on the bit line stack. Using the second mask pattern 66 as a mask, the second etching layer 64, the second barrier layer 65, the bit line stack, the first dielectric layer 22 and the second dielectric layer 41 are etched through exposure and development processes. , and then remove the second etching layer 64, the second barrier layer 65 and the second mask pattern 66 to obtain the bit line contact structure 5 and the bit line structure 6. The second mask pattern 66 includes a plurality of bit line structure patterns. More specifically, a photolithography coating process is first used to apply spin-coated carbon oxide to make the surface flat, and then, one or more layers of silicon-containing anti-reflective coating are applied. layer, and finally, apply photoresist and expose to form a second mask pattern 66, and use the second mask pattern 66 to shield the bit line stack, the first dielectric layer 22 and the second dielectric layer 41 simultaneously. After etching, after the photoresist is consumed, the etching is stopped at a height that exposes the top surface of the substrate 1, and then the second mask pattern 66 is removed by grinding. Among them, the etched first dielectric layer 22 and the second dielectric layer 41 form the bit line contact structure 5. Since the top surfaces of the first dielectric layer 22 and the second dielectric layer 41 formed in step S205 are flush, the bit line contact structure 5 formed is The top surface of the line structure 6 is flush, and the etched bit line stack forms the bit line structure 6. The bit line structure 6 is arranged above the bit line contact structure 5. Since the top surface of the bit line contact structure 5 is flush, , the flatness of the bit line structure 6 is significantly improved.

As shown in FIG. 7 , there are multiple bit lines, and the multiple bit lines are parallel to each other and arranged in the same direction.

The method for forming a semiconductor structure provided by the embodiment of the present disclosure, with reference to FIG. 4 , etches the second initial dielectric layer 4 and the first mask stack 2 simultaneously, thereby reducing the difficulty of controlling the etching process. During the step, even if there is a height calibration error, an etching device error or an operating error, it will have the same impact on the first initial dielectric layer 21 and the second initial dielectric layer 4 , and the above-mentioned errors will not be converted into the first initial dielectric layer 21 The height difference from the second initial dielectric layer 4 ensures that the subsequent bit lines formed above the first initial dielectric layer 21 have the same height as the bit lines formed above the second initial dielectric layer 4 , thus improving the flatness of the bit lines. This further improves the accuracy of the contact nodes between various components, and ultimately improves the overall electrical performance, qualification rate and service life of the device.

FIG. 8 is a flow chart of step S205 of the method for forming a semiconductor structure provided in FIG. 1 . As shown in Figure 8, in some embodiments of the present disclosure, step S205 includes:

S2051: The first mask stack 2 includes a first initial dielectric layer 21 and a first sacrificial layer 23 stacked in sequence, and the top of the second initial dielectric layer 4 is higher than the top of the first sacrificial layer 23, refer to FIG. 9 . In the embodiment of the present disclosure, the thickness of the stacked first initial dielectric layer 21 is greater than the thickness of the first dielectric layer 22 to be formed (refer to FIG. 5 ), and the thickness difference between the first initial dielectric layer 21 and the first dielectric layer 22 is The setting value can be selected so that in the subsequent etching process, with reference to Figures 4 and 5, part of the first initial dielectric layer 21 and part of the second initial dielectric layer 4 are etched away at the same time, so that the first dielectric layer 22 formed It is flush with the top surface of the second dielectric layer 41 .

S2052: Remove the first sacrificial layer 23, part of the first initial dielectric layer 21 and part of the second initial dielectric layer 4. The first initial dielectric layer 21 and the second initial dielectric layer 4 form the first dielectric layer 22 and the second dielectric layer respectively. 41.

The method of forming a semiconductor structure provided by the embodiment of the present disclosure provides an etching space for the subsequent formation process of the first dielectric layer 22 by setting the first initial dielectric layer 21 with a thickness greater than the first dielectric layer 22. According to the first dielectric layer 22 In order to meet the actual thickness requirements, the first initial dielectric layer 21 and the second initial dielectric layer 4 are etched simultaneously. Even if there is a height calibration error, etching device error or operating error in the etching process steps, the first initial dielectric layer 21 and the second initial dielectric layer 4 will be etched. The dielectric layer 21 and the second initial dielectric layer 4 have the same impact, and the above error will not be converted into a height difference between the first initial dielectric layer 21 and the second initial dielectric layer 4 , thereby ensuring subsequent formation above the first initial dielectric layer 21 The height of the bit line is the same as the bit line formed above the second initial dielectric layer 4, which improves the flatness of the bit line, thereby improving the accuracy of the contact nodes between the various components, and ultimately improving the overall electrical performance and qualification of the device. rate and service life.

In some embodiments of the present disclosure, an etching process is used to remove the first sacrificial layer 23, part of the first initial dielectric layer 21, and part of the second initial dielectric layer 4; The etching rates of the two initial dielectric layers 4 are the same.

The method for forming a semiconductor structure provided by the embodiment of the present disclosure first sets the first sacrificial layer 23, the first initial dielectric layer 21 and the second initial dielectric layer 4 with the same etching rate, and then sets the first sacrificial layer 23, the first initial dielectric layer 23 and the second initial dielectric layer 4. The layer 21 and the second initial dielectric layer 4 are etched at the same time, which helps to further reduce the impact of the etching process error on the flatness of the subsequently formed first dielectric layer 22 and the second dielectric layer 41. During the etching process , even if there is an error in the etching rate, it will have the same impact on the first initial dielectric layer 21 and the second initial dielectric layer 4 , preventing the error in the etching rate from being converted into the first initial dielectric layer 21 and the second initial dielectric layer 4 The height difference ensures that the bit lines subsequently formed above the first initial dielectric layer 21 have the same height as the bit lines formed above the second initial dielectric layer 4, thereby improving the flatness of the bit lines and thereby improving the overall electrical performance of the device. performance and pass rate.

In some embodiments of the present disclosure, a chemical mechanical polishing process is used to remove the first sacrificial layer 23 , part of the first initial dielectric layer 21 and part of the second initial dielectric layer 4 ; , the selection ratios of the first initial dielectric layer 21 and the second initial dielectric layer 4 are the same.

In some embodiments of the present disclosure, step S203 includes: patterning the first mask stack 2 and etching the substrate 1 using the patterned first mask stack 2 as a mask to form a first Contact hole 3. In this embodiment, for example, the first mask pattern 26 is first provided on the first mask stack 2, and then the first mask pattern 26 is used as a mask to pattern the first mask stack 2, and then the first mask pattern 26 is removed. A mask pattern 26 is used to obtain a patterned first mask stack 2 , and then the substrate 1 is etched using the patterned first mask stack 2 as a mask to form a first contact hole 3 .

In some embodiments of the present disclosure, a first isolation layer 54 is also included, located between the first dielectric layer 22 and the substrate 1 . Before forming the first mask stack 2 on the substrate 1 , a first initial isolation layer 53 is formed on the substrate 1 , and a portion of the first mask stack 2 , a portion of the first initial isolation layer 53 and a portion of the substrate are etched. 1. Form the first contact hole 3 in the substrate 1 and form the first isolation layer 54 at the same time. In the embodiment of the present disclosure, the first initial isolation layer 53 is made of, for example, an insulating material, and the first isolation layer 54 is disposed between the second dielectric layer 41 and the substrate 1 so that the second dielectric layer 41 is insulated from the substrate 1 . .

In some embodiments of the present disclosure, the first dielectric layer 22 and the second dielectric layer 41 are made of the same material.

The method for forming a semiconductor structure provided by the embodiment of the present disclosure helps to further ensure the etching of the first dielectric layer 22 and the second dielectric layer 41 by setting the first dielectric layer 22 and the second dielectric layer 41 to be made of the same material. The speed is the same to avoid the height difference between the first dielectric layer 22 and the second dielectric layer 41, thereby ensuring that the height of the bit lines subsequently formed above the first initial dielectric layer 21 is the same as that of the bit lines formed above the second initial dielectric layer 4. Improve the flatness of the bit lines, thereby improving the overall electrical performance and qualification rate of the device.

FIG. 8 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 8, the embodiment of the present disclosure also discloses a semiconductor structure, including:

Substrate 1 includes an active area 11 and an isolation area 12 . The substrate 1 may be, but is not limited to, a silicon substrate 1. In other examples, the substrate 1 may be a semiconductor substrate 1 such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, etc. There are multiple active areas 11 arranged in an array, and the multiple active areas 11 are parallel to each other and arranged in the same direction. Adjacent active regions 11 are isolated from each other by isolation regions 12 , which are, for example, shallow trench isolation structures. The isolation regions 12 are used to define the shape of the active regions 11 . The active region 11 is made of conductive material. For example, the active region 11 is formed by implanting N-type ions or P-type ions. The isolation region 12 is made of an insulating material.

The substrate 1 includes a first contact hole 3 , and the bottom of the first contact hole 3 exposes the active area 11 . The first contact hole 3 is used as a bit line contact hole, for example. The bottom of the first contact hole 3 is, for example, circular or elliptical. There are multiple first contact holes 3 , and the plurality of first contact holes 3 are, for example, distributed in an array.

The bit line contact structure 5 , part of the bit line contact structure 5 is located in the first contact hole 3 , and the bottom of the bit line contact structure 5 is connected to the active area 11 . The top surface of the bit line contact structure 5 is higher than the top surface of the substrate 1 . There are multiple bit line contact structures 5 , and the top surfaces of the multiple bit line contact structures 5 are flush.

The bit line structure 6 is electrically connected to the substrate 1 through the bit line contact structure 5 . The bit line structure 6 includes a conductive layer 62 , the top surface of the conductive layer 62 is higher than the surface of the substrate 1 . The conductive layer 62 is made of metal material, and has a single-layer structure or a multi-layer structure, for example. The material of the conductive layer 62 includes but is not limited to W. The conductive layer 62 includes, for example, TiN or WN. The bit line structure 6 includes a second isolation layer 63 located on top of the conductive layer 62 . The bit line structure 6 includes a barrier layer 61 made of conductive material, and the barrier layer 61 is located between the conductive layer 62 and the bit line contact structure 5 . The thickness of the conductive layer 62 is, for example, smaller than the thickness of the second isolation layer 63 .

The semiconductor structure provided by the embodiments of the present disclosure can be manufactured by any of the above-mentioned semiconductor structure forming methods. In the semiconductor structure provided by the embodiment of the present disclosure, multiple bit line contact structures 5 with flush top surfaces are provided so that the heights of the bit lines subsequently formed above the bit line contact structures 5 are the same, thereby improving the flatness of the bit lines, thereby improving the It improves the accuracy of the contact nodes between various components, and ultimately improves the overall electrical performance, qualification rate and service life of the device.

In some embodiments of the present disclosure, referring to FIG. 7 , the bit line contact structure 5 includes a first contact structure 51 and a second contact structure 52 . The first contact structure 51 is located in the first contact hole 3 (refer to FIG. 3 ). Two contact structures 52 are located above the substrate 1 . The top surface of the first contact structure 51 and the top surface of the second contact structure 52 are located on the same horizontal plane.

Referring to FIG. 7 , the semiconductor structure provided by the embodiment of the present disclosure is provided with a first contact structure 51 and a second contact structure 52 whose top surfaces are located on the same horizontal plane, so that the bit lines subsequently formed above the first contact structure 51 are in line with the first contact structure 51 and the second contact structure 52 . The heights of the bit lines formed above the two contact structures 52 are the same, which improves the flatness of the bit lines, thereby improving the accuracy of the contact nodes between various components, and ultimately improving the overall electrical performance, qualification rate and service life of the device.

Each embodiment or implementation mode in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between various embodiments can be referred to each other.

In the description of this specification, reference to the description of the terms "embodiments," "exemplary embodiments," "some embodiments," "illustrative embodiments," "examples," etc. is intended to be described in connection with the embodiments or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description. It does not indicate or imply that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on the present disclosure.

It will be understood that the terms "first", "second", etc. used in this disclosure may be used to describe various structures in this disclosure, but these structures are not limited by these terms. These terms are used only to distinguish one structure from another.

In one or more of the drawings, identical elements are designated with similar reference numbers. For the sake of clarity, various parts of the figures are not drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure are described below, such as device structures, materials, dimensions, processing processes and techniques, to provide a clearer understanding of the present disclosure. However, as one skilled in the art will appreciate, the present disclosure may be practiced without these specific details.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that it can still be used Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent substitutions are made to some or all of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present disclosure.

Industrial applicability

In a semiconductor structure and its formation method provided by embodiments of the present disclosure, by simultaneously etching the second initial dielectric layer and the first mask stack, it is helpful to avoid the existence of the first dielectric layer and the second dielectric layer. The height difference helps to improve the flatness of the subsequently formed bit lines, thereby improving the overall electrical performance of the device.

Claims

A method of forming a semiconductor structure, the method comprising:

providing a substrate, the substrate including an active region and an isolation region;

forming a first mask stack on the substrate;

Etching a portion of the first mask stack and the substrate, forming a first contact hole in the substrate, the first contact hole exposing a portion of the active region;

Forming a second initial dielectric layer that fills the first contact hole and covers the top of the mask stack;

Remove part of the second initial dielectric layer and the first mask stack to form a first dielectric layer and a second dielectric layer, and the tops of the first dielectric layer and the second dielectric layer are flush;

A bit line stack is formed on the first dielectric layer and the second dielectric layer, and the bit line stack, the first dielectric layer and the second dielectric layer are patterned so that the The bit line stack forms a bit line structure, and the first dielectric layer and the second dielectric layer form a bit line contact structure; wherein the bit line structure realizes electrical connection with the substrate through the bit line contact structure. connect.
The method of forming a semiconductor structure according to claim 1, wherein removing part of the second initial dielectric layer and the first mask stack to form the first dielectric layer and the second dielectric layer includes:

The first mask stack includes a first initial dielectric layer and a first sacrificial layer stacked in sequence, and the top of the second initial dielectric layer is higher than the top of the first sacrificial layer;

Remove the first sacrificial layer, part of the first initial dielectric layer and part of the second initial dielectric layer, and the first initial dielectric layer and the second initial dielectric layer form the first dielectric layer and the second initial dielectric layer respectively. the second dielectric layer.
The method of forming a semiconductor structure according to claim 2, wherein an etching process is used to remove the first sacrificial layer, part of the first initial dielectric layer and part of the second initial dielectric layer; the first sacrificial layer The etching rates of the first initial dielectric layer and the second initial dielectric layer are the same.
The method of forming a semiconductor structure according to claim 2, wherein a chemical mechanical polishing process is used to remove the first sacrificial layer, part of the first initial dielectric layer and part of the second initial dielectric layer; In the grinding process, the selection ratio of the grinding fluid to the first sacrificial layer, the first initial dielectric layer and the second initial dielectric layer is the same.
The method of forming a semiconductor structure according to claim 1, wherein said etching portions of said first mask stack and said substrate to form a first contact hole in said substrate includes:

The first mask stack is patterned, and the substrate is etched using the patterned first mask stack as a mask to form the first contact hole.
The method of forming a semiconductor structure according to claim 1, further comprising a first isolation layer located between the first dielectric layer and the substrate.
The method of forming a semiconductor structure according to claim 6, wherein before forming the first mask stack on the substrate, a first initial isolation layer is formed on the substrate, and a portion of the first isolation layer is etched. A mask stack, a portion of the first initial isolation layer and a portion of the substrate in which a first contact hole is formed and a first isolation layer is formed.
The method of forming a semiconductor structure according to claim 1, wherein the first dielectric layer and the second dielectric layer are made of the same material.
A semiconductor structure including:

A substrate including an active region and an isolation region;

The substrate includes a first contact hole, and the bottom of the first contact hole exposes the active area;

A bit line contact structure, part of the bit line contact structure is located in the first contact hole, and the bottom of the bit line contact structure is connected to the active area;

A bit line structure is electrically connected to the substrate through the bit line contact structure.
The semiconductor structure of claim 9, wherein

The bit line structure includes a conductive layer, and a top surface of the conductive layer is higher than the substrate surface.
The semiconductor structure of claim 10, wherein

The bit line structure includes a second isolation layer on top of the conductive layer.
The semiconductor structure of claim 10, wherein

The bit line structure includes a barrier layer between the conductive layer and the bit line contact structure.
The semiconductor structure of claim 9, wherein

The bit line contact structure includes a first contact structure located in the first contact hole and a second contact structure located above the substrate.