CN115664359A

CN115664359A - Topological circuit combining operational amplifier and comparator

Info

Publication number: CN115664359A
Application number: CN202211097139.3A
Authority: CN
Inventors: 耿靖斌; 姜俊伟; 李志翔; 耿娟娟
Original assignee: Beijing Weike Nengchuang Science & Technology Co ltd
Current assignee: Beijing Weike Nengchuang Science & Technology Co ltd
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2023-01-31

Abstract

The application provides a topological circuit combining an operational amplifier and a comparator, wherein the circuit comprises an active load, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a driving circuit; when the first differential input voltage of the differential input circuit is smaller than the second differential input voltage, the four MOS tubes of the active load are in a first connection mode to realize the function of the operational amplifier; when the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS tubes of the active load are in the second connection mode to realize the function of the comparator. The operational amplifier and the comparator circuit structure are shared on the circuit topology, and a related mechanism is formed on the mechanism of generating forward voltage drop and reverse turn-off voltage, so that the advantage of keeping the forward voltage drop as low as possible is realized, and the reverse turn-off point is not too far away from the origin, so that the aims of reducing reverse current and avoiding oscillation during the reverse turn-off period are fulfilled.

Description

Topological circuit combining operational amplifier and comparator

Technical Field

The present application relates to the field of circuit technologies, and in particular, to a topology circuit combining an operational amplifier and a comparator.

Background

In the field of controller chips related to an ideal diode and a load switch, in order to obtain low voltage drop and rapid turn-off characteristics, an operational amplifier and a comparator are often involved, the operational amplifier obtains low conduction voltage drop through negative feedback action to reduce power loss on a path, the comparator compares the voltage drops generated at two ends of the path, certain external devices are quickly turned off when certain voltage difference conditions are met, and reverse current is prevented from flowing. For example, in the field of ideal diode controllers, as shown in fig. 1, an operational amplifier forms a closed loop with an external power NMOS, and obtains a low on-state voltage drop Vos _ ea under the action of negative feedback, for example: 30mV, because the voltage drop from the input source end to the output out end is very low, when the external power NMOS has large current, the power loss on the path is effectively reduced; the comparator compares the voltage drop from the input source terminal to the output out terminal, and when a certain voltage difference Vos _ com is satisfied, for example: 30mV, the comparator will rapidly turn off the external power NMOS, preventing reverse current from flowing.

At present, the forward conduction voltage drop Vos _ ea is obtained by negative feedback of an operational amplifier, the monitoring turn-off voltage Vos _ com is realized by a comparator, and in order to realize as low as possible conduction voltage drop, the Vos _ ea is often reduced, but the reduction of the Vos _ ea is limited by mismatch (mismatch) factors of manufacturing processes, so that the reduction of the central expected value of the Vos _ ea can cause that the voltage drop value is too low and negative feedback fails under a negative feedback condition (combined with mismatch introduced by manufacturing); the monitoring voltage Vos _ com of the comparator is also affected by mismatch caused by manufacturing, and from the distribution point of view, there is a possibility that the forward on-voltage drop distribution function Vos _ ea (X) and the reverse off-voltage distribution function Vos _ com (Y) have an overlapping region, once the overlapping occurs, it means that the forward on-voltage drop of some chips is not higher than the reverse off-point, and a technical problem of oscillation is caused. Therefore, how to implement an operational amplifier and a comparator to avoid oscillation during use is a non-trivial technical problem.

Disclosure of Invention

In view of the above, the present application provides a topology circuit combining an operational amplifier and a comparator, which is a related mechanism in terms of generating a forward voltage drop and a reverse turn-off voltage mechanism by sharing a circuit structure of the operational amplifier and the comparator in a circuit topology, so as to achieve the advantages of keeping the forward voltage drop as low as possible, and preventing a reverse turn-off point from being too far away from an origin, so as to achieve the purposes of reducing a reverse current and avoiding oscillation during a reverse turn-off period.

The embodiment of the application provides a topological circuit combining an operational amplifier and a comparator, wherein the topological circuit comprises an active load, a comparator and a comparator, wherein the active load comprises four MOS (metal oxide semiconductor) tubes, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a driving circuit; the active load comprises four MOS tubes, and each single-ended conversion circuit comprises two MOS tubes; wherein, the first and the second end of the pipe are connected with each other,

the first end of the first single-ended conversion circuit is electrically connected with the first end of the active load, the second end of the first single-ended conversion circuit is electrically connected with the second end of the active load, the third end of the first single-ended conversion circuit is electrically connected with the third end of the second single-ended conversion circuit, and the fourth end of the first single-ended conversion circuit is electrically connected with the fourth end of the second single-ended conversion circuit and the second end of the drive circuit;

the first end of the second single-ended conversion circuit is electrically connected with the third end of the active load, the second end of the second single-ended conversion circuit is electrically connected with the fourth end of the active load, and the fifth end of the second single-ended conversion circuit is electrically connected with the first end of the driving circuit;

the fifth end of the active load is electrically connected with the first end of the differential current conversion circuit, the sixth end of the active load is electrically connected with the second end of the differential current conversion circuit, the third end of the differential current conversion circuit is electrically connected with the first end of the differential input circuit, the fourth end of the differential current conversion circuit is electrically connected with the second end of the differential input circuit, and the third end of the differential input circuit is electrically connected with the second end of the driving circuit; the power supply is electrically connected with the seventh end of the active load;

when the first differential input voltage of the differential input circuit is smaller than the second differential input voltage, the four MOS tubes of the active load are in a first connection mode to realize the function of an operational amplifier;

when the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS tubes of the active load are in a second connection mode to realize the function of the comparator.

In a possible implementation manner, the active load comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; wherein, the first and the second end of the pipe are connected with each other,

a source electrode of a first MOS tube is electrically connected with a source electrode of a second MOS tube, and a grid electrode of the first MOS tube is electrically connected with a drain electrode of the second MOS tube and a drain electrode of the first MOS tube, wherein the source electrode of the first MOS tube is used as a first end of the active load, the grid electrode of the first MOS tube is used as a second end of the active load, and the drain electrode of the first MOS tube is used as a fifth end of the active load;

a source electrode of the third MOS transistor is electrically connected with a source electrode of a fourth MOS transistor, and a drain electrode of the third MOS transistor is electrically connected with a drain electrode of the fourth MOS transistor and a gate electrode of the fourth MOS transistor, wherein the source electrode of the fourth MOS transistor serves as a third end of the active load, the gate electrode of the fourth MOS transistor serves as a fourth end of the active load, and the drain electrode of the third MOS transistor serves as a sixth end of the active load;

the grid electrode of the second MOS tube is electrically connected with the drain electrode of the third MOS tube, and the source electrode of the second MOS tube is electrically connected with the grid electrode of the third MOS tube.

In a possible embodiment, the first connection mode is:

the first MOS tube and the second MOS tube are connected in parallel to obtain a first target MOS tube, the third MOS tube and the fourth MOS tube are connected in parallel to obtain a second target MOS tube, the grid electrode of the first target MOS tube is respectively and electrically connected with the grid electrode of the second target MOS tube and the drain electrode of the first target MOS tube, and the second target MOS tube is electrically connected with the grid electrode of the third MOS tube.

In a possible embodiment, the second connection mode is:

the grid electrode of the second MOS tube is electrically connected with the grid electrode of the fourth MOS tube, the drain electrode of the fourth MOS tube is electrically connected with the grid electrode of the fourth MOS tube, and the first MOS tube and the third MOS tube are cut off.

In a possible implementation, the first single-ended conversion circuit includes two MOS transistors; wherein the content of the first and second substances,

the drain electrode of the fifth MOS transistor is electrically connected to the drain electrode and the gate electrode of the sixth MOS transistor, wherein the source electrode of the fifth MOS transistor is used as the first end of the first single-ended conversion circuit, the gate electrode of the fifth MOS transistor is used as the second end of the first single-ended conversion circuit, the gate electrode of the sixth MOS transistor is used as the third end of the first single-ended conversion circuit, and the source electrode of the sixth MOS transistor is used as the fourth end of the first single-ended conversion circuit.

In one possible implementation, the second single-ended conversion circuit includes two MOS transistors; wherein the content of the first and second substances,

a drain of the seventh MOS transistor is electrically connected to a drain of the eighth MOS transistor, wherein a source of the seventh MOS transistor serves as a first end of the second single-ended conversion circuit, a gate of the seventh MOS transistor serves as a second end of the second single-ended conversion circuit, a gate of the eighth MOS transistor serves as a third end of the second single-ended conversion circuit, a source of the eighth MOS transistor serves as a fourth end of the second single-ended conversion circuit, and a drain of the eighth MOS transistor serves as a fifth end of the second single-ended conversion circuit.

In one possible implementation, the differential current conversion circuit comprises four MOS transistors and a first bias current source; wherein the content of the first and second substances,

a grid electrode of the ninth MOS tube is electrically connected with a grid electrode of the tenth MOS tube, a drain electrode of the tenth MOS tube and a first bias current source, a source electrode of the ninth MOS tube is electrically connected with a source electrode of the tenth MOS tube, a grid electrode of the eleventh MOS tube is electrically connected with a grid electrode of the twelfth MOS tube, a drain electrode of the eleventh MOS tube and the first bias current source, and a source electrode of the eleventh MOS tube is electrically connected with a source electrode of the twelfth MOS tube;

the drain of the tenth MOS transistor is used as the first end of the differential current conversion circuit, the drain of the twelfth MOS transistor is used as the second end of the differential current conversion circuit, the source of the tenth MOS transistor is used as the third end of the differential current conversion circuit, and the source of the twelfth MOS transistor is used as the fourth end of the differential current conversion circuit.

In one possible implementation, the differential input circuit comprises two MOS transistors; wherein, the first and the second end of the pipe are connected with each other,

the drain electrode of the thirteenth MOS tube is electrically connected with the drain electrode of the fourteenth MOS tube and the grid electrode of the fourteenth MOS tube, wherein the source electrode of the thirteenth MOS tube is used as the first end of the differential input circuit, the source electrode of the fourteenth MOS tube is used as the second end of the differential input circuit, and the grid electrode of the fourteenth MOS tube is used as the third end of the differential input circuit.

In a possible implementation manner, the driving circuit comprises two MOS tubes and a second bias current source; wherein the content of the first and second substances,

the drain electrode of the fifteenth MOS transistor is electrically connected to the second bias current source and the gate electrode of the sixteenth MOS transistor, and the source electrode of the sixteenth MOS transistor is electrically connected to the source electrode of the fifteenth MOS transistor, wherein the gate electrode of the fifteenth MOS transistor serves as the first end of the driving circuit, and the source electrode of the fifteenth MOS transistor serves as the second end of the driving circuit.

In a possible implementation, the ratio between the width-to-length ratio of the first MOS transistor, the width-to-length ratio of the second MOS transistor, the width-to-length ratio of the third MOS transistor, and the width-to-length ratio of the fourth MOS transistor is 3.5:2.5:2:3.

the topological circuit combining the operational amplifier and the comparator comprises an active load, a comparator and a comparator, wherein the active load comprises four MOS tubes, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a drive circuit; the active load comprises four MOS tubes, and each single-ended conversion circuit comprises two MOS tubes; the first end of the first single-ended conversion circuit is electrically connected with the first end of the active load, the second end of the first single-ended conversion circuit is electrically connected with the second end of the active load, the third end of the first single-ended conversion circuit is electrically connected with the third end of the second single-ended conversion circuit, and the fourth end of the first single-ended conversion circuit is electrically connected with the fourth end of the second single-ended conversion circuit and the second end of the drive circuit; the first end of the second single-ended conversion circuit is electrically connected with the third end of the active load, the second end of the second single-ended conversion circuit is electrically connected with the fourth end of the active load, and the fifth end of the second single-ended conversion circuit is electrically connected with the first end of the driving circuit; the fifth end of the active load is electrically connected with the first end of the differential current conversion circuit, the sixth end of the active load is electrically connected with the second end of the differential current conversion circuit, the third end of the differential current conversion circuit is electrically connected with the first end of the differential input circuit, the fourth end of the differential current conversion circuit is electrically connected with the second end of the differential input circuit, and the third end of the differential input circuit is electrically connected with the second end of the driving circuit; the power supply is electrically connected with the seventh end of the active load; when the first differential input voltage of the differential input circuit is smaller than the second differential input voltage, the four MOS tubes of the active load are in a first connection mode to realize the function of an operational amplifier; when the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS tubes of the active load are in a second connection mode to realize the function of the comparator. The operational amplifier and the comparator circuit structure are shared on the circuit topology, and a related mechanism is formed on the mechanism of generating forward voltage drop and reverse turn-off voltage, so that the advantage of keeping the forward voltage drop as low as possible is realized, and the reverse turn-off point is not too far away from the origin, so that the aims of reducing reverse current and avoiding oscillation during the reverse turn-off period are fulfilled.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 is a circuit diagram of the operational amplifier and the comparator for controlling the external power NMOS;

fig. 2 is a schematic structural diagram of a combined topology circuit of an operational amplifier and a comparator according to an embodiment of the present disclosure;

fig. 3 is a second schematic diagram of a topology circuit combining an operational amplifier and a comparator according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an operational amplifier equivalent to a topological circuit combining an operational amplifier and a comparator according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a topology circuit equivalent to a comparator of a combination of an operational amplifier and a comparator according to an embodiment of the present disclosure;

FIG. 6 is a comparison of an operational amplifier and comparator combination and an independent design of the operational amplifier and comparator according to an embodiment of the present application.

An icon: 200-topological circuit of combination of operational amplifier and comparator; 210 — an active load; 211-a first MOS transistor; 212-a second MOS tube; 213-third MOS tube; 214-fourth MOS transistor; 220-a first single-ended conversion circuit; 221-a fifth MOS tube; 222-a sixth MOS transistor; 230-a second single-ended conversion circuit; 231-a seventh MOS transistor; 232-eighth MOS tube; 240-differential current conversion circuit; 241-ninth MOS transistor; 242-tenth MOS transistor; 243-eleventh MOS transistor; 244-twelfth MOS transistor; 245-a first bias current source; 250-a differential input circuit; 251-thirteenth MOS transistor; 252-a fourteenth MOS tube; 260-a driver circuit; 261-a fifteenth MOS tube; 262-sixteenth MOS tube; 263-second bias current source.

Detailed Description

To make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustrative and descriptive purposes only and are not used to limit the scope of protection of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and that steps without logical context may be reversed in order or performed concurrently. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.

In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

To enable those skilled in the art to utilize the present disclosure, the following embodiments are presented in conjunction with a specific application scenario "circuit that fuses an operational amplifier and a comparator", and it will be apparent to those skilled in the art that the general principles defined herein may be applied to other embodiments and application scenarios without departing from the spirit and scope of the present disclosure.

The following circuit in the embodiment of the present application may be applied to any scenario that an operational amplifier and a comparator need to be fused, and the embodiment of the present application does not limit a specific application scenario, and any scheme that uses a topology circuit that combines an operational amplifier and a comparator provided in the embodiment of the present application is within the protection scope of the present application.

First, an application scenario to which the present application is applicable will be described. The application can be applied to the field of circuits.

Research shows that, at present, the forward conduction voltage drop Vos _ ea is obtained by negative feedback of an operational amplifier, the monitoring turn-off voltage Vos _ com is realized by a comparator, and in order to realize as low conduction voltage drop as possible, the Vos _ ea is often reduced, but the reduction of the Vos _ ea is limited by mismatch (mismatch) factors of manufacturing processes, so that the reduction of the central expected value of the Vos _ ea can cause that the voltage drop value is too low and negative feedback fails under a negative feedback condition (combined with mismatch introduced by manufacturing); the monitoring voltage Vos _ com of the comparator is also affected by mismatch caused by manufacturing, and from the distribution point of view, there is a possibility that the forward on-voltage drop distribution function Vos _ ea (X) and the reverse off-voltage distribution function Vos _ com (Y) have an overlapping region, once the overlapping occurs, it means that the forward on-voltage drop of some chips is not higher than the reverse off-point, and a technical problem of oscillation is caused. Therefore, how to implement an operational amplifier and a comparator to avoid oscillation during use is a non-trivial technical problem.

There are two major contradictions in the prior art, one is: reducing the forward voltage drop Vos _ ea (X) is contradictory to the mismatch of the manufacturing process, so that the designer cannot reduce the forward voltage drop at once; secondly, the following steps: the reverse turn-off voltage Vos _ com (Y) is to be far from the distribution of the forward voltage drop Vos _ ea (X) to avoid self-oscillation, so that the designer cannot get the reverse turn-off voltage close to the forward voltage drop at once. Therefore, in order to reduce the forward voltage drop Vos _ ea (X) and keep the controller stable, a common technique in the industry is to make the two distributions symmetrically distributed around the central 0 axis, but although the design strategy is safe enough, there is a defect that the reverse turn-off point Vos _ com (Y) is arranged on the left side of the 0 axis, which means that the turn-off must be started only when out is significantly larger than a certain value of source, and inevitably causes a reverse current problem, so that a circuit structure such as a differential structure exists in the design to assist in reducing the reverse current at the turn-off moment. As can be seen from the above analysis, the root cause of the occurrence of reverse current is that, in order to keep the voltage drop low and the controller stable, the off detection voltage must be far from the region of the forward voltage drop, it is very easy to enter the left side of the 0 axis, and in conjunction with the mismatch of the comparator, the Vos _ com (Y) distribution center μ os _ com is arranged much to the left side of the 0 axis, and the occurrence of reverse current is almost unavoidable in consideration of the transmission delay of the comparator.

Based on this, the embodiment of the present application provides a topology circuit combining an operational amplifier and a comparator, which is a related mechanism in terms of generating a forward voltage drop and a reverse turn-off voltage mechanism by sharing a circuit structure of the operational amplifier and the comparator in a circuit topology, so that the advantage of keeping the forward voltage drop as low as possible is achieved, and the reverse turn-off point is not too far away from the origin, so as to achieve the purpose of reducing reverse current and avoiding oscillation during reverse turn-off.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a topology circuit combining an operational amplifier and a comparator according to an embodiment of the present disclosure. As shown in fig. 2, the operational amplifier and comparator combined topology circuit 200 provided by the embodiment of the present application includes an active load 210 including four MOS transistors, two single-ended conversion circuits each including 2 MOS transistors, a differential current conversion circuit 240, a differential input circuit 250, and a driving circuit 260.

Specifically, a first end of the first single-ended conversion circuit 220 is electrically connected to a first end of the active load 210, a second end of the first single-ended conversion circuit 220 is electrically connected to a second end of the active load 210, a third end of the first single-ended conversion circuit 220 is electrically connected to a third end of the second single-ended conversion circuit 230, and a fourth end of the first single-ended conversion circuit 220 is electrically connected to a fourth end of the second single-ended conversion circuit 230 and a second end of the driving circuit 260.

Illustratively, the first single-ended conversion circuit 220 is used to convert double-ended to single-ended.

For example, the first single-ended conversion circuit 220 includes 2 MOS transistors.

For example, the active load 210 is composed of four MOS transistors, and due to the existence of the forward voltage drop of the operational amplifier and the reverse turn-off voltage drop of the comparator, the active load 210 needs to be specially designed, and the width-to-length ratios of the four MOS transistors need to be designed.

In an example, a first terminal of the first single-ended conversion circuit 220 is electrically connected to a first terminal of the active load 210, a second terminal of the first single-ended conversion circuit 220 is electrically connected to a second terminal of the active load 210, a third terminal of the first single-ended conversion circuit 220 is electrically connected to a third terminal of the second single-ended conversion circuit 230, and a fourth terminal of the first single-ended conversion circuit 220 is electrically connected to a fourth terminal of the second single-ended conversion circuit 230 and a second terminal of the driving circuit 260.

Specifically, a first terminal of the second single-ended conversion circuit 230 is electrically connected to the third terminal of the active load 210, a second terminal of the second single-ended conversion circuit 230 is electrically connected to the fourth terminal of the active load 210, and a fifth terminal of the second single-ended conversion circuit 230 is electrically connected to the first terminal of the driving circuit 260.

Illustratively, the second single-ended conversion circuit 230 is used for double-ended to single-ended conversion.

Illustratively, the second single-ended conversion circuit 230 is formed by two MOS transistors.

For example, the first terminal of the second single-ended conversion circuit 230 is electrically connected to the third terminal of the active load 210, the second terminal of the second single-ended conversion circuit 230 is electrically connected to the fourth terminal of the active load 210, and the fifth terminal of the second single-ended conversion circuit 230 is electrically connected to the first terminal of the driving circuit 260.

Specifically, the fifth terminal of the active load 210 is electrically connected to the first terminal of the differential current converting circuit 240, the sixth terminal of the active load 210 is electrically connected to the second terminal of the differential current converting circuit 240, the third terminal of the differential current converting circuit 240 is electrically connected to the first terminal of the differential input circuit 250, the fourth terminal of the differential current converting circuit 240 is electrically connected to the second terminal of the differential input circuit 250, and the third terminal of the differential input circuit 250 is electrically connected to the second terminal of the driving circuit 260; the power supply is electrically connected to the seventh terminal of the active load 210.

Here, the power supply may be 3V, 5V, etc., and the type of the power supply is not limited herein.

Illustratively, the differential current converting circuit 240 is configured to convert the tail current input by the differential input circuit 250 into a differential current.

Illustratively, the differential input circuit 250 is used for differential input, such differential input using PMOS allows the common mode level to be 0, and the differential input is symmetrical, and the mismatch caused by the differential input is very low if the width-to-length ratio is sufficient.

For example, the fifth terminal of the active load 210 is electrically connected to the first terminal of the differential current converting circuit 240, the sixth terminal of the active load 210 is electrically connected to the second terminal of the differential current converting circuit 240, the third terminal of the differential current converting circuit 240 is electrically connected to the first terminal of the differential input circuit 250, the fourth terminal of the differential current converting circuit 240 is electrically connected to the second terminal of the differential input circuit 250, and the third terminal of the differential input circuit 250 is electrically connected to the second terminal of the driving circuit 260; the power supply is electrically connected to the seventh terminal of the active load 210.

Specifically, when the first differential input voltage of the differential input circuit 250 is smaller than the second differential input voltage, the four MOS transistors of the active load 210 are in the first connection mode to implement the function of an operational amplifier; when the first differential input voltage of the differential input circuit 250 is greater than the second differential input voltage, the four MOS transistors of the active load 210 are in the second connection mode to implement the function of the comparator.

The working principle of the circuit is as follows:

when the first differential input voltage of the differential input circuit 250 is smaller than the second differential input voltage in the topology circuit combining the operational amplifier and the comparator, the current flowing from the first end of the differential current converting circuit 240 through the fifth end of the active load 210 is higher than the current flowing from the second end of the differential current converting circuit 240 through the sixth end of the active load 210, and the four MOS transistors inside the active load 210 are in the first connection mode to make the topology circuit equivalent to the operational amplifier; when the first differential input voltage of the differential input circuit 250 is greater than the second differential input voltage, and the current flowing from the first terminal of the differential current converting circuit 240 through the fifth terminal of the active load 210 is lower than the current flowing from the second terminal of the differential current converting circuit 240 through the sixth terminal of the active load 210, the four MOS transistors inside the active load 210 are in the second connection mode to make the topology circuit equivalent to a comparator, so as to realize that the forward voltage drop generated by the operational amplifier and the reverse turn-off voltage generated by the comparator are in the same mechanism, and even if there is an overlapping area between the two, there is no oscillation, thus not only maintaining the advantage of the forward voltage drop as low as possible, but also making the reverse turn-off point not far away from the 0 axis too much, so as to achieve the purpose of reducing the reverse current and avoiding oscillation during the reverse turn-off.

Further, referring to fig. 3, fig. 3 is a second schematic structural diagram of a topology circuit combining an operational amplifier and a comparator according to an embodiment of the present application. As shown in fig. 3, the active load 210 includes a first MOS transistor 211, a second MOS transistor 212, a third MOS transistor 213 and a fourth MOS transistor 214, the first single-ended converter circuit 220 includes a fifth MOS transistor 221 and a sixth MOS transistor 222, the second single-ended converter circuit 230 includes a seventh MOS transistor 231 and an eighth MOS transistor 232, the differential current converter circuit 240 includes a ninth MOS transistor 241, a tenth MOS transistor 242, an eleventh MOS transistor 243, a twelfth MOS transistor 244 and a first bias current source 245, the differential input circuit 250 includes a thirteenth MOS transistor 251 and a fourteenth MOS transistor 252, and the driving circuit 260 includes a fifteenth MOS transistor 261, a sixteenth MOS transistor 262 and a second bias current source 263.

Specifically, a source of a first MOS transistor 211 is electrically connected to a source of a second MOS transistor 212, a gate of the first MOS transistor 211 is electrically connected to a drain of the second MOS transistor 212 and a drain of the first MOS transistor 211, wherein the source of the first MOS transistor 211 is used as a first end of the active load 210, the gate of the first MOS transistor 211 is used as a second end of the active load 210, and the drain of the first MOS transistor 211 is used as a fifth end of the active load 210; a source electrode of the third MOS transistor 213 is electrically connected to a source electrode of a fourth MOS transistor 214, and a drain electrode of the third MOS transistor 213 is electrically connected to a drain electrode of the fourth MOS transistor 214 and a gate electrode of the fourth MOS transistor 214, wherein the source electrode of the fourth MOS transistor 214 serves as a third terminal of the active load 210, the gate electrode of the fourth MOS transistor 214 serves as a fourth terminal of the active load 210, and the drain electrode of the third MOS transistor 213 serves as a sixth terminal of the active load 210; the gate of the second MOS transistor 212 is electrically connected to the drain of the third MOS transistor 213, and the source of the second MOS transistor 212 is electrically connected to the gate of the third MOS transistor 213.

Illustratively, the gate of the second MOS transistor 212 is electrically connected to the drain of the third MOS transistor 213, so that the gate of the second MOS transistor 212 and the drain of the third MOS transistor 213 have the same current, and the gate of the third MOS transistor 213 is electrically connected to the drain of the second MOS transistor 212, so that the gate of the third MOS transistor 213 and the drain of the second MOS transistor 212 have the same current.

For example, the type of the MOS transistor may be an NPN type, and the type of the MOS transistor is not limited herein.

Specifically, a drain of the fifth MOS 221 is electrically connected to a drain and a gate of the sixth MOS 222, wherein a source of the fifth MOS 221 is used as the first end of the first single-ended conversion circuit 220, a gate of the fifth MOS 221 is used as the second end of the first single-ended conversion circuit 220, a gate of the sixth MOS 222 is used as the third end of the first single-ended conversion circuit 220, and a source of the sixth MOS 222 is used as the fourth end of the first single-ended conversion circuit 220.

Illustratively, the drain of the fifth MOS 221 is electrically connected to the drain and the gate of the sixth MOS 222, wherein the source of the fifth MOS 221 is electrically connected to the source of the first MOS 211, the gate of the fifth MOS 221 is electrically connected to the gate of the first MOS 211, the gate of the sixth MOS 222 is electrically connected to the gate of the eighth MOS 232, and the source of the sixth MOS 222 is electrically connected to the source of the eighth MOS 232.

Specifically, a drain of the seventh MOS transistor 231 is electrically connected to a drain of the eighth MOS transistor 232, wherein a source of the seventh MOS transistor 231 is used as the first end of the second single-ended conversion circuit 230, a gate of the seventh MOS transistor 231 is used as the second end of the second single-ended conversion circuit 230, a gate of the eighth MOS transistor 232 is used as the third end of the second single-ended conversion circuit 230, a source of the eighth MOS transistor 232 is used as the fourth end of the second single-ended conversion circuit 230, and a drain of the eighth MOS transistor 232 is used as the fifth end of the second single-ended conversion circuit 230.

In an example, the drain of the seventh MOS transistor 231 is electrically connected to the drain of the eighth MOS transistor 232, the source of the seventh MOS transistor 231 is electrically connected to the source of the fourth MOS transistor 214, the gate of the seventh MOS transistor 231 is electrically connected to the gate of the fourth MOS transistor 214, the gate of the eighth MOS transistor 232 is electrically connected to the gate of the sixth MOS transistor 222, and the drain of the eighth MOS transistor 232 is electrically connected to the gate of the fifteenth MOS transistor 261.

Specifically, the gate of the ninth MOS transistor 241 is electrically connected to the gate of the tenth MOS transistor 242, the drain of the tenth MOS transistor 242 and the first bias current source 245, the source of the ninth MOS transistor 241 is electrically connected to the source of the tenth MOS transistor 242, the gate of the eleventh MOS transistor 243 is electrically connected to the gate of the twelfth MOS transistor 244, the drain of the eleventh MOS transistor 243 and the first bias current source 245, and the source of the eleventh MOS transistor 243 is electrically connected to the source of the twelfth MOS transistor 244; the drain of the tenth MOS 242 is used as the first end of the differential current converting circuit 240, the drain of the twelfth MOS 244 is used as the second end of the differential current converting circuit 240, the source of the tenth MOS 242 is used as the third end of the differential current converting circuit 240, and the source of the twelfth MOS 244 is used as the fourth end of the differential current converting circuit 240.

Illustratively, the gate of the ninth MOS transistor 241 is electrically connected to the gate of the tenth MOS transistor 242, the drain of the tenth MOS transistor 242, and the first bias current source 245, the source of the ninth MOS transistor 241 is electrically connected to the source of the tenth MOS transistor 242, the gate of the eleventh MOS transistor 243 is electrically connected to the gate of the twelfth MOS transistor 244, the drain of the eleventh MOS transistor 243, and the first bias current source 245, the source of the eleventh MOS transistor 243 is electrically connected to the source of the twelfth MOS transistor 244, the drain of the ninth MOS transistor 241 is electrically connected to the drain of the second MOS transistor 212, the drain of the eleventh MOS 243 is electrically connected to the drain of the third MOS transistor 213, the source of the tenth MOS transistor 242 is electrically connected to the source of the thirteenth MOS transistor 251, and the source of the twelfth MOS transistor 244 is electrically connected to the source of the fourteenth MOS transistor 252.

Specifically, a drain of the thirteenth MOS 251 is electrically connected to a drain of the fourteenth MOS 252 and a gate of the fourteenth MOS 252, wherein a source of the thirteenth MOS 251 is used as the first end of the differential input circuit 250, a source of the fourteenth MOS 252 is used as the second end of the differential input circuit 250, and a gate of the fourteenth MOS 252 is used as the third end of the differential input circuit 250.

In an example, the drain of the thirteenth MOS tube 251 is electrically connected to the drain of the fourteenth MOS tube 252 and the gate of the fourteenth MOS tube 252, the source of the thirteenth MOS tube is electrically connected to the source of the tenth MOS tube 242, the source of the fourteenth MOS tube 252 is electrically connected to the source of the twelfth MOS tube 244, and the gate of the eleventh MOS tube 243 is electrically connected to the source of the fifteenth MOS tube 261.

Here, the thirteenth MOS tube 251 and the fourteenth MOS tube 252 form a differential input, such differential input using PMOS allows the common mode level to be 0, the differential mode current controlled by the first differential input voltage (out) and the second differential input voltage (source) is represented by the leakage current of the ninth MOS tube 241 and the twelfth MOS tube 244, and the differential input is symmetrical, and the mismatch caused by the differential input is very low on the premise that the aspect ratio is sufficient.

Specifically, the drain of the fifteenth MOS 261 is electrically connected to the second bias current source 263 and the gate of the sixteenth MOS 262, respectively, and the source of the sixteenth MOS 262 is electrically connected to the source of the fifteenth MOS 261, wherein the gate of the fifteenth MOS 261 serves as the first end of the driving circuit 260, and the source of the fifteenth MOS 261 serves as the second end of the driving circuit 260.

In an example, the drain of the fifteenth MOS tube 261 is electrically connected to the second bias current source 263 and the gate of the sixteenth MOS tube 262, the source of the sixteenth MOS tube 262 is electrically connected to the source of the fifteenth MOS tube 261, and the gate of the fifteenth MOS tube 261 is electrically connected to the gate of the eighth MOS tube 232.

Here, the fifteenth MOS 261 is designed by the sixteenth MOS 262, and can generate a pull-down current or a driving current of at most Ip for the gate terminal, when the fifteenth MOS 261 is in the operational amplifier state, under the loop control of the high-gain operational amplifier, the level of the gate with respect to the second differential input voltage source is adjusted by adjusting the magnitude of the leakage current of the fifteenth MOS 261, and the voltage difference of the gate with respect to the second differential input voltage source is the driving voltage of the sixteenth MOS 262 for external power, so as to ensure that the forward voltage drop of the second differential input voltage with respect to the first differential input voltage is always maintained under the current load within a certain range. When external factors change to cause the first differential input voltage out to rise with respect to the second differential input voltage source, the gate voltage of the fifteenth MOS tube 261 will gradually rise to discharge the charges injected to the gate by the constant current source, but if the first differential input voltage out exceeds the second differential input voltage source and meets the reverse turn-off voltage, the gate of the fifteenth MOS tube 261 will rise to the maximum value at this time, so as to discharge the charges to the gate with the maximum capability, and turn off the power sixteenth MOS tube 262.

Here, the sixteenth MOS transistor 262 may be an NMOS transistor.

In an example, the gate of the thirteenth MOS transistor is electrically connected to the drain of the sixteenth MOS transistor.

Further, referring to fig. 4, fig. 4 is a schematic structural diagram of a topology circuit equivalent to an operational amplifier of the combination of the operational amplifier and the comparator according to the embodiment of the present application. As shown in fig. 4, the first MOS transistor 211 and the second MOS transistor 212 are connected in parallel to form a first target MOS transistor, the third MOS transistor 213 and the fourth MOS transistor 214 are connected in parallel to form a second target MOS transistor, a gate of the first target MOS transistor is electrically connected to a gate of the second target MOS transistor and a drain of the first target MOS transistor, respectively, and the second target MOS transistor is electrically connected to a gate of the third MOS transistor 213.

Illustratively, the first MOS transistor 211 is a first target MOS transistor connected in parallel with the second MOS transistor 212, the third MOS transistor 213 is a second target MOS transistor connected in parallel with the fourth MOS transistor 214, a gate of the first target MOS transistor is electrically connected to a gate of the second target MOS transistor and a drain of the first target MOS transistor, respectively, the second target MOS transistor is electrically connected to a gate of the third MOS transistor 213, a source of the first target MOS transistor is electrically connected to a source of the first MOS transistor 211, a drain of the first target MOS transistor is electrically connected to a drain of the seventh MOS transistor 231, a source of the second target MOS transistor is electrically connected to a source of the third MOS transistor 213, and a drain of the second target MOS transistor is electrically connected to a drain of the tenth MOS transistor 242 and a gate of the third MOS transistor 213.

Here, when the first differential input voltage of the differential input circuit 250 is lower than the second differential input voltage by Δ V, the current flowing through the first target MOS is slightly larger than the current flowing through the second target MOS (with slightly smaller width-to-length ratio), where the first target MOS is composed of MA5 and MA4, and the second target MOS is composed of MB5 and MB4, and the width-to-length ratios of the four sets of MOS satisfy the following relation:

W/L _M1 is the width-to-length ratio, W/L, of the first MOS transistor 211 _M2 Is the width-to-length ratio, W/L, of the second MOS transistor 212 _M3 Is the width-to-length ratio, W/L, of the third MOS transistor 213 _M4 Width-to-length ratio of the fourth MOS transistor 214) =1+ δ, where δ is a coefficient slightly greater than 0, so as to ensure that the active load 210 has weak asymmetry, and a determined equivalent input offset, i.e., a forward voltage drop Vos _ ea, is constructed, so that a negative feedback stabilization condition is satisfied, and after the state is stabilized, the first differential input voltage out side is lower than the second differential input voltage source side by Δ V, which is designed to be the forward voltage drop Vos _ ea, so that the topology circuit serves as an operational amplifier.

In a specific embodiment, the drain of the fifth MOS transistor 221 is electrically connected to the drain and the gate of the sixth MOS transistor 222, wherein the source of the fifth MOS transistor 221 is electrically connected to the source of the first MOS transistor 211, the gate of the fifth MOS transistor 221 is electrically connected to the gate of the first MOS transistor 211, the gate of the sixth MOS transistor 222 is electrically connected to the gate of the eighth MOS transistor 232, the source of the sixth MOS transistor 222 is electrically connected to the source of the eighth MOS transistor 232, the drain of the seventh MOS transistor 231 is electrically connected to the drain of the eighth MOS transistor 232, the source of the seventh MOS transistor 231 is electrically connected to the source of the fourth MOS transistor 214, the gate of the seventh MOS transistor 231 is electrically connected to the gate of the fourth MOS transistor 214, the gate of the eighth MOS transistor 232 is electrically connected to the gate of the sixth MOS transistor 222, and the drain of the eighth MOS transistor 232 is electrically connected to the gate of the fifteenth MOS transistor 261. The gate of the ninth MOS transistor 241 is electrically connected to the gate of the tenth MOS transistor 242, the drain of the tenth MOS transistor 242, and the first bias current source 245, the source of the ninth MOS transistor 241 is electrically connected to the source of the tenth MOS transistor 242, the gate of the eleventh MOS transistor 243 is electrically connected to the gate of the twelfth MOS 244, the drain of the eleventh MOS 243, and the first bias current source 245, the source of the eleventh MOS 243 is electrically connected to the source of the twelfth MOS 244, the drain of the ninth MOS 241 is electrically connected to the drain of the second MOS 212, the drain of the eleventh MOS 243 is electrically connected to the drain of the third MOS 213, the source of the tenth MOS 242 is electrically connected to the source of the thirteenth MOS 251, and the source of the twelfth MOS 244 is electrically connected to the source of the fourteenth MOS 252. The drain of the thirteenth MOS 251 is electrically connected to the drain of the fourteenth MOS 252 and the gate of the fourteenth MOS 252, the source of the thirteenth MOS is electrically connected to the source of the tenth MOS 242, the source of the fourteenth MOS 252 is electrically connected to the source of the twelfth MOS 244, and the gate of the eleventh MOS 243 is electrically connected to the source of the fifteenth MOS 261. The drain of the fifteenth MOS tube 261 is electrically connected to the second bias current source 263 and the gate of the sixteenth MOS tube 262, the source of the sixteenth MOS tube 262 is electrically connected to the source of the fifteenth MOS tube 261, and the gate of the fifteenth MOS tube 261 is electrically connected to the gate of the eighth MOS tube 232. When the first differential input voltage out of the differential input circuit 250 is lower than the second differential input voltage source by Δ V, the four MOS transistors in the active load 210 are in the first connection mode, the first target MOS transistor formed by connecting the first MOS transistor 211 and the second MOS transistor 212 in parallel, the second target MOS transistor formed by connecting the third MOS transistor 213 and the fourth MOS transistor 214 in parallel, the gate of the first target MOS transistor is electrically connected to the gate of the second target MOS transistor and the drain of the first target MOS transistor, respectively, the second target MOS transistor is electrically connected to the gate of the third MOS transistor 213, the source of the first target MOS transistor is electrically connected to the source of the first MOS transistor 211, the drain of the first target MOS transistor is electrically connected to the drain of the seventh MOS transistor 231, the source of the second target MOS transistor is electrically connected to the source of the third MOS transistor 213, and the drain of the second target MOS transistor is electrically connected to the drain of the tenth MOS transistor 242 and the gate of the third MOS transistor 213. So as to realize the function of the operational amplifier, and to realize that the power loss on the path is effectively reduced when the current flowing through the sixteenth MOS transistor is large.

Further, referring to fig. 5, fig. 5 is a schematic structural diagram of a topology circuit equivalent to a comparator of a combination of an operational amplifier and a comparator according to an embodiment of the present application. As shown in fig. 5, the gate of the second MOS transistor 212 is electrically connected to the gate of the fourth MOS transistor 214, the drain of the fourth MOS transistor 214 is electrically connected to the gate of the fourth MOS transistor 214, and the first MOS transistor 211 and the third MOS transistor 213 are turned off.

Illustratively, the first MOS transistor 211 and the third MOS transistor 213 are turned off, the gate of the second MOS transistor 212 is electrically connected to the gate of the fourth MOS transistor 214, the drain of the fourth MOS transistor 214 is electrically connected to the gate of the fourth MOS transistor 214, the source of the second MOS transistor 212 is electrically connected to the source of the first MOS transistor 211, the drain of the second MOS transistor 212 is electrically connected to the drain of the seventh MOS transistor 231, the source of the second MOS transistor 212 is electrically connected to the source of the third MOS transistor 213, and the drain of the second MOS transistor 212 is electrically connected to the drain of the tenth MOS transistor 242 and the gate of the third MOS transistor 213.

Here, when the first differential input voltage of the differential input circuit 250 is higher than the second differential input voltage by Δ V, the current flowing through the second MOS transistor 212 is slightly smaller than the current flowing through the fourth MOS transistor 214 (the width/length ratio is slightly larger), the first MOS transistor 211 and the third MOS transistor 213 are turned off, and the width/length ratios of the four sets of MOS satisfy the following relation:

wherein ρ is a coefficient slightly greater than 0, which ensures that the active load 210 has weak asymmetry, and a determined equivalent input offset, i.e., the reverse turn-off voltage Vos _ com, is constructed, so that only when the first differential input voltage side of the differential input circuit 250 is higher than the second differential input voltage side by Δ V, the current flowing through the second MOS transistor 212 (with a slightly smaller width-to-length ratio) side is slightly smaller than the current flowing through the fourth MOS transistor 214 (with a slightly larger width-to-length ratio), under such a condition, a positive feedback trigger condition can be satisfied, and under such a trigger condition, the Δ V is designed as the reverse turn-off voltage Vos _ com, so that the topology circuit serves as a comparator.

For example, the ratio between the width-to-length ratio of the first MOS transistor 211, the width-to-length ratio of the second MOS transistor 212, the width-to-length ratio of the third MOS transistor 213, and the width-to-length ratio of the fourth MOS transistor 214 is 3.5:2.5:2:3.

when ρ = δ, the ratio of the width-to-length ratio of the first MOS transistor 211 to the width-to-length ratio of the second MOS transistor 212 to the width-to-length ratio of the third MOS transistor 213 to the width-to-length ratio of the fourth MOS transistor 214 is 3.5:2.5:2:3, the ratio of the width-to-length ratio of the first MOS transistor 211, the width-to-length ratio of the second MOS transistor 212, the width-to-length ratio of the third MOS transistor 213, and the width-to-length ratio of the fourth MOS transistor 214 is not limited to 3.5:2.5:2:3, setting the width-length ratio according to actual requirements

In a specific embodiment, in the specific embodiment, the drain of the fifth MOS 221 is electrically connected to the drain and the gate of the sixth MOS 222, wherein the source of the fifth MOS 221 is electrically connected to the source of the first MOS 211, the gate of the fifth MOS 221 is electrically connected to the gate of the first MOS 211, the gate of the sixth MOS 222 is electrically connected to the gate of the eighth MOS 232, the source of the sixth MOS 222 is electrically connected to the source of the eighth MOS 232, the drain of the seventh MOS 231 is electrically connected to the drain of the eighth MOS 232, the source of the seventh MOS 231 is electrically connected to the source of the fourth MOS 214, the gate of the seventh MOS 231 is electrically connected to the gate of the fourth MOS 214, the gate of the eighth MOS 232 is electrically connected to the gate of the sixth MOS 222, and the drain of the eighth MOS 232 is electrically connected to the gate of the fifteenth MOS 261. The gate of the ninth MOS transistor 241 is electrically connected to the gate of the tenth MOS transistor 242, the drain of the tenth MOS transistor 242 and the first bias current source 245, the source of the ninth MOS transistor 241 is electrically connected to the source of the tenth MOS transistor 242, the gate of the eleventh MOS transistor 243 is electrically connected to the gate of the twelfth MOS transistor 244, the drain of the eleventh MOS transistor 243 and the first bias current source 245, the source of the eleventh MOS transistor 243 is electrically connected to the source of the twelfth MOS transistor 244, the drain of the ninth MOS transistor 241 is electrically connected to the drain of the second MOS transistor 212, the drain of the eleventh MOS 243 is electrically connected to the drain of the third MOS 213, the source of the tenth MOS transistor 242 is electrically connected to the source of the thirteenth MOS transistor 251, and the source of the twelfth MOS 244 is electrically connected to the source of the fourteenth MOS transistor 252. The drain of the thirteenth MOS tube 251 is electrically connected to the drain of the fourteenth MOS tube 252 and the gate of the fourteenth MOS tube 252, the source of the thirteenth MOS tube is electrically connected to the source of the tenth MOS tube 242, the source of the fourteenth MOS tube 252 is electrically connected to the source of the twelfth MOS tube 244, and the gate of the eleventh MOS tube 243 is electrically connected to the source of the fifteenth MOS tube 261. The drain of the fifteenth MOS tube 261 is electrically connected to the second bias current source 263 and the gate of the sixteenth MOS tube 262, the source of the sixteenth MOS tube 262 is electrically connected to the source of the fifteenth MOS tube 261, and the gate of the fifteenth MOS tube 261 is electrically connected to the gate of the eighth MOS tube 232. When the first differential input voltage out of the differential input circuit 250 is higher than the second differential input voltage source by Δ V, the four MOS transistors in the active load 210 are in the second connection mode, the first MOS transistor 211 and the third MOS transistor 213 are turned off, the gate of the second MOS transistor 212 is electrically connected to the gate of the fourth MOS transistor 214, the drain of the fourth MOS transistor 214 is electrically connected to the gate of the fourth MOS transistor 214, the source of the second MOS transistor 212 is electrically connected to the source of the first MOS transistor 211, the drain of the second MOS transistor 212 is electrically connected to the drain of the seventh MOS transistor 231, the source of the second MOS transistor 212 is electrically connected to the source of the third MOS transistor 213, the drain of the second MOS transistor 212 is electrically connected to the drain of the tenth MOS transistor 242 and the gate of the third MOS transistor 213, but if the first differential input voltage out exceeds the second differential input voltage source and satisfies the reverse turn-off voltage, the gate of the fifteenth MOS transistor is raised to the maximum 261, and the gate of the sixteenth MOS transistor is turned off 262 with the maximum capability to discharge the charge of the gate.

Further, referring to fig. 6, fig. 6 is a comparison diagram of an operational amplifier and comparator combination and an independent design of the operational amplifier and comparator according to an embodiment of the present disclosure. As shown in fig. 6, in the present solution, a circuit topology is used, and the feedback of the operational amplifier and the comparison function of the comparator are combined together, during the forward conduction period, the circuit topology shows the negative feedback characteristic of the operational amplifier, the voltage drop across the feedback depends on the ratio α of the number of transistors of the internal active load, and the forward conduction voltage drop value corresponds to Vos _ ea; when external factors cause that the power NMOS (sixteenth MOS tube) needs to be turned off, the circuit topology is represented as a comparator, the comparison trigger level point of the comparator also depends on the ratio beta of the number of the transistors of the internal active load, the reverse turn-off voltage corresponds to Vos _ com, because both are determined by the same active load, and the forward voltage drop distribution function Vos _ ea (X) and the reverse turn-off distribution function Vos _ com (Y) meet the function correlation. The forward droop distribution function Vos _ ea (X) and the reverse turn-off distribution function Vos _ com (Y) satisfy a functional correlation, which can be described by using a guard interval function G (X-Y), which means that the statistical analysis is performed by using the Vos _ ea-Vos _ com specific to each chip as a sample function. By analyzing the independent design of the operational amplifier and the comparator and the comparison of the scheme in which the operational amplifier and the comparator are fused, G1 (X-Y) and G2 (X-Y) under the two designs are represented as follows: to reduce the forward voltage drop, the distribution center μ os _ ea of the forward on voltage drop is reduced, and considering that the guard interval from the reverse turn-off cannot be too low in distribution (μ -3 σ > 0) or otherwise causes oscillation, the distribution center μ os _ com of the reverse turn-off voltage must be reduced (even into a negative value) so that the center μ of G1 (X-Y) is expected to be sufficiently high, and the distribution is guaranteed to be mostly positive, but causes the distribution of the reverse turn-off voltage to be too low (or even mostly negative), and significant reverse current will occur. In the scheme, the central expectation mu of the protection pitch function G2 (X-Y) is the same as that of the left graph, the amplification and comparison links are related in circuit topology, the pitch difference also depends on the number proportion of MOS (metal oxide semiconductor) tubes, the theoretical dispersion is small, the forward voltage drop mu os _ ea is reduced, the distribution of G2 (X-Y) is very concentrated, a designer can enable the distribution center mu os _ com of the reverse turn-off voltage to be close to the forward voltage drop mu os _ ea, and therefore the central expectation mu of G2 (X-Y) is low, and the situation that the distribution of G2 (X-Y) is smaller than 0 does not need to be worried. Since the distribution of the reverse turn-off voltage can be high (even mostly positive), the reverse current is not significant.

The topological circuit for combining the operational amplifier and the comparator comprises an active load, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a drive circuit, wherein the active load comprises four MOS (metal oxide semiconductor) tubes, and each of the two single-ended conversion circuits comprises 2 MOS tubes; the first end of the first single-ended conversion circuit is electrically connected with the first end of the active load, the second end of the first single-ended conversion circuit is electrically connected with the second end of the active load, the third end of the first single-ended conversion circuit is electrically connected with the third end of the second single-ended conversion circuit, and the fourth end of the first single-ended conversion circuit is electrically connected with the fourth end of the second single-ended conversion circuit and the second end of the driving circuit; the first end of the second single-ended conversion circuit is electrically connected with the third end of the active load, the second end of the second single-ended conversion circuit is electrically connected with the fourth end of the active load, and the fifth end of the second single-ended conversion circuit is electrically connected with the first end of the drive circuit; the fifth end of the active load is electrically connected with the first end of the differential current conversion circuit, the sixth end of the active load is electrically connected with the second end of the differential current conversion circuit, the third end of the differential current conversion circuit is electrically connected with the first end of the differential input circuit, the fourth end of the differential current conversion circuit is electrically connected with the second end of the differential input circuit, and the third end of the differential input circuit is electrically connected with the second end of the driving circuit; when the first differential input voltage of the differential input circuit is smaller than the second differential input voltage, the four MOS tubes of the active load are in a first connection mode to realize the function of an operational amplifier; when the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS tubes of the active load are in a second connection mode to realize the function of the comparator. The operational amplifier and the comparator circuit structure are shared on the circuit topology, and a related mechanism is formed on the mechanism of generating forward voltage drop and reverse turn-off voltage, so that the advantage of keeping the forward voltage drop as low as possible is realized, and the reverse turn-off point is not too far away from the origin, so that the aims of reducing reverse current and avoiding oscillation during the reverse turn-off period are fulfilled. It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, and for example, the division of the units into only one type of logical function may be implemented in other ways, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some communication interfaces, indirect coupling or communication connection between devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present application, and are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A topological circuit combining an operational amplifier and a comparator is characterized in that the topological circuit comprises an active load, a plurality of transistors, a plurality of single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a driving circuit, wherein the active load comprises four MOS tubes; the active load comprises four MOS tubes, and each single-ended conversion circuit comprises two MOS tubes; wherein the content of the first and second substances,

the first end of the second single-ended conversion circuit is electrically connected with the third end of the active load, the second end of the second single-ended conversion circuit is electrically connected with the fourth end of the active load, and the fifth end of the second single-ended conversion circuit is electrically connected with the first end of the drive circuit;

2. The topology circuit of claim 1, wherein the active load comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; wherein the content of the first and second substances,

the source electrode of the first MOS tube is electrically connected with the source electrode of the second MOS tube, and the grid electrode of the first MOS tube is electrically connected with the drain electrode of the second MOS tube and the drain electrode of the first MOS tube, wherein the source electrode of the first MOS tube is used as the first end of the active load, the grid electrode of the first MOS tube is used as the second end of the active load, and the drain electrode of the first MOS tube is used as the fifth end of the active load;

3. The topology circuit of claim 2, wherein the first connection means is:

4. The topology circuit of claim 2, wherein the second connection mode is:

5. The topology circuit of claim 1, wherein the first single-ended conversion circuit comprises two MOS transistors; wherein the content of the first and second substances,

6. The topology circuit of claim 1, wherein the second single-ended conversion circuit comprises two MOS transistors; wherein the content of the first and second substances,

7. The topology circuit of claim 1, wherein the differential current conversion circuit comprises four MOS transistors and a first bias current source; wherein the content of the first and second substances,

8. The topology circuit of claim 1, wherein the differential input circuit comprises two MOS transistors; wherein the content of the first and second substances,

the drain of the thirteenth MOS tube is electrically connected with the drain of the fourteenth MOS tube and the gate of the fourteenth MOS tube, wherein the source of the thirteenth MOS tube is used as the first end of the differential input circuit, the source of the fourteenth MOS tube is used as the second end of the differential input circuit, and the gate of the fourteenth MOS tube is used as the third end of the differential input circuit.

9. The topology circuit of claim 1, wherein the driving circuit comprises two MOS transistors and a second bias current source; wherein the content of the first and second substances,

the drain of the fifteenth MOS transistor is electrically connected to the second bias current source and the gate of the sixteenth MOS transistor, and the source of the sixteenth MOS transistor is electrically connected to the source of the fifteenth MOS transistor, where the gate of the fifteenth MOS transistor is used as the first end of the driving circuit, and the source of the fifteenth MOS transistor is used as the second end of the driving circuit.

10. The topological circuit of claim 2, wherein a ratio between a width-to-length ratio of the first MOS transistor, a width-to-length ratio of the second MOS transistor, a width-to-length ratio of the third MOS transistor, and a width-to-length ratio of the fourth MOS transistor is 3.5:2.5:2:3.