CN115657572A - Design method for modular SoC chip power management system controller - Google Patents
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- CN115657572A CN115657572A CN202211678953.4A CN202211678953A CN115657572A CN 115657572 A CN115657572 A CN 115657572A CN 202211678953 A CN202211678953 A CN 202211678953A CN 115657572 A CN115657572 A CN 115657572A
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Abstract
The invention discloses a design method of a modular SoC chip power management system controller, which comprises the following specific steps: step S1: constructing a single subsystem control unit; step S2: connecting a plurality of single subsystem control units in a cascade manner to form a cascade sub-state machine; and step S3: and combining the cascade sub-state machines with an SoC main state machine control unit to construct a power management system controller. The single subsystem control unit realizes the multiplexing in different SoC chips.
Description
Technical Field
The invention relates to the technical field of power management systems, in particular to a design method of a modular SoC chip power management system controller.
Background
The SoC chip power management system is generally composed of a plurality of subsystem modules, such as a reference voltage subsystem module, an LDO power subsystem module, a clock load subsystem module, and the like. The controller of the power management system is used for controlling the system to enable and close each subsystem module according to a specific time sequence when the system is powered on or powered off and various working modes are switched;
different SoCs are composed of different subsystem modules, and the dependency relationship among the subsystem modules is different, so that the design of the controller of the complex power management system is often realized by consuming high design verification cost, and the control logic is basically not reusable among different systems;
in the prior art, a complex and complete power control state machine is designed according to different subsystem modules of an SoC and the enabling and closing dependency relationship among the subsystem modules, and all corresponding time sequence control is completed through the state machine, so that the complexity of system-level control logic is high, the maintenance and the updating are inconvenient, and the multiplexing among different systems cannot be realized;
the prior art can not meet the requirements of people at the present stage, and the prior art is urgently needed to be reformed based on the current situation.
Disclosure of Invention
The present invention is directed to a method for designing a modular SoC chip power management system controller to solve the above problems in the background art.
The invention provides a method for designing a modular SoC chip power management system controller, which comprises the following steps:
step S1: constructing a single subsystem control unit;
step S2: connecting a plurality of single subsystem control units in a cascade manner to form a cascade sub-state machine;
and step S3: combining the cascade sub-state machine with an SoC main state machine control unit to construct a power management system controller;
preferably, in step S1, signal input pins of the single subsystem control unit are configured: an application enabling pin en _ req, an enabling allowing pin en _ grant, a feedback notification pin ack, an application closing pin dis _ req, and an allowing closing pin dis _ grant;
preferably, the application enabling pin en _ req and the application closing pin dis _ req are controlled by the SoC master state machine control unit;
preferably, the enable pin en _ grant and the disable pin dis _ grant are controlled by other subsystem control units cascade-connected to the single subsystem control unit, and the feedback notification pin ack is feedback-controlled by a sub-module controlled by the single subsystem control unit.
Preferably, in step S2, the specific connection mode is: coupling an enable control completion flag on of a first single subsystem control unit to an enable pin en _ grant of a second single subsystem control unit, coupling an enable control completion flag on of the second single subsystem control unit to an enable pin en _ grant of a third single subsystem control unit, and so on, coupling a close control completion flag off of a last single subsystem control unit to an enable close pin dis _ grant of a previous single subsystem control unit;
preferably, in step S3, the SoC master state machine control logic may set a high level or a low level to the input pin of the single subsystem control unit according to a specific timing sequence, so as to implement control of enabling, closing, status indication, and the like of the single subsystem control unit;
preferably, in step S3, the SoC master state machine control logic may set a high level or a low level to a signal input pin of each single subsystem control unit in the cascaded sub-state machine according to a specific timing sequence, so as to control enabling, shutting down, and the like of the power management system controller.
The invention firstly proposes to build a single subsystem control unit, the control unit can be multiplexed in different SoCs, and realizes the design of the SoC power management system controller by cascading the control units, thereby greatly simplifying the design of the SoC power management system controller, realizing the control of enabling or closing a plurality of sub-module control units (single subsystem control units), and having convenient updating and maintenance and high reusability.
Drawings
FIG. 1 is a schematic diagram of a single subsystem control unit configuration according to the present invention;
FIG. 2 is a timing diagram of a single subsystem control unit of the present invention;
FIG. 3 is a schematic diagram of the connection of the present invention enabling two individual subsystem control units;
FIG. 4 is a schematic diagram of the present invention showing the connection of two individual subsystem control units being shut down;
FIG. 5 is a schematic diagram of the connections enabling three individual subsystem control units according to the present invention;
FIG. 6 is a schematic diagram of the present invention showing the connection of three individual subsystem control units;
FIG. 7 is a schematic flow chart of the present invention;
FIG. 8 is a diagram of a controller of the power management system according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the invention without making any creative effort, shall fall within the protection scope of the invention.
Referring to fig. 7, the present invention first provides a method for designing a modular SoC chip power management system controller according to the following technical solution, which specifically includes the steps:
referring to fig. 1, step S1: constructing a single subsystem control unit;
specifically, a signal input pin of a single subsystem control unit is established: an application enabling pin en _ req, an enabling allowing pin en _ grant, a feedback notification pin ack, an application closing pin dis _ req, and an allowing closing pin dis _ grant; in an embodiment, the application enable pin en _ req and the application close pin dis _ req are controlled by an SoC master state machine control unit, the enable pin en _ grant and the close enable pin dis _ grant are controlled by other subsystem control units cascade-connected to the single subsystem control unit, and the feedback notification pin ack is feedback-controlled by a submodule controlled by the single subsystem control unit.
Specifically, a single subsystem control unit is configured with signal output pins: an enable signal en, an enable control completion flag on, and a close control completion flag off; in an embodiment, the enable signal en is used to output an enable signal of a single subsystem control unit; the enabling control completion flag on is used for being sent to the SoC main state machine control unit or other subsystem control units to be used as enabling completion state identification; and the closing control completion mark off is used for being sent to the SoC main state machine control unit or other subsystem control units to be used as closing completion state marks.
Step S2: connecting a plurality of single subsystem control units in a cascade manner to form a cascade sub-state machine;
referring to fig. 8, in an embodiment, three single subsystem control units are connected in cascade: the first submodule control unit, the second submodule control unit and the third submodule control unit form a cascade submodule state machine; the concrete connection mode is as follows: coupling an enabling control completion flag on of the first sub-module control unit to an enabling pin en _ grant of the second sub-module control unit, coupling an enabling control completion flag on of the second sub-module control unit to an enabling pin en _ grant of the third sub-module control unit, and finally coupling a closing control completion flag off of the third sub-module control unit to an enabling pin dis _ grant of the second sub-module control unit;
in the embodiment, the plurality of single subsystem control units are connected in a cascade manner in various manners, and according to requirements, the plurality of single subsystem control units can be used together in a serial or parallel cascade manner, and after cascade connection, the control of enabling, closing and the like of the plurality of subsystem control units can be realized according to a specific time sequence.
Referring to fig. 3, the present invention provides another alternative embodiment in which two single subsystem control units are provided: the control unit of the submodule 1 and the control unit of the submodule 2 are used for coupling the enabling control completion mark on of the control unit of the submodule 1 to the enabling pin en _ grant of the control unit of the submodule 2, and the control unit of the submodule 2 can enable the submodule 1 to be operated after the control unit of the submodule 1 is enabled, so that the enabling control of the control unit of the submodule 1 and the control unit of the submodule 2 is realized.
Referring to fig. 4, the present invention provides another alternative embodiment in which two single subsystem control units are provided: the control unit of the sub-module 3 and the control unit of the sub-module 4 couple a closing control completion flag off of the control unit of the sub-module 3 to a closing permission pin dis _ grant of the control unit of the sub-module 4, and the control unit of the sub-module 4 can close the operation only after the control unit of the sub-module 3 is closed, so that the closing control of the control unit of the sub-module 3 and the control unit of the sub-module 4 is realized.
Referring to fig. 5, the present invention provides another alternative embodiment in which three individual subsystem control units are provided: the control method comprises a submodule 5 control unit, a submodule 6 control unit and a submodule 7 control unit, enabling control completion marks on of the submodule 5 control unit and the submodule 6 control unit are coupled to an enabling pin en _ grant of the submodule 7 control unit in parallel, the submodule 7 control unit can enable operation after the submodule 5 control unit and the submodule 6 control unit are enabled, and enabling control over the submodule 5 control unit, the submodule 6 control unit and the submodule 7 control unit is achieved.
Referring to fig. 6, the present invention provides another alternative embodiment in which three individual subsystem control units are provided: the control unit of the sub-module 8, the control unit of the sub-module 9 and the control unit of the sub-module 10 are connected in parallel with an enable control completion flag on of the control unit of the sub-module 8 and an off control completion flag off of the control unit of the sub-module 9 to an enable pin en _ grant of the control unit of the sub-module 10, the control unit of the sub-module 10 needs to enable operation after the control unit of the sub-module 8 is enabled and after the control unit of the sub-module 9 is turned off, and therefore the control on turning off of the control unit of the sub-module 8, the control unit of the sub-module 9 and the control unit of the sub-module 10 is achieved.
Referring to fig. 8, step S3: combining the cascade sub-state machine with an SoC main state machine control unit to construct a power management system controller;
in the embodiment, the high level or the low level can be set for the input pin of the single subsystem control unit according to a specific time sequence through the SoC master state machine control logic, so that the control of enabling, closing, state indication and the like of the single subsystem control unit is realized;
referring to fig. 2, in the embodiment, the timing of the single subsystem control unit control is as follows, when enabled (1 denotes a high level, 0 denotes a low level), when en _ req = 1 and en _ grant = 1, en is set, the single subsystem control unit returns an ack high signal after completion of enabling, completes enabling control, and pulls up an enable control completion flag on; when the system is closed, when dis _ req = 1 and dis _ grant = 1, en is reset and pulled low, the single subsystem control unit returns an ack low signal after closing is finished, closing control is finished, and a closing control completion flag is pulled high off, so that the logic of the single subsystem control unit controlled by the SoC main state machine is very simple, maintenance and updating are convenient, and the system can be reused in different SoCs;
in an embodiment, the SoC main state machine control logic may set a high level or a low level to a signal input pin of each single subsystem control unit in the cascade sub-state machine according to a specific timing sequence, so as to control enabling, shutting down, and the like of the power management system controller.
Specifically, in the embodiment, the SoC master state machine control unit sets the application enable pins en _ req of the first sub-module control unit, the second sub-module control unit, and the third sub-module control unit to be level 1, so that the power management system controller can be set to default all enable states, and the enable sequence is the first sub-module control unit- > the second sub-module control unit- > the third sub-module control unit.
Specifically, in the embodiment, the application closing pin dis _ req of the first sub-module control unit is set to be level 0 by the SoC master state machine control unit, and the application closing pins dis _ req of the second sub-module control unit and the third sub-module control unit are both set to be level 1, that is, the power management system controller is set to be in the low power consumption mode, the closing sequence of the second sub-module control unit and the third sub-module control unit is the third sub-module control unit- > the second sub-module control unit, and only the first sub-module control unit is kept in the enabling state.
Therefore, the working mode of the power management system controller can be controlled to be a default working mode or a low-power consumption mode by the SoC master state machine control unit only needing to simply control the switching of the working mode and outputting the level states of en _ req and dis _ req of each submodule control unit according to the mode requirement.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some features of the invention can be made without departing from the spirit and scope of the invention.
Claims (12)
1. A design method of a modular SoC chip power management system controller is characterized in that the controller can be multiplexed in different SoCs and can realize the enabling control and closing control of a plurality of single subsystem control units;
the method comprises the following specific steps:
step S1: constructing a single subsystem control unit;
step S2: connecting a plurality of single subsystem control units in a cascade manner to form a cascade sub-state machine;
and step S3: and combining the cascade sub-state machines with an SoC main state machine control unit to construct a power management system controller.
2. The modular SoC chip power management system controller design method of claim 1, wherein: the specific method of step S1 includes:
signal input pins of a single subsystem control unit are established: an application enabling pin en _ req, an enabling allowing pin en _ grant, a feedback notification pin ack, an application closing pin dis _ req, and an allowing closing pin dis _ grant; wherein the content of the first and second substances,
the application enabling pin en _ req and the application closing pin dis _ req are controlled by an SoC master state machine control unit;
the enable pin en _ grant and the disable pin dis _ grant are controlled by other subsystem control units which are in cascade connection with the single subsystem control unit;
the feedback notification pin ack is feedback controlled by a sub-module controlled by the single subsystem control unit.
3. The modular SoC chip power management system controller design method of claim 2, wherein: the specific method of step S1 further comprises:
and (3) forming a signal output pin of a single subsystem control unit: an enable signal en, an enable control completion flag on, and a close control completion flag off; wherein the content of the first and second substances,
the enable signal en is used for outputting an enable signal of a single subsystem control unit;
the enabling control completion flag on is used for being sent to the SoC main state machine control unit or other subsystem control units to be used as enabling completion state identification;
and the closing control completion mark off is used for being sent to the SoC main state machine control unit or other subsystem control units to be used as a closing completion state identifier.
4. The modular SoC chip power management system controller design method of claim 3, wherein: when the application enable pin en _ req and the enable pin en _ grant are both set to a high level, the enable signal en is set.
5. The modular SoC chip power management system controller design method of claim 3, wherein: when the application shutdown pin dis _ req and the permission shutdown pin dis _ grant are both set to a high level, the enable signal en is reset and pulled low.
6. The modular SoC chip power management system controller design method of claim 1, wherein: when the application enabling pins en _ req of the single subsystem control units in cascade connection are all set to be at a high level through the SoC master state machine control unit, the power management system controller defaults to be in a full enabling state.
7. The modular SoC chip power management system controller design method of claim 1, wherein: the application closing pin dis _ req of the first single subsystem control unit in the cascade sub-state machine is set to be at a low level through the SoC main state machine control unit, the application closing pins dis _ req of the other single subsystem control units in the cascade sub-state machine are set to be at a high level, and the power management system controller works in a low power consumption mode.
8. The modular SoC chip power management system controller design method of claim 6, wherein: the enabling sequence of the power management system controller is as follows: a first single subsystem control unit, a second single subsystem control unit, and up to an nth single subsystem control unit, wherein n represents the number of single subsystem control units.
9. The modular SoC chip power management system controller design method of claim 7, wherein: the low power consumption mode of the power management system controller is as follows: only the first individual subsystem control unit is kept in an enabled state, and the other individual subsystem control units are all in a closed state.
10. The modular SoC chip power management system controller design method of any of claims 1-9, wherein: the power management system controller can be composed of an SoC main state machine control unit and N single subsystem control units in a parallel or serial cascade mode, wherein N is more than or equal to 1.
11. The modular SoC chip power management system controller design method of claim 1, wherein: the cascade sub-state machine has two cascade modes of single subsystem control units, and comprises the following steps:
coupling an enabling control completion flag on of a single subsystem control unit of a previous stage to an enabling pin en _ grant of a single subsystem control unit of a next stage;
coupling a turn-off control completion flag off of a previous-stage single subsystem control unit to an enable pin en _ grant of a next-stage single subsystem control unit;
coupling an enabling control completion flag on of a single subsystem control unit of a previous stage to an allowable shutdown pin dis _ grant of a single subsystem control unit of a next stage;
the enable-off control completion flag off of the previous-stage single subsystem control unit is coupled to the enable-off pin dis _ grant of the next-stage single subsystem control unit.
12. The modular SoC chip power management system controller design method of claim 1, wherein: the cascade sub-state machine has more than two cascade modes of single subsystem control units, and comprises the following steps:
the enable control completion flag on or the off control completion flag off of the individual subsystem control unit preceding the subsequent stage is coupled to the enable off pin dis _ grant or the enable pin en _ grant of the individual subsystem control unit of the subsequent stage in a permutation and combination manner.
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Citations (5)
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| US20040227404A1 (en) * | 2003-05-12 | 2004-11-18 | Boros Mircea Cristian | Controlling devices using cascaded control units |
| CN201039123Y (en) * | 2007-04-28 | 2008-03-19 | 杭州华三通信技术有限公司 | Seamless cascading multi-channel power on control circuit |
| US20120042177A1 (en) * | 2010-08-12 | 2012-02-16 | Inventec Corporation | Computer System |
| CN104133545A (en) * | 2014-07-29 | 2014-11-05 | 三星半导体(中国)研究开发有限公司 | State machines of power management module of system-on-chip and creating method thereof |
| CN112799465A (en) * | 2019-10-28 | 2021-05-14 | 京东方科技集团股份有限公司 | Control signal generator and driving method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040227404A1 (en) * | 2003-05-12 | 2004-11-18 | Boros Mircea Cristian | Controlling devices using cascaded control units |
| CN201039123Y (en) * | 2007-04-28 | 2008-03-19 | 杭州华三通信技术有限公司 | Seamless cascading multi-channel power on control circuit |
| US20120042177A1 (en) * | 2010-08-12 | 2012-02-16 | Inventec Corporation | Computer System |
| CN104133545A (en) * | 2014-07-29 | 2014-11-05 | 三星半导体(中国)研究开发有限公司 | State machines of power management module of system-on-chip and creating method thereof |
| CN112799465A (en) * | 2019-10-28 | 2021-05-14 | 京东方科技集团股份有限公司 | Control signal generator and driving method thereof |
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