CN115656765B - Impedance test circuit of field effect transistor wafer - Google Patents
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Abstract
The invention provides an impedance test circuit of a field effect tube wafer, which relates to the field of test and comprises test equipment and the field effect tube wafer, wherein the field effect tube wafer comprises a first field effect tube and a second field effect tube which are adjacently arranged, the drain electrode of the first field effect tube is connected with the drain electrode of the second field effect tube, the first field effect tube is provided with a front surface and a back surface which are oppositely arranged, the test equipment is connected with the source electrode and the grid electrode of the first field effect tube and the source electrode of the second field effect tube from the front surface side so as to carry out impedance test on the first field effect tube, and the problems that test data are inaccurate and calibration is difficult to operate due to the fact that wires are long when the drain electrode of the field effect tube is led out from the back surface side of the field effect tube wafer are solved.
Description
Technical Field
The invention relates to the field of testing, in particular to an impedance testing circuit of a field effect transistor wafer.
Background
In the process of manufacturing the wafer, if most parameters can be tested at the wafer level, a great deal of cost can be saved in the subsequent packaging and other processes. Therefore, in ATE (automatic test equipment), field effect transistor wafer testing has a great test requirement. The test items of the field effect transistor wafer comprise an impedance Rg test, an input capacitor Ciss test, an output capacitor Coss test, a reverse transmission capacitor Crss test and the like.
However, testing the above parameters on a fet wafer places very high demands on the test equipment. The traditional test mode can be directly connected to a probe station chassis test scheme by using a long wire, namely, because the drain electrode of a field effect tube in a field effect tube wafer is positioned on the back side of the wafer, and the source electrode and the grid electrode of the field effect tube are positioned on the front side of the wafer, when the field effect tube in the field effect tube wafer is used, the drain electrode of the field effect tube needs to be led out from the back side of the wafer by using the long wire, so that the wire connected with the drain electrode of the field effect tube is longer, and when the test is carried out, the longer wire can attenuate signals of test equipment, parasitic inductance, parasitic capacitance and parasitic resistance can exist, the phase of the test signals can be influenced, namely, the longer wire can cause a plurality of parasitic parameters to cause inaccurate test results, and the test precision is influenced. The conventional test method can also adopt a load calibration test method, but because the test method needs load calibration and needs a standard wafer, the open circuit, short circuit and load calibration operations are difficult to be carried out on a probe station. The test mode is difficult to operate and implement in practical application.
Disclosure of Invention
The invention provides an impedance test circuit of a field effect transistor wafer, which can solve the problems of inaccurate test data and difficult calibration operation caused by long lead when a drain electrode of a field effect transistor is led out from the back side of the wafer.
In order to solve the above problems, the present invention provides an impedance test circuit for a field effect transistor wafer, including a test device and a field effect transistor wafer, where the field effect transistor wafer includes a first field effect transistor and a second field effect transistor which are adjacently disposed, a drain of the first field effect transistor is connected to a drain of the second field effect transistor, the first field effect transistor has a front surface and a back surface which are disposed oppositely, and the test device connects a source and a gate of the first field effect transistor and a source of the second field effect transistor from the front surface side so as to perform an impedance test on the first field effect transistor.
Optionally, the source and the gate of the first field effect transistor and the source and the gate of the second field effect transistor are disposed close to the front side, and the drain of the first field effect transistor and the drain of the second field effect transistor are disposed close to the back side.
Optionally, the field effect transistor wafer further includes a first diode and a second diode, an anode of the first diode is connected to the source of the first field effect transistor, and a cathode of the first diode is connected to the drain of the first field effect transistor; the anode of the second diode is connected with the source electrode of the second field effect transistor, and the cathode of the second diode is connected with the drain electrode of the second field effect transistor.
Optionally, the test device includes a first current output end, a first voltage sampling end, a second current output end, a second voltage sampling end, a current return end, and a third voltage sampling end;
the grid electrode and the source electrode of the first field effect transistor are respectively provided with a current input end and a voltage input end, and the grid electrode and the source electrode of the second field effect transistor are respectively provided with a current input end and a voltage input end;
the first current output end is connected with a current input end of a source electrode of the second field effect transistor, the second current output end is connected with a current input end of a grid electrode of the first field effect transistor, the second voltage sampling end is connected with a voltage input end of the grid electrode of the first field effect transistor, the current return end is connected with a current input end of the source electrode of the first field effect transistor, and the third voltage sampling end is connected with a voltage input end of the source electrode of the first field effect transistor.
Furthermore, the impedance test circuit further comprises a voltage source, wherein the anode of the voltage source is connected with the voltage input end of the grid electrode of the second field effect transistor, and the cathode of the voltage source and the first voltage sampling end are both connected with the voltage input end of the source electrode of the second field effect transistor.
Furthermore, the test equipment further comprises a first inductor, a first capacitor, a first resistor and a direct current source, wherein one end of the first resistor is connected with the direct current source, the other end of the first resistor is connected with one end of the first inductor, and the other end of the first inductor is connected with the first current output end, the first voltage sampling end and one end of the first capacitor.
Further, when the impedance test and the input capacitance test are performed, the other end of the first capacitor is connected to the current return end and is used for short-circuiting a capacitor between a drain electrode and a source electrode of the field effect transistor to be tested at high frequency, the test equipment provides high current to the second current output end, the second voltage sampling end samples the output high current and obtains sampled current, and the test equipment provides virtual ground to the current return end and the third voltage sampling end;
the high current is a sinusoidal voltage waveform with the peak value of 0.01V to 2V and the frequency of 1Hz to 2MHz, and the virtual ground is equipotential with a negative electrode end of a source generating the sinusoidal voltage waveform.
Further, when the reverse transmission capacitor test is performed, the test equipment provides a high current to the other end of the first capacitor, so that the first current output end outputs the high current, the first voltage sampling end samples the output high current to obtain a sampled current, the test equipment provides a virtual ground to the second current output end and the second voltage sampling end, and the current return end and the third voltage sampling end are grounded;
the high current is a sinusoidal voltage waveform with the peak value of 0.01V to 2V and the frequency of 1Hz to 2MHz, and the virtual ground is equipotential with a negative electrode end of a source generating the sinusoidal voltage waveform.
Further, when an output capacitor test is performed, the test equipment outputs a high current to the other end of the first capacitor, so that the first current output end outputs the high current, the first voltage sampling end samples the output high current to obtain a sampled current, the test equipment provides a virtual ground to the second current output end and the second voltage sampling end, the current return end is in short circuit with the second current output end, and the third voltage sampling end is in short circuit with the second voltage sampling end;
the high current is a sinusoidal voltage waveform with the peak value of 0.01V to 2V and the frequency of 1Hz to 2MHz, and the virtual ground is equipotential with a negative electrode end of a source generating the sinusoidal voltage waveform.
Furthermore, the resistance of the first resistor is 10K omega-100K omega, the inductance value of the first inductor is 100 muH-330 muH, and the capacitance of the first capacitor is 0.1 muF-2.2 muF.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides an impedance test circuit of a field effect transistor wafer, which comprises test equipment and the field effect transistor wafer, wherein the field effect transistor wafer comprises a first field effect transistor and a second field effect transistor which are adjacently arranged, the drain electrode of the first field effect transistor is connected with the drain electrode of the second field effect transistor, the first field effect transistor is provided with a front surface and a back surface which are oppositely arranged, the test equipment is connected with the source electrode and the grid electrode of the first field effect transistor and the source electrode of the second field effect transistor from the front surface side so as to carry out impedance test on the first field effect transistor, and the problems that test data are inaccurate and calibration is difficult to operate due to the fact that wires are long when the drain electrode of the field effect transistor is led out from the back surface side of the wafer are solved.
Drawings
Fig. 1 is a schematic diagram of an impedance testing circuit of a field effect transistor wafer according to an embodiment of the present invention;
fig. 2-4 are circuit diagrams corresponding to parameters tested in the testing apparatus according to an embodiment of the invention.
Detailed Description
The impedance test circuit of a fet wafer according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are each provided with a non-precise ratio for the purpose of facilitating and clearly facilitating the description of the embodiments of the present invention.
Fig. 1 is a schematic diagram of an impedance testing circuit of a field effect transistor wafer according to the present embodiment. As shown in fig. 1, the impedance test circuit of a field effect transistor wafer according to this embodiment performs an impedance test on a field effect transistor in the field effect transistor wafer. The impedance test circuit of the field effect transistor wafer comprises test equipment 10, a voltage source VDC1 and a field effect transistor wafer 20.
The field effect transistor wafer 20 includes a first field effect transistor M1 and a second field effect transistor M2, the second field effect transistor M2 is located near the first field effect transistor M1, and the first field effect transistor M1 and the second field effect transistor M2 are adjacently disposed, wherein the first field effect transistor M1 is a field effect transistor to be tested, and the second field effect transistor M2 is used as a conduction device of a drain electrode D of the first field effect transistor M1. The fet wafer 20 has a front surface and a back surface which are oppositely arranged, the source S and the gate G of the first fet M1 and the source S and the gate G of the second fet M2 are arranged close to the front surface, the drain D of the first fet M1 and the drain D of the second fet M2 are arranged close to the back surface, and the drain D of the first fet M1 and the drain D of the second fet M2 are connected to each other, so that the impedance test circuit 10 only needs to be connected to the source S and the gate G of the first fet M1 and the source S and the gate G of the second fet M2 on the front surface of the fet wafer 20 during testing, and does not need to be connected to the drain D of the first fet M1 or the drain D of the second fet M2 on the back surface, which can solve the problem of inaccurate test drain data caused by long lead wires when the fets are led out from the wafer, and the problem of relatively difficult calibration operation.
The test apparatus 10 includes a first current output terminal CI, a first voltage sampling terminal CV, a second current output terminal BI, a second voltage sampling terminal BV, a current return terminal EI, and a third voltage sampling terminal EV. The gate of the first field effect transistor M1 has a current input terminal BI _1 and a voltage input terminal BV _1, the source of the first field effect transistor M1 has a current input terminal EI _1 and a voltage input terminal EV _1, the gate of the second field effect transistor M2 has a current input terminal BI _2 and a voltage input terminal BV _2, and the source of the second field effect transistor M2 has a current input terminal EI _2 and a voltage input terminal EV _2.
The field effect transistor wafer 20 further includes a first diode D1 and a second diode D2, wherein the anode of the first diode D1 is connected to the source S of the first field effect transistor M1, and the cathode of the first diode D1 is connected to the drain D of the first field effect transistor M1; the anode of the second diode D2 is connected to the source S of the second field effect transistor M2, and the cathode is connected to the drain D of the second field effect transistor M2.
The positive pole of voltage source VDC1 is connected voltage input end BV _2, voltage source VDC 1's negative pole with first voltage sample end CV all connects voltage input end EV _2, first current output end CI connects current input end EI _2, second current output end BI connects current input end BI _1, second voltage sample end BV is connected voltage input end BV _1, current return end EI connects current input end EI _1, third voltage sample end EV connects voltage input end EV _1. Since the connection between the fet wafer 20 and the external structure (i.e., the testing device 10 and the voltage source VDC 1) is performed on the front side of the fet wafer 20, it is not necessary to wind around the back side of the fet wafer 20 to connect the drain D of the fet wafer 20, which shortens the length of the wire, thereby avoiding various influences caused by a long wire.
The test equipment further comprises a first inductor L1, a first capacitor C1, a first resistor R1 and a direct current source VDC, wherein the direct current source VDC is a voltage source for providing direct current bias for the field effect transistor wafer 20. The first resistor R1 has a resistance of 10K Ω to 100K Ω, such as 10K Ω, the first inductor L1 has an inductance of 100 μ H to 330 μ H, such as 330 μ H, and the first capacitor C1 has a capacitance of 0.1 μ F to 2.2 μ F, such as 1 μ H.
Fig. 2 is a circuit diagram corresponding to the test of the impedance Rg and the input capacitance Ciss in the test apparatus of the embodiment. As shown in fig. 2, when performing the impedance Rg test and the input capacitance Ciss test, the dc source VDC is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the first inductor L1, the other end of the first inductor L1 is simultaneously connected to the first current output terminal CI, the first voltage sampling terminal CV and one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the current return terminal EI and is used for short-circuiting a capacitance between a drain and a source of the fet under test at a high frequency, the test apparatus 10 provides a high current HI _ C to the second current output terminal BI, the second voltage sampling terminal BV samples the output high current HI _ C to obtain a sampled current HI _ p, the test apparatus 10 provides a virtual ground LO _ C to the current return terminal, and provides a virtual ground LO _ p to the third voltage sampling terminal EV. The high current HI _ c is a sinusoidal voltage waveform with a peak value of 0.01V to 2V and a frequency of 1Hz to 2MHz, the virtual ground is equal to the potential of the negative electrode end of a source generating the sinusoidal voltage waveform, and the value of the virtual ground is 0V.
Because the input capacitance Ciss test is used for measuring Cgs + Cgd of the first field-effect tube M1, a direct current input is applied to two ends of a source electrode and a drain electrode (namely SD) of the first field-effect tube M1, an alternating current is applied to two ends of a grid electrode and a source electrode (namely GS) of the first field-effect tube M1, alternating voltage and current passing through two ends of the GS of the first field-effect tube M1 are collected, impedance between two ends of the GS of the first field-effect tube M1 is calculated according to the alternating voltage and current at the two ends of the GS of the first field-effect tube M1, and then an impedance imaginary part (namely an input capacitance Ciss) and an impedance real part (namely impedance Rg) are calculated by utilizing a voltage-current phase relation.
Fig. 3 is a circuit diagram corresponding to the testing of the reverse transfer capacitor Crss in the testing apparatus of the present embodiment. As shown in fig. 3, when performing the reverse transfer capacitor Crss test, the dc source VDC is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the first inductor L1, the other end of the first inductor L1 is simultaneously connected to the first current output terminal CI, the first voltage sampling terminal CV and one end of the first capacitor C1, the test apparatus provides a high current HI _ C to the other end of the first capacitor C1, so that the first current output terminal outputs the high current HI _ C, the first voltage sampling terminal samples the output high current to obtain a sampled current HI _ p, the test apparatus provides a virtual ground LO _ C to the second current output terminal BI, provides a virtual ground LO _ p to the second voltage sampling terminal BV, and the current return terminal and the third voltage sampling terminal EV are grounded GND.
The reverse transmission capacitor Crss test is used for measuring the Cdg of the first field effect transistor M1, a direct current input is applied to two ends of a drain electrode and a grid electrode (namely DG) of the first field effect transistor M1, an alternating current is applied to two ends of the drain electrode and the grid electrode (namely DG) of the first field effect transistor M1, an alternating voltage and an alternating current passing through two ends of the DG of the first field effect transistor M1 are collected, the impedance between two ends of the DG of the first field effect transistor M1 is calculated according to the alternating voltage and the alternating current at the two ends of the DG of the first field effect transistor M1, and then an impedance imaginary part (namely the reverse transmission capacitor Crss) is calculated by using a voltage-current phase relation.
Fig. 4 is a circuit diagram corresponding to the output capacitance Coss test in the test equipment of the embodiment. As shown in fig. 4, when performing an output capacitance Coss test, the dc source VDC is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the first inductor L1, the other end of the first inductor L1 is simultaneously connected to the first current output terminal CI, a first voltage sampling terminal CV and one end of the first capacitor C1, the test apparatus provides a high current HI _ C to the other end of the first capacitor C1, so that the first current output terminal CI outputs the high current HI _ C, the first voltage sampling terminal CV samples the output high current and obtains a sampled current HI _ p, the test apparatus provides a virtual ground LO _ C to the second current output terminal BI, provides a virtual ground LO _ p to the second voltage sampling terminal BV, the current return terminal is shorted to the second current output terminal EI, and the third voltage sampling terminal EV is shorted to the second voltage sampling terminal BV, wherein the short is used for shorting the capacitor between the gate and the source of the fet under test.
The output capacitance Coss test is used for measuring the Cds + Cdg of the first field effect tube M1, a direct current input is applied to two ends of a drain electrode and a source electrode (namely DS) of the first field effect tube M1, an alternating current is applied to two ends of the DS of the first field effect tube M1, alternating voltage and current passing through two ends of the DS of the first field effect tube M1 are collected, impedance between two ends of the DS of the first field effect tube M1 is calculated according to the alternating voltage and current at the two ends of the DS of the first field effect tube M1, and an imaginary impedance part (namely an output capacitance Coss) is calculated by utilizing a voltage-current phase relation.
Compared with the traditional load calibration scheme or the testing method of connecting the long wire to the probe station chassis, the impedance testing circuit of the embodiment skillfully conducts a field effect tube (namely a conducting device) on a field effect tube wafer with a tested field effect tube, and conducts the drain electrode of the tested field effect tube with the first current output end CI and the first voltage sampling end CV of the testing equipment through the conducting device, so that the problem of overlong chassis lead wire from the probe station is solved, direct testing can be realized without calibration such as load, and the like, thereby realizing simple operation and higher precision.
In summary, the impedance test circuit of the field effect transistor wafer provided by the invention has the advantages that through hardware improvement, the test line is shortened, the test operation is simplified, and the test equipment can simply, directly and accurately test various impedances of the field effect transistor. Particularly, the required parameters can be measured without additionally adding probes on the probe card, so that the test is greatly facilitated, the cost is saved, and the production efficiency of a production line is improved.
In addition, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification are only used for distinguishing various components, elements, steps and the like in the specification, and are not used for representing logical relationships, sequence relationships or the like between the various components, elements, steps.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are within the scope of the technical solution of the present invention, unless the technical essence of the present invention is not departed from the content of the technical solution of the present invention.
Claims (9)
1. An impedance test circuit of a field effect transistor wafer is characterized by comprising test equipment and the field effect transistor wafer, wherein the field effect transistor wafer comprises a first field effect transistor and a second field effect transistor which are arranged adjacently, a drain electrode of the first field effect transistor is connected with a drain electrode of the second field effect transistor, the first field effect transistor is provided with a front surface and a back surface which are arranged oppositely, and the test equipment is connected with a source electrode and a grid electrode of the first field effect transistor and a source electrode of the second field effect transistor from the front surface side so as to carry out impedance test on the first field effect transistor;
the test equipment comprises a first current output end, a first voltage sampling end, a second current output end, a second voltage sampling end, a current return end and a third voltage sampling end;
the grid electrode and the source electrode of the first field effect transistor are respectively provided with a current input end and a voltage input end, and the grid electrode and the source electrode of the second field effect transistor are respectively provided with a current input end and a voltage input end;
the first current output end is connected with a current input end of a source electrode of the second field effect transistor, the second current output end is connected with a current input end of a grid electrode of the first field effect transistor, the second voltage sampling end is connected with a voltage input end of the grid electrode of the first field effect transistor, the current return end is connected with a current input end of the source electrode of the first field effect transistor, and the third voltage sampling end is connected with a voltage input end of the source electrode of the first field effect transistor.
2. The impedance testing circuit of a field effect transistor wafer of claim 1, wherein a source and a gate of the first field effect transistor and a source and a gate of the second field effect transistor are disposed proximate the front side, and a drain of the first field effect transistor and a drain of the second field effect transistor are disposed proximate the back side.
3. The impedance testing circuit of claim 1, wherein the fet wafer further comprises a first diode and a second diode, wherein an anode of the first diode is connected to the source of the first fet and a cathode of the first diode is connected to the drain of the first fet; the anode of the second diode is connected with the source electrode of the second field effect transistor, and the cathode of the second diode is connected with the drain electrode of the second field effect transistor.
4. The impedance testing circuit of claim 1, further comprising a voltage source, wherein an anode of the voltage source is connected to the voltage input terminal of the gate of the second fet, and wherein a cathode of the voltage source and the first voltage sampling terminal are both connected to the voltage input terminal of the source of the second fet.
5. The impedance testing circuit of a field effect transistor wafer of claim 1, wherein the testing device further comprises a first inductor, a first capacitor, a first resistor, and a dc source, wherein one end of the first resistor is connected to the dc source, the other end of the first resistor is connected to one end of the first inductor, and the other end of the first inductor is connected to the first current output terminal, the first voltage sampling terminal, and one end of the first capacitor.
6. The impedance test circuit of a field effect transistor wafer as claimed in claim 5, wherein, during the impedance test and the input capacitance test, the other end of the first capacitor is connected to the current return terminal and is used for short-circuiting the capacitor between the drain and the source of the field effect transistor under test at high frequency, the test device provides high current to the second current output terminal, the second voltage sampling terminal samples the output high current to obtain a sampled current, and the test device provides a virtual ground to the current return terminal and the third voltage sampling terminal;
the high current is a sinusoidal voltage waveform with the peak value of 0.01V to 2V and the frequency of 1Hz to 2MHz, and the virtual ground is equipotential with a negative electrode end of a source generating the sinusoidal voltage waveform.
7. The impedance testing circuit of a field effect transistor wafer of claim 5, wherein when performing a reverse transmission capacitance test, the testing device provides a high current to the other end of the first capacitor, such that the first current output terminal outputs the high current, the first voltage sampling terminal samples the output high current and obtains a sampled current, the testing device provides a virtual ground to the second current output terminal and the second voltage sampling terminal, and the current return terminal and the third voltage sampling terminal are grounded;
the high current is a sine voltage waveform with the peak value of 0.01V to 2V and the frequency of 1Hz to 2MHz, and the virtual ground is equipotential with a negative electrode end of a source generating the sine voltage waveform.
8. The impedance test circuit of the FET wafer of claim 5, wherein when performing an output capacitance test, the test equipment outputs a high current to the other end of the first capacitor, such that the first current output terminal outputs the high current, the first voltage sampling terminal samples the output high current and obtains a sampled current, the test equipment provides a virtual ground to the second current output terminal and the second voltage sampling terminal, the current return terminal is shorted to the second current output terminal, and the third voltage sampling terminal is shorted to the second voltage sampling terminal;
the high current is a sinusoidal voltage waveform with the peak value of 0.01V to 2V and the frequency of 1Hz to 2MHz, and the virtual ground is equipotential with a negative electrode end of a source generating the sinusoidal voltage waveform.
9. The impedance testing circuit of claim 5, wherein the first resistor has a resistance of 10K Ω to 100K Ω, the first inductor has an inductance of 100 μ H to 330 μ H, and the first capacitor has a capacitance of 0.1 μ F to 2.2 μ F.
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| US8183892B2 (en) * | 2009-06-05 | 2012-05-22 | Fairchild Semiconductor Corporation | Monolithic low impedance dual gate current sense MOSFET |
| CN102128989B (en) * | 2011-01-27 | 2013-04-24 | 广州金升阳科技有限公司 | Field effect transistor input/output capacitance measurement circuit and measurement method thereof |
| CN105445635B (en) * | 2014-07-29 | 2017-05-17 | 华润赛美科微电子(深圳)有限公司 | Metal oxide semiconductor field effect transistor on-resistance measuring method |
| CN104375074B (en) * | 2014-11-27 | 2018-02-27 | 山东贞明半导体技术有限公司 | A kind of test circuit of FET |
| CN107345996B (en) * | 2017-07-11 | 2023-08-22 | 北京华峰测控技术有限公司 | Field effect transistor test circuit and test method |
| US10782334B2 (en) * | 2017-08-16 | 2020-09-22 | Infineon Technologies Ag | Testing MOS power switches |
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