CN115642902A - Sampling clock delay phase determining method, device and system and storage medium - Google Patents
Sampling clock delay phase determining method, device and system and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a method, a device and a system for determining a delay phase of a sampling clock and a storage medium. The sampling clock delay phase determination method includes, for example: acquiring a reference clock signal and a low-voltage differential signal sent by sending end equipment; converting the low-voltage differential signal to obtain a single-ended signal; performing delay processing on the single-ended signal according to the current phase to obtain serial data; buffering the reference clock signal to obtain a high-speed sampling clock signal; converting the serial data according to the high-speed sampling clock signal to obtain parallel data; determining a target delay phase of the delay process from the current phase, the reference clock signal, and the parallel data. The embodiment of the invention can automatically find the best adopted clock delay phase of the data in an automatic cycle training mode, and has high reliability.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method, an apparatus, a system, and a storage medium for determining a delay phase of a sampling clock.
Background
For the recovery of high-speed data, a clock is needed to sample the data, if the data is sampled by double edges, the data is stable when the rising edge and the falling edge of the clock need to be ensured, and if the data is at a change boundary, a data sampling error code is caused. The traditional LVDS data transmission usually includes one channel associated clock plus several data channels, one clock channel is added physically, the complexity of the peripheral circuit is increased, and the time delay of the clock channel or the data channel needs to be adjusted manually to ensure the correctness of reading and writing data, which is not flexible and reliable enough. In addition, under the condition of no associated clock, the traditional LVDS data transmission needs to sample data by using clocks with 4 phases (0 degree, 90 degrees, 180 degrees, 270 degrees), or oversample the data by using clocks with several times of the speed of a data channel to recover the data.
Disclosure of Invention
Therefore, in view of the technical problems in the prior art, embodiments of the present invention provide a sampling clock delay phase determining method, a sampling clock delay phase determining apparatus, a sampling clock delay phase determining system, and a storage medium, which can automatically find an optimal sampling clock delay phase of data in an automatic cycle training manner, and have high reliability.
In one aspect, a method for determining a delay phase of a sampling clock according to an embodiment of the present invention includes: acquiring a reference clock signal and a low-voltage differential signal sent by sending end equipment; converting the low-voltage differential signal to obtain a single-ended signal; performing delay processing on the single-ended signal according to the current phase to obtain serial data; buffering the reference clock signal to obtain a high-speed sampling clock signal; converting the serial data according to the high-speed sampling clock signal to obtain parallel data; determining a target delay phase of the delay process from the current phase, the reference clock signal, and the parallel data.
In one embodiment of the present invention, the determining a target delay phase of the delay process according to the current phase, the reference clock signal, and the parallel data comprises: carrying out frequency reduction processing on the reference clock signal to obtain a parallel data clock signal; determining a plurality of delay phase ranges from the current phase, the parallel data clock signal, and the parallel data; and determining the target retard phase from the plurality of retard phase ranges.
In one embodiment of the invention, determining a plurality of delay phase ranges from the current phase, the parallel data clock signal, and the parallel data comprises: respectively acquiring first parallel data and second parallel data in the current phase in two adjacent parallel data clock signal periods, combining the first parallel data and the second parallel data to obtain a first group of merged data, comparing the first group of merged data with reference data to obtain a first comparison result, and adding 1 to the count of the number value of the correct phase when the first comparison result shows that the current phase is correct; repeating until the number value of the correct phase reaches a first threshold value, adjusting the current phase according to the phase adjustment step length to obtain a first adjustment phase, and clearing the number value of the correct phase; and taking the first adjusting phase as the current phase, and repeating the previous two steps until a cycle ending instruction is received to obtain a plurality of delay phase ranges including the first adjusting phase.
In one embodiment of the present invention, the determining the target delay phase from the plurality of delay phase ranges comprises: acquiring the maximum delay phase and the minimum delay phase of the delay phase range with the maximum width of the plurality of delay phase ranges; and determining the target delay phase according to the maximum delay phase and the minimum delay phase.
On the other hand, a sampling clock delay phase determining apparatus provided in an embodiment of the present invention includes, for example: the signal acquisition module is used for acquiring a reference clock signal and a low-voltage differential signal sent by the sending end equipment; the first signal conversion module is used for converting the low-voltage differential signal to obtain a single-ended signal; the delay processing module is used for carrying out delay processing on the single-ended signal to obtain serial data; the buffer processing module is used for carrying out buffer processing on the reference clock signal to obtain a high-speed sampling clock signal; the second signal conversion acquisition module is used for converting the serial data according to the high-speed sampling clock signal to obtain parallel data; a phase determination module for determining a target delay phase of the delay process according to the reference clock signal and the parallel data.
In one embodiment of the present invention, the phase determining means includes: the parallel signal determining unit is used for carrying out frequency reduction processing on the reference clock signal to obtain a parallel data clock signal; a phase range determination unit for determining a plurality of delay phase ranges from the parallel data clock signal and the parallel data; and a target phase determination unit for determining the target delay phase from the plurality of delay phase ranges.
In one embodiment of the present invention, the phase range determination unit includes: the phase adjustment determining subunit is used for respectively acquiring first parallel data and second parallel data in the current phase in two adjacent parallel data clock signal periods, combining the first parallel data and the second parallel data to obtain a first group of combined data, comparing the first group of combined data with reference data to obtain a first comparison result, and adding 1 to the number value count of the correct phase when the first comparison result shows that the current phase is correct; repeating until the number value of the correct phase reaches a first threshold value, adjusting the current phase according to the phase adjustment step length to obtain a first adjustment phase, and clearing the number value of the correct phase; and the phase range determining subunit is used for repeating the previous step by taking the first adjusting phase as the current phase until a cycle ending instruction is received, so as to obtain a plurality of delay phase ranges including the first adjusting phase.
In one embodiment of the present invention, the target phase determination unit includes: a phase boundary determining subunit, configured to acquire a maximum delay phase and a minimum delay phase of a delay phase range with a maximum width of the plurality of delay phase ranges; and a target phase determining subunit configured to determine the target delay phase according to the maximum delay phase and the minimum delay phase.
In another aspect, a sampling clock delay phase determining system provided in an embodiment of the present invention includes: a processor and a memory coupled to the processor; wherein the memory stores instructions for execution by the processor and the instructions cause the processor to perform operations to perform a sampling clock delay phase determination method as described in any one of the preceding.
In yet another aspect, an embodiment of the present invention provides a storage medium, which is a non-volatile memory and stores a computer program, where the computer program is used to execute the sampling clock delay phase determination method according to any one of the preceding claims.
As can be seen from the above, the above technical solutions of the present invention may have one or more of the following advantages: according to the sampling clock delay phase determining method provided by the embodiment of the invention, the target delay phase of the data is automatically determined according to the current phase, the reference clock signal and the parallel data, so that the optimal adopted phase is obtained. In addition, the complexity and the circuit of the clock system are simplified, and the reliability of the system is increased.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for determining a delay phase of a sampling clock according to a first embodiment of the present invention.
Fig. 2 is a detailed flowchart of step S60 shown in fig. 1.
Fig. 3 is a detailed flowchart of step S630 shown in fig. 2.
Fig. 4 is a detailed flowchart of step S650 shown in fig. 2.
Fig. 5 is a schematic structural diagram of a programmable logic device according to a first embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating a state flow of the phase determining unit in fig. 5.
Fig. 7 is a schematic structural diagram of a sampling clock delay phase determining apparatus according to a second embodiment of the present invention.
Fig. 8 is a schematic structural diagram of the phase determination module shown in fig. 7.
Fig. 9 is a schematic structural diagram of the phase range determining unit shown in fig. 8.
Fig. 10 is a schematic configuration diagram of the target phase determining unit shown in fig. 8.
Fig. 11 is a schematic structural diagram of a sampling clock delay phase determining system according to a third embodiment of the present invention.
Fig. 12 is a schematic structural diagram of a storage medium according to a fourth embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a sampling clock delay phase determination method. Specifically, the sampling clock delay phase determination method includes, for example, the steps of:
s10: acquiring a reference clock signal and a low-voltage differential signal sent by sending end equipment;
s20: converting the low-voltage differential signal to obtain a single-ended signal;
s30: performing delay processing on the single-ended signal according to the current phase to obtain serial data;
s40: buffering the reference clock signal to obtain a high-speed sampling clock signal;
s50: converting the serial data according to the high-speed sampling clock signal to obtain parallel data;
s60: determining a target delay phase of the delay process from the current phase, the reference clock signal, and the parallel data.
According to the sampling clock delay phase determining method provided by the embodiment of the invention, the target delay phase of the data is automatically determined according to the current phase, the reference clock signal and the parallel data, so that the optimal adopted phase is obtained. In addition, the complexity and the circuit of the clock system are simplified, and the reliability of the system is increased.
Specifically, as shown in fig. 2, step S60 includes, for example:
s610: carrying out frequency reduction processing on the reference clock signal to obtain a parallel data clock signal;
s630: determining a plurality of delay phase ranges from the current phase, the parallel data clock signal, and the parallel data; and
s650: determining the target delay phase from the plurality of delay phase ranges.
Further, as shown in fig. 3, step S630 includes, for example, the steps of:
s631: respectively acquiring first parallel data and second parallel data in the current phase in two adjacent parallel data clock signal periods, combining the first parallel data and the second parallel data to obtain a first group of merged data, comparing the first group of merged data with reference data to obtain a first comparison result, and adding 1 to the count of the number value of the correct phase when the first comparison result shows that the current phase is correct; repeating until the number value of the correct phase reaches a first threshold value, adjusting the current phase according to the phase adjustment step length to obtain a first adjustment phase, and clearing the number value of the correct phase;
s633: and taking the first adjusting phase as the current phase, and repeating the previous two steps until a cycle ending instruction is received to obtain a plurality of delay phase ranges including the first adjusting phase.
Specifically, as shown in fig. 4, step S650 specifically includes:
s651: acquiring the maximum delay phase and the minimum delay phase of the delay phase range with the maximum width of the plurality of delay phase ranges;
s653: and determining the target delay phase according to the maximum delay phase and the minimum delay phase.
For the convenience of understanding the present invention, the sampling clock delay phase determination method of the present embodiment will be described in detail below with reference to fig. 5 to 6.
The method for determining the delay phase of the sampling clock provided by the embodiment of the invention is suitable for a receiving module of a Low-Voltage Differential Signaling (LVDS) in a programmable logic device, for example. The Programmable Logic Device is, for example, an FPGA (Field-Programmable Gate Array) or a CPLD (Complex Programmable Logic Device). Specifically, as shown in fig. 5, the programmable logic device includes, for example, a data processing module and a receiving module. The receiving module is used for receiving the low-voltage differential signals such as LVDS signals, performing serial-parallel conversion on the low-voltage differential signals to obtain parallel data, and transmitting the parallel data to the data processing module so that the data processing module can further process the parallel data.
Further, the receiving module includes, for example, a Phase Locked Loop (PLL), a clock dividing unit (iocldiv), a clock buffering unit (ioclduf), a phase determining unit (iddelay _ transmitting), a single-ended signal converting unit (inbufds), a delay unit (IODELAY), a serial-to-parallel converting unit (ISERDES), and the like. The following describes a sampling clock delay phase determination method according to the present embodiment.
Firstly, a single-ended signal conversion unit of a receiving module of the programmable logic device acquires low-voltage differential signals data _ p _ i and data _ n _ i sent by a generating terminal device. In addition, the phase-locking unit of the receiving module obtains a reference clock signal ref _ clk which is input externally. The reference clock ref _ clk needs to be homologous with the clock of the sending end device, so that frequency deviation between the receiving module and the sending end device is avoided.
And the single-ended signal conversion unit converts the low-voltage differential signals data _ p _ i and data _ n _ i to obtain a single-ended signal data _ in. A single-ended signal is a signal expressed in terms of a change in voltage to ground, for example, with "ground" as a reference point. The single-ended signal conversion unit is, for example, a signal conversion module in the prior art, and is not described herein again.
And the delay unit carries out delay processing on the single-ended signal data _ in according to the current phase to obtain serial data _ in _ dly. By configuring different step parameters, the delay amount, i.e. the delay phase, of the output signal of the delay unit relative to the input signal can be adjusted. The output signal and the input signal of the delay unit have the same frequency and are delayed only in phase. The delay unit may dynamically adjust a phase difference of the input signal and the output signal through the external port. For example, the adjustable number of steps of the delay unit is 247 steps, each step being about 10ps.
The phase locking unit configures the frequency of the output clock signal hs _ clk to be 1/2 of the data rate of the low-voltage differential signal transmitted by the transmitting terminal device according to the reference clock signal. The clock frequency division unit divides the frequency of the output clock signal hs _ clk by 5 to obtain a parallel data clock signal byte _ clk. The clock buffer unit buffers the output clock signal hs _ clk of the phase lock unit to obtain a high-speed sampling clock signal ioclk.
The serial-parallel conversion unit converts the serial data _ in _ dly according to the high-speed sampling clock signal ioclk to obtain parallel data rx _ data [ 9. Specifically, the serial data _ in _ dly is subjected to double edge sampling by a high-speed sampling clock signal ioclk clock, converted into 10-bit parallel data rx _ data, and synchronized to a clock domain of a low-speed parallel clock signal byte _ clk.
A phase determination unit determines a target delay phase of the delay process from the current phase, the reference clock signal, and the parallel data. The target delay phase is the optimal delay phase of the delay processing unit.
Further, referring to fig. 6, a state flow diagram of the phase determination unit (IODELAY _ traveling) is shown.
Specifically, first, the transmitting-end device transmits a continuous segment of the comma code pattern as the byte boundary alignment pattern of the receiving end at idle or at power-up initialization. The 10-bit code pattern 0011111010 is taken as an example of the comma code, and the comma code can be reconfigured through parameters. The transmitting device cycles 0011111010 or its complement 1100000101 at idle or power-up initialization. The comma code or its complement is, for example, reference data. The configuration parameter ONE LOOP TIME is 1000 TIMES, and the total LOOP TIME is 5 TIMES. Other circuit parameters may be reconfigured by user configuration. The number of data channels is reconstructed through parameter configuration, each channel is independent, and this embodiment is described by taking 1 channel as an example.
At system initialization, the phase determination unit enters an IDLE state (IDLE). When the phase determining unit detects that the start _ train signal is at a high level, starting to enter an automatic training process (namely, a phase determining process);
then entering a FIND _ COMMA state, each byte _ clk of the phase determination unit receives 1 rx _ data of 10 bits, and 2 byte _ clk of the phase determination unit receives 2 parallel data (first parallel data and second parallel data) of 10 bits. Then, the phase determining unit splices (also called combines) 2 10-bit data into 1 20-bit data (i.e. combined parallel data), and judges whether a 10-bit comma code or its complement can be framed in the 20-bit data, i.e. the 20-bit data is compared with the comma code. For example, two adjacent 10-bit data are 1111101000 and 0011110000, respectively, the lower two bits (00) of the 2 nd 10-bit data and the upper 8 bits (11111010) of the first 10-bit data may be combined into a 10-bit comma code (0011111010) to indicate the data transmitted, where a comma code can be framed from the code stream of 20 bits to indicate that the receiving module can correctly recover the data transmitted by the transmitting end device. If so, then enter the LOOP _ FIND1 state and LOOP _ cnt1 is incremented by 1; if not, the sampling of the parallel data by the current high-speed sampling clock is error-coded, and a PHASE _ ADJ state is entered for PHASE adjustment.
When in the LOOP _ FIND1 state, if the counter LOOP _ cnt1 is equal to 1000, it means that 1000 COMMA codes are found, the counter LOOP _ cnt2 is incremented by 1, and the LOOP _ FIND2 state is entered, and if the counter LOOP _ cnt1 is not equal to 1000, the LOOP _ COMMA state is entered to continue to FIND the COMMA codes.
When the counter LOOP _ cnt1 clears 0 in the LOOP _ FIND2 state, and if the counter LOOP _ cnt2 is equal to 5, it indicates that 5 × 1000 comma codes are found in this PHASE, that is, the number of correct PHASEs reaches 5000 (the first threshold), that is, the current PHASE is considered to be correct, and the PHASE _ ADJ state is entered. If the counter loop _ cnt2 is not equal to 5, the FIND _ COMMA state is entered to continue looking for the COMMA code.
When in the PHASE _ ADJ state, the counter loop _ cnt2 clears 0, the delay unit is adjusted by 5 steps (each step is about 10ps,5 steps are about 50 ps), that is, the PHASE adjustment step, i.e., the PHASE difference between the high-speed clocks ioclk and data _ in, is adjusted by 50ps. After 5 steps are adjusted, the TRAIN _ END state is entered. Wherein, the delay unit can adjust 247step at most.
When the TRAIN _ END state is in the TRAIN _ END state, whether the boundary _ END signal is in a high level is judged, and the high level indicates that the training is finished, namely whether a cycle END command is received. The premise that boundary _ end is high is: two consecutive phases are found or the delay value of the IODELAY unit has been adjusted to a maximum value (247 step).
When receiving a loop end command, the phase determination unit finds all correct phase values, i.e. multiple phase ranges, or multiple phase windows. And calculating a target sampling phase, namely an optimal sampling phase according to the plurality of delay phase ranges so as to be used for data sampling of the whole system. If low, i.e., no end of loop command is received, the FIND _ COMMA state is entered. The precondition for judging the sampling correct phase is that 5 × 1000 comma codes or the complement thereof can be found continuously, and the condition for judging the sampling phase as error is that no comma code or the complement thereof can be found in 2 byte _ clk.
The calculation method of the target phase or the optimal phase comprises the following steps: the maximum intermediate value of the consecutive correct windows is taken as the optimal IODELAY cell delay value. For example, assuming that steps 0 to 30 are correct phases, steps 31 to 49 are error phases, and steps 50 to 100 are correct phases, step50 to 100 is regarded as the largest continuous correct window, or is the delay phase range with the largest width, and (50 + 100)/2 =75 is taken as the optimal delay phase of the IODELAY unit, that is, the maximum delay phase and the minimum delay phase are weighted and the optimal delay phase is obtained, so that the data sampling by the clock is correct and reliable.
In summary, the sampling clock delay phase determining method provided in the embodiment of the present invention automatically determines the target delay phase of the data according to the current phase, the reference clock signal, and the parallel data, so as to obtain the optimal sampling phase. In addition, the complexity and the circuit of the clock system are simplified, and the system reliability is increased.
As shown in fig. 7, a second embodiment of the present invention provides a sampling clock delay phase determining apparatus 10. The sampling clock delay phase determination apparatus 10 includes, for example, a signal acquisition module 100, a first signal conversion module 200, a delay processing module 300, a buffer processing module 400, a second signal conversion acquisition module 500, and a phase determination module 600.
Specifically, the signal obtaining module 100 is configured to obtain a reference clock signal and a low voltage differential signal sent by a sending end device; the first signal conversion module 200 is configured to perform conversion processing on the low-voltage differential signal to obtain a single-ended signal; the delay processing module 300 is configured to perform delay processing on the single-ended signal to obtain serial data; the buffer processing module 400 is configured to perform buffer processing on the reference clock signal to obtain a high-speed sampling clock signal; the second signal conversion obtaining module 500 is configured to convert the serial data according to the high-speed sampling clock signal to obtain parallel data; the phase determination module 600 is configured to determine a target delay phase of the delay process according to the reference clock signal and the parallel data.
Further, as shown in fig. 8, the model building and training module 60 includes: a parallel signal determination unit 610, a phase range determination unit 630 and a target phase determination unit 650. The parallel signal determining unit 610 is configured to perform frequency reduction on the reference clock signal to obtain a parallel data clock signal; a phase range determination unit 630 for determining a plurality of delay phase ranges from the parallel data clock signal and the parallel data; and a target phase determination unit 650 for determining the target retard phase from the plurality of retard phase ranges.
Further, as shown in fig. 9, the phase range determining unit 630 further includes: an adjustment phase determining sub-unit 631 and a phase range determining sub-unit 633. Specifically, the adjusted phase determining subunit 631 is configured to obtain first parallel data and second parallel data in the current phase in two adjacent parallel data clock signal periods, combine the first parallel data and the second parallel data to obtain a first set of merged data, compare the first set of merged data with reference data to obtain a first comparison result, and add 1 to the count of the number value of the correct phase when the first comparison result indicates that the current phase is correct; repeating until the number value of the correct phase reaches a first threshold value, adjusting the current phase according to the phase adjustment step length to obtain a first adjustment phase, and clearing the number value of the correct phase; the phase range determining subunit 633 is configured to repeat the previous steps with the first adjusted phase as a current phase until a loop end instruction is received, and obtain a plurality of delay phase ranges including the first adjusted phase.
In addition, as shown in fig. 10, the target phase determination unit 650 includes: a phase boundary determining sub-unit 651 and a target phase determining sub-unit 653. Wherein, the phase boundary determining subunit 651 is configured to obtain a maximum delay phase and a minimum delay phase of the delay phase range with the largest width of the plurality of delay phase ranges; the target phase determining sub-unit 653 is configured to determine the target delay phase according to the maximum delay phase and the minimum delay phase.
For the specific working process and technical effect of each module in the sampling clock delay phase determining apparatus 10 in this embodiment, reference is made to the description of the related steps in the foregoing first embodiment, and details are not repeated here.
As shown in fig. 11, a third embodiment of the present invention provides a sampling clock delay phase determination system 20. The sampling clock delay phase determination system 20 includes, for example, a memory 22 and a processor 21 connected to the memory 22. The memory 22 may be, for example, a non-volatile memory having instructions stored thereon. The processor 21 may for example comprise an embedded processor or a central processor or the like. The processor 21 executes the instructions to perform the sampling clock delay phase determination method provided in the foregoing first embodiment.
As shown in fig. 12, a fourth embodiment of the present invention provides a storage medium 30 storing a computer program for executing the sampling clock delay phase determining method according to the foregoing first embodiment. The storage medium 30 is, for example, a nonvolatile memory, such as including: magnetic media (e.g., hard disks, floppy disks, and magnetic tape), optical media (e.g., cd ROM disks and DVDs), magneto-optical media (e.g., optical disks), and hardware devices specially constructed for storing and executing computer-executable instructions (e.g., read Only Memories (ROMs), random Access Memories (RAMs), flash memories, etc.). The storage medium 30 may execute a computer program by one or more processors or processing devices.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and technical solutions of the embodiments may be arbitrarily combined and used without departing from the scope of the present invention.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for sample clock delay phase determination, comprising:
acquiring a reference clock signal and a low-voltage differential signal sent by sending end equipment;
converting the low-voltage differential signal to obtain a single-ended signal;
performing delay processing on the single-ended signal according to the current phase to obtain serial data;
buffering the reference clock signal to obtain a high-speed sampling clock signal;
converting the serial data according to the high-speed sampling clock signal to obtain parallel data;
determining a target delay phase of the delay process from the current phase, the reference clock signal, and the parallel data.
2. The sampling clock delay phase method of claim 1, wherein the determining a target delay phase for the delay process from the current phase, the reference clock signal, and the parallel data comprises:
carrying out frequency reduction processing on the reference clock signal to obtain a parallel data clock signal;
determining a plurality of delay phase ranges from the current phase, the parallel data clock signal, and the parallel data; and
determining the target retard phase from the plurality of retard phase ranges.
3. The sampling clock delay phase determination method of claim 2, wherein determining a plurality of delay phase ranges from the current phase, the parallel data clock signal, and the parallel data comprises:
respectively acquiring first parallel data and second parallel data in the current phase in two adjacent parallel data clock signal periods, combining the first parallel data and the second parallel data to obtain a first group of merged data, comparing the first group of merged data with reference data to obtain a first comparison result, and adding 1 to the count of the number value of the correct phase when the first comparison result shows that the current phase is correct; repeating until the number value of the correct phase reaches a first threshold value, adjusting the current phase according to the phase adjustment step length to obtain a first adjustment phase, and clearing the number value of the correct phase;
and taking the first adjusting phase as the current phase, and repeating the first two steps until a loop ending instruction is received to obtain a plurality of delay phase ranges including the first adjusting phase.
4. The sampling clock delay phase determination method of claim 2, wherein the determining the target delay phase from the plurality of delay phase ranges comprises:
acquiring the maximum delay phase and the minimum delay phase of the delay phase range with the maximum width of the plurality of delay phase ranges; and
and determining the target delay phase according to the maximum delay phase and the minimum delay phase.
5. A sampling clock delay phase determination apparatus, comprising:
the signal acquisition module is used for acquiring a reference clock signal and a low-voltage differential signal sent by the sending end equipment;
the first signal conversion module is used for carrying out conversion processing on the low-voltage differential signal to obtain a single-ended signal;
the delay processing module is used for carrying out delay processing on the single-ended signal to obtain serial data;
the buffer processing module is used for carrying out buffer processing on the reference clock signal to obtain a high-speed sampling clock signal;
the second signal conversion acquisition module is used for converting the serial data according to the high-speed sampling clock signal to obtain parallel data;
a phase determination module for determining a target delay phase of the delay process according to the reference clock signal and the parallel data.
6. The sampling clock delay phase determination apparatus of claim 5, wherein the phase determination apparatus comprises:
the parallel signal determining unit is used for carrying out frequency reduction processing on the reference clock signal to obtain a parallel data clock signal;
a phase range determination unit for determining a plurality of delay phase ranges from the parallel data clock signal and the parallel data; and
a target phase determination unit for determining the target delay phase from the plurality of delay phase ranges.
7. The sampling clock delay phase determination apparatus of claim 6, wherein the phase range determination unit comprises:
the phase adjustment determining subunit is used for respectively acquiring first parallel data and second parallel data in the current phase in two adjacent parallel data clock signal periods, combining the first parallel data and the second parallel data to obtain a first group of combined data, comparing the first group of combined data with reference data to obtain a first comparison result, and adding 1 to the number value count of the correct phase when the first comparison result shows that the current phase is correct; repeating until the number value of the correct phase reaches a first threshold value, adjusting the current phase according to the phase adjustment step length to obtain a first adjustment phase, and clearing the number value of the correct phase;
and the phase range determining subunit is used for taking the first adjusting phase as the current phase, repeating the previous step until a loop ending instruction is received, and obtaining a plurality of delay phase ranges including the first adjusting phase.
8. The sampling clock delay phase determination apparatus of claim 6, wherein the target phase determination unit comprises:
a phase boundary determining subunit, configured to acquire a maximum delay phase and a minimum delay phase of a delay phase range having a maximum delay phase range width; and
and the target phase determining subunit is used for determining the target delay phase according to the maximum delay phase and the minimum delay phase.
9. A sampling clock delay phase determination system, comprising: a processor and a memory coupled to the processor; wherein the memory stores instructions for execution by the processor and the instructions cause the processor to perform operations to perform the method of sample clock delay phase determination of any of claims 1 to 5.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium is a non-volatile memory and stores a computer program for executing the sampling clock delay phase determination method according to any one of claims 1 to 5.
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| CN202211414796.6A CN115642902A (en) | 2022-11-11 | 2022-11-11 | Sampling clock delay phase determining method, device and system and storage medium |
| PCT/CN2023/117518 WO2024098932A1 (en) | 2022-11-11 | 2023-09-07 | Sampling clock delay phase determination method, apparatus and system, and storage medium |
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| CN202211414796.6A CN115642902A (en) | 2022-11-11 | 2022-11-11 | Sampling clock delay phase determining method, device and system and storage medium |
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Cited By (5)
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| CN116055927A (en) * | 2023-04-03 | 2023-05-02 | 深圳市紫光同创电子有限公司 | Data double oversampling method, system, equipment and storage medium |
| CN116954306A (en) * | 2023-09-20 | 2023-10-27 | 芯动微电子科技(珠海)有限公司 | Clock phase shifting method and device |
| CN117076372A (en) * | 2023-10-12 | 2023-11-17 | 北京华峰测控技术股份有限公司 | Communication signal receiving interface circuit and communication method |
| CN117590897A (en) * | 2023-11-23 | 2024-02-23 | 北京国科天迅科技股份有限公司 | Chip and chip control method |
| WO2024098932A1 (en) * | 2022-11-11 | 2024-05-16 | 深圳市紫光同创电子有限公司 | Sampling clock delay phase determination method, apparatus and system, and storage medium |
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| CN118694508A (en) * | 2024-08-23 | 2024-09-24 | 中科亿海微电子科技（苏州）有限公司 | Serial data receiving and recovering method, computer readable storage medium and electronic equipment |
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| JP3581584B2 (en) * | 1998-12-07 | 2004-10-27 | 株式会社日立製作所 | Delay amount correction circuit, ATM exchange, and delay amount correction method |
| JP6241156B2 (en) * | 2013-09-11 | 2017-12-06 | 株式会社ソシオネクスト | Method for determining the phase of a clock used to receive parallel data, a receiving circuit and an electronic device |
| CN104378114B (en) * | 2014-10-23 | 2017-12-22 | 西安电子科技大学 | A kind of method for realizing that multipath A/D converter is synchronous |
| CN206711081U (en) * | 2017-04-07 | 2017-12-05 | 华中师范大学 | A kind of multi-channel high-speed serial data collection system based on simultaneous techniques |
| CN109600560A (en) * | 2018-12-04 | 2019-04-09 | 中国航空工业集团公司洛阳电光设备研究所 | Cmos image sensor exports high speed serialization LVDS signal calibration method and device |
| CN115642902A (en) * | 2022-11-11 | 2023-01-24 | 深圳市紫光同创电子有限公司 | Sampling clock delay phase determining method, device and system and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024098932A1 (en) * | 2022-11-11 | 2024-05-16 | 深圳市紫光同创电子有限公司 | Sampling clock delay phase determination method, apparatus and system, and storage medium |
| CN116055927A (en) * | 2023-04-03 | 2023-05-02 | 深圳市紫光同创电子有限公司 | Data double oversampling method, system, equipment and storage medium |
| CN116055927B (en) * | 2023-04-03 | 2023-06-02 | 深圳市紫光同创电子有限公司 | Data double oversampling method, system, equipment and storage medium |
| CN116954306A (en) * | 2023-09-20 | 2023-10-27 | 芯动微电子科技(珠海)有限公司 | Clock phase shifting method and device |
| CN116954306B (en) * | 2023-09-20 | 2024-01-02 | 芯动微电子科技(珠海)有限公司 | Clock phase shifting method and device |
| CN117076372A (en) * | 2023-10-12 | 2023-11-17 | 北京华峰测控技术股份有限公司 | Communication signal receiving interface circuit and communication method |
| CN117076372B (en) * | 2023-10-12 | 2023-12-26 | 北京华峰测控技术股份有限公司 | Communication signal receiving interface circuit and communication method |
| CN117590897A (en) * | 2023-11-23 | 2024-02-23 | 北京国科天迅科技股份有限公司 | Chip and chip control method |
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| WO2024098932A1 (en) | 2024-05-16 |
| WO2024098932A9 (en) | 2024-06-13 |
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