CN115642801A

CN115642801A - Cross-coupled charge pump circuit

Info

Publication number: CN115642801A
Application number: CN202211346359.5A
Authority: CN
Inventors: 许屹昂; 胡剑
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2023-01-24

Abstract

The invention discloses a cross-coupling charge pump circuit, comprising: the first charge and discharge circuit is used for charging and discharging the first capacitor under the control of a zeroth clock and a first clock so as to generate a first high-voltage pulse; the second charge and discharge circuit is used for charging and discharging the second capacitor under the control of the reverse zeroth clock and the second clock so as to generate a second high-voltage pulse; the first transmission circuit is used for transmitting the first high-voltage pulse generated by the first charge and discharge circuit to a load under the control of a reverse phase second clock; the second transmission circuit is used for transmitting the second high-voltage pulse generated by the second charge and discharge circuit to a load under the control of the inverted first clock; the four-phase non-overlapping clock generation circuit is used for converting an input clock source into the non-overlapping zeroth clock, the non-overlapping inverted zeroth clock, the non-overlapping first clock, the non-overlapping inverted first clock, the non-overlapping second clock and the non-overlapping second clock; and the load, the efficiency of the charge pump structure can be greatly improved by the invention.

Description

Cross-coupled charge pump circuit

Technical Field

The present invention relates to a cross-coupled charge pump circuit, and more particularly, to a cross-coupled charge pump circuit using four-phase non-overlapping clocks.

Background

The charge pump circuit is one of the most important circuits of the whole Flash memory, and determines the area and the power consumption of the Flash memory.

The prior art charge pump circuit is shown in fig. 1 and includes: the device comprises a clock circuit 10, a charging and discharging circuit 20, a substrate voltage adjusting circuit 30, a transmission circuit 40 and a load 50, wherein the clock circuit 10 consists of a clock source CLK, inverters I1, I2 and I3 and is used for generating an output clock CLKK and an inverted output clock CLKKB; the charge-discharge circuit 20 consists of NMOS tubes MN1 and MN2 and charge-discharge capacitors C1 and C2 and is used for generating pulse high voltage through the charge-discharge of the charge-discharge capacitors C1 and C2 under the control of an output clock; the transmission circuit 40 is composed of PMOS transistors MP3 and MP4, and is configured to transmit the pulse high voltage generated by the charge and discharge circuit 20 to the load 50; the substrate voltage adjusting circuit 30 is composed of PMOS transistors MP1 and MP2, and is configured to adjust the substrate voltages of the transmission transistors MP3 and MP4 to reduce the substrate bias effect; the load 50 is composed of a load resistor RL and a load capacitor CL and is used for simulating the load of the charge pump.

Fig. 2 and 3 are respectively a power supply current waveform diagram of a conventional charge pump circuit during clock conversion, and a curve diagram of the output voltage and efficiency of the conventional charge pump circuit with the change of a load current. Therefore, in the existing charge pump circuit, the clock signals are strictly inverted, and the MOS tubes are simultaneously conducted in a short time, so that the efficiency is low, the power consumption is high, the area of a used wafer is inevitably increased to meet the requirement of output load, and the cost of a chip is increased.

Disclosure of Invention

To overcome the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a cross-coupled charge pump circuit, which can greatly improve the efficiency of the charge pump structure.

To achieve the above and other objects, the present invention provides a cross-coupled charge pump circuit, comprising:

the first charging and discharging circuit is used for charging and discharging a first capacitor (C1) to generate a first high-voltage pulse under the control of a zeroth clock (clk) and a first clock (clk 1);

a second charging and discharging circuit for charging and discharging a second capacitor (C2) to generate a second high voltage pulse under the control of the inverted zero clock (clkb) and the second clock (clk 2);

a first transmission circuit for transmitting a first high voltage pulse generated by the first charge and discharge circuit to a load under the control of an inverted second clock (clk 2 b);

a second transmission circuit for transmitting a second high voltage pulse generated by the second charge and discharge circuit to a load under the control of an inverted first clock (clk 1 b);

a four-phase non-overlapping clock generation circuit for converting an input clock source into the non-overlapping zero clock (clk), inverted zero clock (clkb), first clock (clk 1), inverted first clock (clk 1 b), second clock (clk 2), and inverted second clock (clk 2 b); and

and (4) loading.

Optionally, the four-phase non-overlapping clock generating circuit is connected to an input clock source to generate the zero-th clock (clk), the first clock (clk 1), the inverted second clock (clk 2 b) whose high levels do not overlap and the inverted zero-th clock (clkb), the second clock (clk 2), the inverted first clock (clk 1 b) whose high levels do not overlap.

Optionally, the four-phase non-overlap clock generating circuit comprises a first nor gate (NR 1), second to sixth nor gates, a seventh and gate (AD 7), an eighth OR gate (OR 8), a tenth nor gate (I10), an eleventh nor gate (NR 11), twelfth to sixteenth nor gates, a seventeenth and gate (AD 7), an eighteenth OR gate (OR 8), and a third capacitor (C3), a fourth capacitor (C4), a thirteenth capacitor (C13), a fourteenth capacitor ((C14), wherein an input terminal of the first nor gate (NR 1) and an input terminal of the tenth not gate (I10) are connected to form an input terminal of the four-phase non-overlap clock generating circuit and are connected to the input clock source, an output terminal of the tenth not gate (I10) is connected to an input terminal of the eleventh nor gate (NR 11), an output terminal of the first nor gate (NR 1) is connected to an input terminal of the second not gate (I2), an output terminal of the second not gate (I2) is connected to an input terminal of the thirteenth not gate (I3) and an input terminal of the thirteenth nor gate (NR 3), an output terminal of the eleventh OR gate (C13), an input terminal of the twelfth OR gate (NR 12) is connected to an input terminal of the twelfth OR gate (C12), an output terminal of the eleventh OR gate (C12) is connected to an input terminal of the eleventh OR gate (C12, an output end of the thirteenth not gate (I13) is connected to an input end of the fourteenth not gate (I14), an input end of the seventeenth and gate (AD 17), an input end of the eighteenth OR gate (OR 18) and the other input end of the first NOR gate (NR 1), an output end of the fourth not gate (I4) is connected to an input end of the fifth not gate (I5) and one end of the fourth capacitor (C4), an output end of the fifth not gate (I5) is connected to the other input end of the seventh AND gate (AD 7) and the other input end of the eighth OR gate (OR 8), an output end of the fourteenth NOT gate (I14) is connected with an input end of a fifteenth NOT gate (I15) and one end of a fifth capacitor (C5), an output end of the fifteenth NOT gate (I15) is connected with the other input end of a seventeenth AND gate (AD 17) and the other input end of an eighteenth OR gate (OR 18), the second clock (clk 2) output by the seventh AND gate (AD 7) is connected with an input end of a sixth NOT gate (I16), the inverted second clock (clk 2 b) output by the sixth NOT gate (I6), and the zero clock (clk) output by the eighth OR gate (OR 8), the output of the seventeenth AND gate (AD 17) the first clock (clk 1) is connected to the input of a sixteenth NOT gate (I16), the output of the sixteenth not gate (I16) is the inverted first clock (clk 1 b), and the output of the eighteenth OR gate (OR 18) is the inverted zero clock (clkb).

Optionally, the first charge and discharge circuit and the second charge and discharge circuit are symmetrical circuits.

Optionally, the first charge and discharge circuit includes a first NMOS transistor (MN 1), a third NMOS transistor (MN 3), a first capacitor (C1) and a first auxiliary capacitor (Ca 1), the zero clock (clk) is connected to one end of the first capacitor (C1), the first clock (clk 1) is connected to one end of the first auxiliary capacitor (Ca 1), a source and a substrate of the first NMOS transistor (MN 1), a source and a substrate of the third NMOS transistor (MN 3) are connected to the power supply (Vin), a gate of the first NMOS transistor (MN 1), a drain of the third NMOS transistor (MN 3) and another end of the first auxiliary capacitor (Ca 1) form a node vn1, and a drain of the first NMOS transistor (MN 1), a gate of the third NMOS transistor (MN 3), another end of the first capacitor (C1) and a source of the first PMOS transistor (MP 1) form a node a.

Optionally, the second charging and discharging circuit includes a second NMOS transistor (MN 2), a fourth NMOS transistor (MN 4), a second capacitor (C2), and a second auxiliary capacitor (Ca 2), the inverted zero-th clock (clkb) is connected to one end of the second capacitor (C2), and the second clock (clk 2) is connected to one end of the second auxiliary capacitor (Ca 2); the source electrode and the substrate of the second NMOS tube (MN 2), the source electrode and the substrate of the fourth NMOS tube (MN 4) are connected with the power supply (Vin), the drain electrode of the second NMOS tube (MN 2) and the grid electrode of the fourth NMOS tube (MN 4), the other end of the second capacitor (C2) and the source electrode of the second PMOS tube (MP 2) form a node B, and the grid electrode of the second NMOS tube (MN 2) and the drain electrode of the fourth NMOS tube (MN 4) and the other end of the second auxiliary capacitor (Ca 2) form a node vn2.

Optionally, the first transmission circuit and the second transmission circuit are symmetrical circuits.

Optionally, the first transmission circuit includes a fifth NMOS transistor (MN 5), a first PMOS transistor (MP 1), and a third auxiliary capacitor (Cb 1), the inverted second clock (clk 2 b) is connected to one end of the third auxiliary capacitor (Cb 1), a source, a substrate, and a gate of the fifth NMOS transistor (MN 5) are connected to the power Vin, a drain of the fifth NMOS transistor (MN 5), a gate of the first PMOS transistor (MP 1), and another end of the third auxiliary capacitor (Cb 1) form a node Vp1, a drain and a substrate of the first PMOS transistor (MP 1) are connected to the second transmission circuit to form an output node Vout, and the output node Vout is connected to the load.

Optionally, the second transmission circuit includes a sixth NMOS transistor (MN 6), a second PMOS transistor (MP 2) and a fourth auxiliary capacitor (Cb 2), the inverted first clock (clk 1 b) is connected to one end of the fourth auxiliary capacitor (Cb 2), a source, a substrate and a gate of the sixth NMOS transistor (MN 6) are connected to the power Vin, a drain of the sixth NMOS transistor (MN 6) forms a node Vp2 with the gate of the second PMOS transistor (MP 2) and the other end of the fourth auxiliary capacitor (Cb 2), and the drain of the second PMOS transistor (MP 2) is connected to the substrate and the drain of the first PMOS transistor (MP 1) to form the output node.

Optionally, the load comprises a load Resistor (RL) and a load Capacitor (CL), the output node (Vout) is connected to one end of the load Resistor (RL) and one end of the load Capacitor (CL), and the other end of the load Resistor (RL) and the other end of the load Capacitor (CL) are grounded.

Compared with the prior art, the zero clock clk and the first clock clk1 generated by the four-phase non-overlapping clock generation circuit and the inverted zero clock clkb and the second clock clk2 do not have high level overlapping, the clock inverted second clock clk2b and the inverted first clock clk1b which are responsible for closing the discharging path are wider in high level 1, short circuit is avoided, and therefore the efficiency of the charge pump is effectively improved.

Drawings

FIG. 1 is a circuit diagram of a prior art charge pump circuit;

FIG. 2 is a diagram of a power supply current waveform during clock transitions for a conventional charge pump circuit;

FIG. 3 is a graph of output voltage and efficiency of a conventional charge pump circuit as a function of load current;

FIG. 4 is a circuit diagram of a cross-coupled charge pump circuit according to the present invention;

FIG. 5 is a circuit diagram of a four-phase non-overlapping clock generation circuit according to an embodiment of the present invention;

FIG. 6 is a diagram of the waveforms of the power supply current during the four-phase non-overlapping clock and voltage transitions of the present invention.

Detailed Description

Other advantages and capabilities of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification by describing embodiments of the present invention with specific embodiments and by referring to the attached drawings. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Fig. 4 is a circuit diagram of a cross-coupled charge pump circuit according to the present invention. As shown in fig. 4, a cross-coupled charge pump circuit of the present invention includes: the circuit comprises a first charging and discharging circuit 10, a second charging and discharging circuit 20, a first transmission circuit 30, a second transmission circuit 40, a four-phase non-overlap clock generating circuit 50 and a load 60.

The first charge/discharge circuit 10 includes: the first NMOS transistor MN1, the third NMOS transistor MN3, the first capacitor C1, and the first auxiliary capacitor Ca1 are configured to charge and discharge the first capacitor C1 under the control of the zero-th clock clk and the first clock clk1 to generate a first high-voltage pulse; the second charge and discharge circuit 20 includes: the second NMOS transistor MN2, the fourth NMOS transistor MN4, the second capacitor C2, and the second auxiliary capacitor Ca2 are configured to charge and discharge the second capacitor C2 to generate a second high-voltage pulse under the control of the inverted zero-th clock clkb and the second clock clk 2; the first transmission circuit 30 includes: a fifth NMOS transistor MN5, a first PMOS transistor MP1, and a third auxiliary capacitor Cb1, configured to transmit the first high-voltage pulse generated by the first charge/discharge circuit 10 to the load 60 under the control of the inverted second clock clk2 b; a second transmission circuit 40, comprising: a sixth NMOS transistor MN6, a second PMOS transistor MP2, and a fourth auxiliary capacitor Cb2, configured to transmit the second high-voltage pulse generated by the second charge/discharge circuit 20 to the load 60 under the control of the inverted first clock clk1 b; a four-phase non-overlapping clock generation circuit 50 comprising: first nor gate NR1, second to sixth not gates I2-I6, seventh and gate AD7, eighth OR gate clk 8, tenth not gate, eleventh not gate NR11, twelfth to sixteenth not gates I12-I16, seventeenth and gate AD7, eighteenth OR gate OR8, and third capacitor C3, fourth capacitor C4, thirteenth capacitor C13, fourteenth capacitor C14 for converting the input clock source clkin into a zero clock clk, an inverted zero clock clkb, a first clock clk1, an inverted first clock clk1b, a second clock clk2, and an inverted second clock clk2b, so that the zero clock, the first clock 1, the inverted second clock clk2b high levels used by the upper branch do not overlap (non-overlap clock), and the 3 clock signals used by the lower branch do not invert the zero clock clkb, the second clock 2, the inverted second clock clk2b high levels (non-overlap clock), and the 3 clock signals used by the lower branch do not overlap the first clock 2, the inverted clock 1b high levels (non-overlap clock); a load 60, comprising: and the load resistor RL and the load capacitor CL are used for simulating the load of the charge pump.

Specifically, the zeroth clock clk is connected to one end of the first capacitor C1, the inverted zeroth clock clkb is connected to one end of the second capacitor C2, the first clock clk1 is connected to one end of the first auxiliary capacitor Ca1, and the second clock clk2 is connected to one end of the second auxiliary capacitor Ca 2; a source electrode and a substrate of a first NMOS tube MN1, a source electrode and a substrate of a third NMOS tube MN3, a source electrode and a substrate of a second NMOS tube MN2, a source electrode and a substrate of a fourth NMOS tube MN4 are connected with a power source Vin, a gate electrode of the first NMOS tube MN1, a drain electrode of the third NMOS tube MN3 and the other end of a first auxiliary capacitor Ca1 form a node vn1, a drain electrode of the first NMOS tube MN1, a gate electrode of the third NMOS tube MN3, the other end of a first capacitor C1 and a source electrode of a first PMOS tube MP1 form a node A, a drain electrode of the second NMOS tube MN2, a gate electrode of the fourth NMOS tube MN4, the other end of the second capacitor C2 and a source electrode of the second PMOS tube MP2 form a node B, and a gate electrode of the second NMOS tube MN2, a drain electrode of the fourth NMOS tube MN4 and the other end of the second auxiliary capacitor Ca2 form a node vn2;

the inverted second clock clk2b is connected to one end of the third auxiliary capacitor Cb1, and the inverted first clock clk1b is connected to one end of the fourth auxiliary capacitor Cb 2; a source electrode, a substrate and a grid electrode of the fifth NMOS transistor MN5, and a source electrode, a substrate and a grid electrode of the sixth NMOS transistor MN6 are connected with a power source Vin, a drain electrode of the fifth NMOS transistor MN5, the grid electrode of the first PMOS transistor MP1 and the other end of the third auxiliary capacitor Cb1 form a node Vp1, and a drain electrode of the sixth NMOS transistor MN6, the grid electrode of the second PMOS transistor MP2 and the other end of the fourth auxiliary capacitor Cb2 form a node Vp2; the drain electrode of the first PMOS tube MP1 is connected with the substrate, the drain electrode of the second PMOS tube MP2 is connected with the substrate to form an output node Vout, the output node Vout is connected to one end of a load resistor RL and one end of a load capacitor CL, and the other end of the load resistor RL and the other end of the load capacitor CL are grounded;

the input clock source clkin is connected to an input terminal of the four-phase non-overlap clock generating circuit 50, and outputs of the four-phase non-overlap clock generating circuit 50 are a zero-th clock clk, an inverted zero-th clock clkb, a first clock clk1, an inverted first clock clk1b, a second clock clk2, and an inverted second clock clk2b.

Specifically, the detailed structure of the four-phase non-overlap clock generating circuit 50 is as shown in fig. 5, wherein an input terminal of the first nor gate NR1 and an input terminal of the tenth not gate I10 are connected to form an input terminal of the four-phase non-overlap clock generating circuit 50 and connected to the input clock source clkin, and an output terminal of the tenth not gate I10 is connected to an input terminal of the eleventh not gate NR 11;

an output end of the first nor gate NR1 is connected to an input end of the second nor gate I2, an output end of the second not gate I2 is connected to an input end of the third not gate I3 and one end of the third capacitor C3, an output end of the third not gate I3 is connected to an input end of the fourth not gate I4, one input end of the seventh and gate AD7, one input end of the eighth OR gate OR8 and the other input end of the eleventh nor gate NR11, an output end of the eleventh nor gate NR11 is connected to an input end of the twelfth not gate I12, an output end of the twelfth not gate I12 is connected to an input end of the thirteenth not gate I13 and one end of the thirteenth capacitor C13, and an output end of the thirteenth not gate I13 is connected to an input end of the fourteenth not gate I14, one input end of the seventeenth and gate AD17, one input end of the eighteenth OR gate OR18 and the other input end of the first nor gate NR 1;

an output end of the fourth not gate I4 is connected to an input end of the fifth not gate I5 and one end of the fourth capacitor C4, an output end of the fifth not gate I5 is connected to another input end of the seventh and gate AD7 and another input end of the eighth OR gate OR8, an output end of the fourteenth not gate I14 is connected to an input end of the fifteenth not gate I15 and one end of the fifth capacitor C5, and an output end of the fifteenth not gate I15 is connected to another input end of the seventeenth and gate AD17 and another input end of the eighteenth OR gate OR 18;

the output of the seventh and gate AD7, i.e., the second clock clk2, is connected to the input terminal of the sixth not gate I16, the output of the sixth not gate I6, i.e., the inverted second clock clk2b, the output of the eighth OR gate OR8, i.e., the zero clock clk, the output of the seventeenth and gate AD17, i.e., the first clock clk1, is connected to the input terminal of the sixteenth not gate I16, the output of the sixteenth not gate I16, i.e., the inverted first clock clk1b, and the output of the eighteenth OR gate OR18, i.e., the inverted zero clock clkb.

FIG. 6 is a diagram of the power supply current waveforms during four-phase non-overlapping clock and voltage transitions in accordance with the present invention. In the present invention, since fig. 4 is a symmetrical circuit, the operation principle of the present invention will be described below with reference to fig. 4 and 6, taking only the upper half as an example:

after power-on, the nodes A, vn1 and Vp1 are precharged to Vin-Vthn, and the source and gate short circuit of the fifth NMOS transistor MN5 is equivalent to a diode, so that the node Vp1 precharge voltage is also Vin-Vthn, vthn is the threshold voltage of the NMOS transistors MN1/MN3/MN5, assuming that the threshold values of the NMOS transistors MN1-MN6 are all Vthn and the threshold values of the PMOS transistors MP1-MP2 are Vthp, and assuming that the voltages of the high levels "1" of all clocks are Vh.

When clk is at low level "0", when clk1 changes from "0" to "1", since the voltage of the first auxiliary capacitor Ca1 cannot suddenly change, the voltage of the node vn1, i.e. the gate voltage of the first NMOS transistor MN1, is raised to Vh + (Vin-Vthn), so that the first NMOS transistor MN1 is turned on, the first capacitor C1 is charged, the voltage of the node a, i.e. the gate voltage of the third NMOS transistor MN3, is precharged to Vin-Vthn, the third NMOS transistor MN3 is turned off, and the voltage of the node vn1 is further stabilized, when clk2b jumps from "0" to "1", since the voltage of the third auxiliary capacitor Cb1 cannot suddenly change, the voltage of the node Vp1 is raised to Vh + (Vin-Vthn), the first PMOS transistor MP1 is turned off, and further charge loss of the node a is prevented; when clk1 goes low to "0", node vn1 will drop to Vin-Vthn, the first NMOS transistor MN1 is turned off, and then clk goes from "0" to "1", since the voltage of the first capacitor C1 cannot change suddenly, the gate voltage of node a, i.e. the third NMOS transistor MN3, is raised to Vh + (Vin-Vthn), so that the third NMOS transistor MN3 is turned on, the voltage of node vn1 is stabilized at Vin-Vthn, and at the same time clk2b jumps to "0" which the voltage of node Vp1 drops, the first PMOS transistor MP1 is turned on, and the charge of node a moves to the load RL/CL through the first PMOS transistor MP1, i.e. the first capacitor C1 discharges.

The lower half of the clock is in phase opposition to the upper half, i.e., clk is in phase opposition to clkb, clk2 is in phase opposition to clk1, and clk1b is in phase opposition to clk2b. When clk changes from "0" to "1", the first capacitor C1 of the upper half circuit discharges to the load RL/CL, and because of the opposite phase, the lower half circuit charges to the second capacitor C2; when clkb changes from "0" to "1", the second capacitor C2 of the lower half circuit discharges to the load RL/CL, and because of the opposite phase, the first capacitor C1 is charged by the upper half circuit.

Because the clocks clk and clk1 and clkb and clk2 do not have high level overlap, the high levels "1" of the clocks clk2b and clk1b which are responsible for closing the discharging path are wider, so that short circuit is avoided, and the efficiency of the charge pump is effectively improved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as set forth in the claims.

Claims

1. A cross-coupled charge pump circuit, comprising:

a first charging and discharging circuit for charging and discharging a first capacitor (C1) to generate a first high voltage pulse under the control of a zeroth clock (clk) and a first clock (clk 1);

and (4) loading.

2. A cross-coupled charge pump circuit as claimed in claim 1, wherein said four-phase non-overlapping clock generating circuit is connected to an input clock source to generate said zero clock (clk), first clock (clk 1), inverted second clock (clk 2 b) with no overlap of high level and said inverted zero clock (clkb), second clock (clk 2), inverted first clock (clk 1 b) with no overlap of high level.

3. A cross-coupled charge pump circuit as claimed in claim 2, wherein the four-phase non-overlap clock generating circuit comprises a first nor gate (NR 1), second to sixth not gates, a seventh and gate (AD 7), an eighth OR gate (OR 8), a tenth not gate (I10), an eleventh nor gate (NR 11), twelfth to sixteenth not gates, a seventeenth and gate (AD 7), an eighteenth OR gate (OR 8), a third capacitor (C3), a fourth capacitor (C4), a thirteenth capacitor (C13), a fourteenth capacitor (C14), an input terminal of the first nor gate (NR 1) and an input terminal of the tenth not gate (I10) are connected to form the input terminal of the four-phase non-overlap clock generating circuit and are connected to the input clock source, an output terminal of the tenth not gate (I10) is connected to an input terminal of the eleventh nor gate (NR 11), an output terminal of the first nor gate (NR 1) is connected to an input terminal of the second not gate (I2), an output terminal of the second not gate (I2) is connected to an input terminal of the eleventh not gate (I3), an output terminal of the eleventh not gate (NR 3) is connected to an input terminal of the twelfth not gate (I12), an output terminal of the eleventh not gate (NR 3) and an input terminal of the eleventh not gate (I12), an input terminal of the eleventh not gate (3) and an input terminal of the eleventh not gate (NR 12) are connected to an input terminal of the twelfth not gate (I12), and an input terminal of the eleventh not gate (I12) are connected to an input terminal of the twelfth not gate (I12), and an input terminal of the eleventh not gate (I8) and a twelfth not gate (I4) are connected to an input terminal of the eleventh not gate (I12) One terminal of a thirteenth capacitor (C13), an output terminal of the thirteenth not-gate (I13) is connected to an input terminal of the fourteenth not-gate (I14), an input terminal of the seventeenth and-gate (AD 17), an input terminal of the eighteenth OR-gate (OR 18) and another input terminal of the first nor-gate (NR 1), an output terminal of the fourth not-gate (I4) is connected to an input terminal of the fifth not-gate (I5) and one terminal of the fourth capacitor (C4), an output terminal of the fifth not-gate (I5) is connected to another input terminal of the seventh and-gate (AD 7), another input terminal of the eighth OR-gate (OR 8), an output terminal of the fourteenth not-gate (I14) is connected to an input terminal of the fifteenth not-gate (I15) and one terminal of the fifth capacitor (C5), an output terminal of the fifteenth not-gate (I15) is connected to another input terminal of the seventeenth and-gate (AD 17), another input terminal of the eighteenth OR-gate (OR 18), an output terminal of the seventh not-gate (AD 7) is connected to the second clock (2), and output terminal of the sixth not-gate (I2) is connected to the sixth inverted output terminal of the sixth not-gate (I8) OR-gate (I8), and-gate (I8), the output of the seventeenth AND gate (AD 17) the first clock (clk 1) is connected to the input of a sixteenth NOT gate (I16), the sixteenth not gate (I16 output the inverted first clock (clk 1 b), the eighteenth OR gate (OR 18) output the inverted zero clock (clkb).

4. A cross-coupled charge pump circuit as claimed in any one of claims 1 to 3, wherein the first charge and discharge circuit and the second charge and discharge circuit are symmetrical circuits.

5. The cross-coupled charge pump circuit of claim 4, wherein the first charge/discharge circuit comprises a first NMOS transistor (MN 1), a third NMOS transistor (MN 3), a first capacitor (C1), and a first auxiliary capacitor (Ca 1), the zeroth clock (clk) is connected to one end of the first capacitor (C1), the first clock (clk 1) is connected to one end of the first auxiliary capacitor (Ca 1), the source and the substrate of the first NMOS transistor (MN 1), the source and the substrate of the third NMOS transistor (MN 3) are connected to a power supply (Vin), the gate of the first NMOS transistor (MN 1) and the drain of the third NMOS transistor (MN 3) and the other end of the first auxiliary capacitor (Ca 1) form a node vn1, the drain of the first NMOS transistor (MN 1) and the gate of the third NMOS transistor (MN 3), the other end of the first capacitor (C1), and the source of the first PMOS transistor (MP 1) form a node a.

6. The cross-coupled charge pump circuit as claimed in claim 5, wherein the second charge/discharge circuit comprises a second NMOS transistor (MN 2), a fourth NMOS transistor (MN 4), a second capacitor (C2), and a second auxiliary capacitor (Ca 2), the inverted zero clock (clkb) is connected to one end of the second capacitor (C2), and the second clock (clk 2) is connected to one end of the second auxiliary capacitor (Ca 2); the source electrode and the substrate of the second NMOS tube (MN 2), the source electrode and the substrate of the fourth NMOS tube (MN 4) are connected with the power supply (Vin), the drain electrode of the second NMOS tube (MN 2) and the grid electrode of the fourth NMOS tube (MN 4), the other end of the second capacitor (C2) and the source electrode of the second PMOS tube (MP 2) form a node B, and the grid electrode of the second NMOS tube (MN 2) and the drain electrode of the fourth NMOS tube (MN 4) and the other end of the second auxiliary capacitor (Ca 2) form a node vn2.

7. The cross-coupled charge pump circuit of claim 6, wherein the first transmission circuit and the second transmission circuit are symmetrical circuits.

8. The cross-coupled charge pump circuit as claimed in claim 7, wherein the first transfer circuit comprises a fifth NMOS transistor (MN 5), a first PMOS transistor (MP 1) and a third auxiliary capacitor (Cb 1), the inverted second clock (clk 2 b) is connected to one end of the third auxiliary capacitor (Cb 1), the source, the substrate and the gate of the fifth NMOS transistor (MN 5) are connected to the power Vin, the drain of the fifth NMOS transistor (MN 5) and the gate of the first PMOS transistor (MP 1) and the other end of the third auxiliary capacitor (Cb 1) form a node Vp1, the drain and the substrate of the first PMOS transistor (MP 1) and the second transfer circuit are connected to form an output node Vout, and the output node Vout is connected to the load.

9. The cross-coupled charge pump circuit as claimed in claim 8, wherein the second transfer circuit comprises a sixth NMOS transistor (MN 6), a second PMOS transistor (MP 2) and a fourth auxiliary capacitor (Cb 2), the inverted first clock (clk 1 b) is connected to one end of the fourth auxiliary capacitor (Cb 2), the source, the substrate and the gate of the sixth NMOS transistor (MN 6) are connected to the power Vin, the drain of the sixth NMOS transistor (MN 6) and the gate of the second PMOS transistor (MP 2) and the other end of the fourth auxiliary capacitor (Cb 2) form a node Vp2, and the drain of the second PMOS transistor (MP 2) and the substrate, and the drain of the first PMOS transistor (MP 1) and the substrate are connected to form the output node.

10. A cross-coupled charge pump circuit as claimed in claim 9, wherein the load comprises a load Resistor (RL) and a load Capacitor (CL), the output node (Vout) is connected to one end of the load Resistor (RL) and one end of the load Capacitor (CL), and the other end of the load Resistor (RL) and the other end of the load Capacitor (CL) are grounded.