CN115632543A - Method and circuit for inhibiting dynamic volt-second unbalance problem of active clamp converter - Google Patents
Method and circuit for inhibiting dynamic volt-second unbalance problem of active clamp converter Download PDFInfo
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- CN115632543A CN115632543A CN202211203547.2A CN202211203547A CN115632543A CN 115632543 A CN115632543 A CN 115632543A CN 202211203547 A CN202211203547 A CN 202211203547A CN 115632543 A CN115632543 A CN 115632543A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Power Engineering (AREA)
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Abstract
The invention provides a method and a circuit for inhibiting dynamic volt-second unbalance of an active clamp converter, wherein the method comprises the following steps: obtaining v B Point voltage value, switch tube Q 3 First on signal Q 3on1 And a switching tube Q 4 Turn-on signal Q of 4on (ii) a For v B Point voltage value and turn-on signal Q 4on Analyzing and processing to determine the switch tube Q 3 ZVS detection signal Q 3ZVS (ii) a For the first open signal Q 3on1 And ZVS detection signal Q 3ZVS Performing AND operation to obtain the switching tube Q 3 Second on signal Q 3on2 (ii) a Second on signal Q through PWM generation module 3on2 Is processedTo obtain the switching tube Q 3 Drive signal Q of 3GS To drive the switch tube Q 3 . The present disclosure changes the switch tube Q 3 The driving signal realizes that the switching tube Q is switched from full load to no load under the condition that the current peak value of the exciting inductor is reduced to be below zero 3 The purpose of not switching on is achieved, and therefore the problem that the converter stops running when the converter is shut down due to the fact that the voltage of a clamping capacitor drops rapidly in the dynamic response process of the converter to trigger a protection mechanism is solved.
Description
Technical Field
The disclosure relates to the technical field of converter control, in particular to a method and a circuit for suppressing dynamic voltage-second unbalance of an active clamp converter.
Background
With the development of high-density miniaturization, high-speed and high-power of electronic systems, the switching power converter with high power density and high efficiency is more and more widely applied. Active clamp converters, such as active clamp flyback converters, active clamp forward converters, dual-clamp zero-voltage switching converters, and the like, are widely used in the power supply field of communication, industry and the like due to the characteristics of high efficiency, full-range soft switching, high switching frequency adaptation and the like.
A self-adaptive control method and circuit for a Zero Voltage Switch of an active clamp type converter are applied to a double-clamp Zero Voltage Switch (ZVS) buck-boost converter. The circuit structure of the converter is shown in FIG. 1The circuit mainly comprises a primary side switching tube Q 1 ～Q 4 Power transformer T r A clamp capacitor C f Secondary side synchronous rectifier Q 5 And an output filter capacitor C LD Power transformer T r Including an exciting inductance L m Equivalent leakage inductance L of primary side r . By sampling the switching tube Q 4 Of the drain-source voltage v dsQ4 Acquiring characteristic information of ZVS characteristics of a main switching tube, and then combining volt-second balance and an adjustment value acquired by closed-loop control of the characteristic information to perform self-adaptive adjustment on the opening time of the clamping switching tube so as to realize closed-loop control on the negative current of the transformer.
Fig. 2 shows a block diagram of an implementation of a zero-voltage switching adaptive control method of an active clamp converter, in which a clamp capacitor voltage V L Converted into analog sampling signal v by sampling circuit Ls And clamp capacitor voltage reference V Lref Making a difference, and adjusting the voltage of a clamping capacitor of the converter through a proportional integral adjuster according to the difference value; input voltage V in Switching tube Q converted into analog signal by sampling circuit for calculating converter 1 ～Q 3 The on-time parameter of (c); switch tube Q 4 Is of the drain-source voltage v dsQ4 Connected to a digital controller via a sampling circuit, and subjected to pulse width extraction and closed-loop pulse width regulation to obtain a switching tube Q 3 The switching time adjustment value dT3, and V in Sampling value v ins Regulator output value v er Calculating together to obtain the switching tube Q 1 ～Q 3 On-time of (d); after generating a driving signal by a PWM production module, further judging v dsQ4 To ensure the switching tube Q 4 ZVS is turned on to obtain the switch tube Q 1 ～Q 4 Drive signal V of QS1 ～V QS4 (ii) a The secondary side adopts synchronous rectification control, and a synchronous rectification driver detects the synchronous rectification tube Q 5 The drain-source terminal voltage of the transistor, and the zero-voltage switching-on and zero-current switching-off are judged to generate Q 5 Drive control signal V of QS5 I.e. Q is turned on when the drain-source voltage is below the turn-on threshold voltage 5 Turn off Q when drain-source voltage is above turn-off threshold voltage 5 。
From the above analysis, it can be seen that the ZVS adaptive control method of the converter involves two control loops, one is to adjust T of the output voltage 1 Loop of (3), its calculated value and input voltage V in Is inversely proportional to the output value v of the clamping capacitor voltage closed-loop regulation module to improve the dynamic response of the converter under the condition of input voltage jump er The voltage stabilizing control is realized by proportional ratio to the output voltage of the converter; the other is T 3 For realizing the control of the reverse excitation current and further realizing the switch tube Q 1 And Q 4 Reliable ZVS. During actual operation, if T 3 Is too fast, once a certain period T 3 If the calculated value of (A) is slightly larger than the value required by volt-second balance, then the negative current of the excitation inductor is too large, and T is 1 Will increase T 1 To ensure output regulation, then at T 3 Under the action of the loop of (A) T 3 Further increases the calculated value of (a), the converter enters a divergent state, so in order to maintain a stable operation of the converter, T 3 Is slower than T 1 Of the loop of (a). However, when the converter output is switched from heavy load to no load, as shown in figure 3, at T 1 Under the action of the loop of the switch tube Q 1 The on-time of the switching tube Q is rapidly reduced 3 The on-time of the switch tube Q is updated to the value required for maintaining volt-second balance after several cycles, and then the switch tube Q is turned on 3 The conduction time of the inductor is far longer than the conduction time required for maintaining volt-second balance, and the current i of the exciting inductor Lm Fast falling secondary side synchronous rectifier tube Q 5 The turn-on time of (c) is also reduced until the minimum turn-on time limited by the synchronous rectification chip is reached. When the peak value of the exciting inductance current is i Lm_peak When the voltage is greater than 0, the switch tube Q 3 Synchronous rectifier tube Q in conducting time period 5 When the switch is turned on, the output capacitor is discharged, but when the current peak value i of the exciting inductor is Lm_peak When the voltage drops below 0, the secondary side synchronous rectifier Q 5 The switch tube Q is not opened when the switch tube Q does not have the opening condition 3 The clamp capacitor discharges in the conducting time period, and the clamp capacitor has small capacitance value, high discharge speed and voltage V L Will fall rapidly. Due to change ofThe converter controls and judges whether the output over-voltage and under-voltage protection is carried out by clamping capacitor voltage V L When the voltage drop of the clamp capacitor is too large, as shown in an actual experimental waveform shown in fig. 4, a protection mechanism of the converter is easily triggered, so that the converter is shut down and does not operate any more.
Disclosure of Invention
The present disclosure provides a method and a circuit for suppressing a dynamic voltage-second imbalance problem of an active clamp converter, so as to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, a method for suppressing a dynamic voltage-second imbalance problem of an active clamp converter is provided.
In one embodiment, the method comprises: obtaining v B Point voltage value, switch tube Q 3 First on signal Q 3on1 And a switching tube Q 4 Turn-on signal Q of 4on (ii) a For v is to v B Point voltage value and said turn-on signal Q 4on Analyzing and processing to determine the switch tube Q 3 ZVS detection signal Q of 3ZVS (ii) a For the first on signal Q 3on1 And said ZVS detection signal Q 3ZVS Performing AND operation to obtain the switching tube Q 3 Second on signal Q 3on2 (ii) a The second opening signal Q is generated by a PWM generation module 3on2 Processing to obtain a switching tube Q 3 Drive signal Q of 3GS To drive the switch tube Q 3 。
In one embodiment, said pair of said v B Point voltage value and said turn-on signal Q 4on Analyzing and determining the switch tube Q 3 ZVS detection signal Q of 3ZVS The method comprises the following steps: at the turn-on signal Q 4on Is low level and said v B Determining the ZVS detection signal Q when the point voltage value reaches the reference voltage 3ZVS Is high level; at the turn-on signal Q 4on Is low level and v is B Determining the ZVS detection signal Q when the point is 0 3ZVS Is low.
According to a second aspect of the present disclosure, a device for suppressing the problem of dynamic voltage-second imbalance of an active clamp converter is provided.
In one embodiment, the apparatus comprises: an acquisition unit for acquiring v B Point voltage value, switch tube Q 3 First on signal Q 3on1 And a switching tube Q 4 Turn-on signal Q of 4on (ii) a An analysis unit for analyzing v B Point voltage value and said turn-on signal Q 4on Analyzing and processing to determine the switch tube Q 3 ZVS detection signal Q of 3ZVS (ii) a An arithmetic unit for comparing the first turn-on signal Q 3on1 And said ZVS detection signal Q 3ZVS Performing AND operation to obtain the switching tube Q 3 Second turn-on signal Q 3on2 (ii) a A processing unit for generating the second turn-on signal Q by PWM 3on2 Processing to obtain a switching tube Q 3 Drive signal Q of 3GS To drive the switch tube Q 3 。
According to a third aspect of the present disclosure, a suppression circuit for an active clamp class converter dynamic voltage-second imbalance problem is provided.
In one embodiment, the circuit includes: switch tube Q 3 The ZVS detection module, the PWM generation module and the AND gate; the AND gate comprises two input terminals, v B The voltage of the point passes through the switch tube Q 3 ZVS detection module generates detection signal Q 3ZVS The PWM generating module generates a first opening signal Q 3on1 Another input terminal connected to AND gate, the detection signal Q 3ZVS And said first on signal Q 3on1 Generating a second on signal Q via the AND gate 3on2 Connected to said PWM generating module, said second turn-on signal Q 3on2 Generating Q via the PWM generation module 3 Drive signal Q of 3GS 。
In one embodiment, the switch tube Q 3 The ZVS detection module comprises: a first capacitor C 11 A second capacitor C 12 A first resistor R 11 A second resistor R 12 A first diode D 11 A second diode D 12 A third diode D 13 A fourth diode D 14 A fifth diode D 15 A first comparator U 11 A first monostable flip-flop and a first RS flip-flop RS 1 (ii) a The fifth diode D 15 Anode and power supply V CC Connected, a fifth diode D 15 Respectively with the second capacitor C 11 A second resistor R 12 A second diode D 12 Anode of (2), fourth diode D 14 Cathode, first diode D 11 Is connected to the anode of a second capacitor C 11 Another end of (a) and v B Voltage connection of the point, second diode D 12 Cathode of and a third diode D 13 Is connected to the positive input terminal of the first comparator U11 and the third diode D, respectively 13 Cathode, second resistor R 12 The other end of (2), a fourth diode D 14 Anode of, first capacitor C 11 Connected by a first capacitor C 11 The other end of which is grounded, a first diode D 11 Respectively with a first comparator U 11 And a first resistor R 11 Connected by a first resistor R 11 Is grounded, a first comparator U 11 The output of the first monostable flip-flop is connected with the input end of the first monostable flip-flop, and the output end of the first monostable flip-flop is connected with the RS trigger 1 Is connected.
In one embodiment, the switch tube Q 3 The ZVS detection module comprises: resistance voltage division sampling circuit and second comparator U 12 A second monostable trigger and a second RS trigger 2 (ii) a Resistance voltage division sampling circuit and second comparator U 12 Is connected to a second comparator U 12 The output of the first monostable flip-flop is connected with the input end of a first monostable flip-flop, and the output end of the first monostable flip-flop is connected with a first RS flip-flop RS 2 Is connected.
According to a third aspect of the present disclosure, there is provided an electronic device comprising a suppression circuit for dynamic voltage-second imbalance problem of an active clamp class converter as described above.
The method for suppressing the dynamic volt-second unbalance problem of the active clamp converterMethod and circuit by changing the switching tube Q 3 The driving signal realizes that the switching tube Q is switched from full load to no load and the peak value of the exciting inductance current is reduced to be below 0 3 The purpose of not switching on is achieved, and therefore the problem that the converter is not in operation when the converter is shut down due to the fact that the voltage of the clamping capacitor drops rapidly in the dynamic response process of the converter to trigger a protection mechanism is solved.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, like or corresponding reference characters designate like or corresponding parts.
Fig. 1 shows a schematic structure diagram of a dual-clamp ZVS buck-boost converter in the prior art;
FIG. 2 is a block diagram illustrating an implementation of a ZVS adaptive control method in the prior art;
FIG. 3 shows a waveform diagram of a prior art converter with volt-second imbalance;
FIG. 4 shows an experimental waveform of a prior art converter when a volt-second imbalance occurs;
fig. 5 shows a first schematic structural diagram of a suppression circuit for a dynamic voltage-second imbalance problem of an active clamp type converter according to an embodiment of the present disclosure;
FIG. 6 shows a switch tube Q according to an embodiment of the disclosure 3 A first circuit structure schematic diagram of the ZVS detection module;
FIG. 7 shows a switch tube Q according to an embodiment of the disclosure 3 A circuit structure schematic diagram II of the ZVS detection module;
fig. 8 shows a schematic implementation flow diagram of a method for suppressing a dynamic voltage-second imbalance problem of an active clamp converter according to an embodiment of the present disclosure;
FIG. 9 shows a switch tube Q according to an embodiment of the disclosure 3 A working waveform schematic diagram I of a circuit structure of the ZVS detection module;
FIG. 10 shows a switch tube Q according to an embodiment of the disclosure 3 A working waveform schematic diagram II of a circuit structure of the ZVS detection module;
fig. 11 is a first simulation waveform diagram illustrating a first method for suppressing the dynamic voltage-second imbalance problem of an active clamp converter according to an embodiment of the present disclosure;
fig. 12 shows a simulation waveform diagram ii of a method for suppressing the dynamic voltage-second imbalance problem of the active clamp converter according to the embodiment of the present disclosure;
fig. 13 shows a block schematic diagram of a suppression device for the problem of dynamic voltage-second imbalance of an active clamp converter according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
Fig. 5 is a schematic structural diagram of a circuit for suppressing a dynamic voltage-second imbalance problem of an active clamp converter according to an embodiment of the present disclosure, and as shown in fig. 5, the circuit includes: switch tube Q 3 The ZVS detection module, the PWM generation module and the AND gate; the AND gate comprises two inputs, v B The voltage of the point is transmitted through the switch tube Q 3 ZVS detection module generates detection signal Q 3ZVS Connected to one input of the AND gate, the PWM generation module generates a first turn-on signal Q 3on1 Connected to the other input of the AND gate, detecting a signal Q 3ZVS And a first on signal Q 3on1 Generating a second ON signal Q via an AND gate 3on2 Is connected toPWM generating module, second on signal Q 3on2 Generating Q via a PWM generation module 3 Drive signal Q of 3GS 。
The circuit discloses a suppression circuit for the problem of dynamic volt-second unbalance of an active clamp converter, which can solve the problem of clamp capacitor voltage V in the dynamic response process of the converter L The fast falling trigger protection shutdown problem, the circuit implementation is simple, the burden brought to a hardware structure and a software flow is small, and the influence on the efficiency of the converter is small.
FIG. 6 shows a switch tube Q according to an embodiment of the disclosure 3 The circuit structure of the ZVS detection module is schematically illustrated as a first.
In one embodiment, as shown in FIG. 6, the switch Q 3 The ZVS detection module comprises: a first capacitor C 11 A second capacitor C 12 A first resistor R 11 A second resistor R 12 A first diode D 11 A second diode D 12 A third diode D 13 A fourth diode D 14 A fifth diode D 15 A first comparator U 11 A first monostable trigger and a first RS trigger RS 1 (ii) a Fifth diode D 15 Anode of (2) and power supply V CC Connected, a fifth diode D 15 Respectively with a second capacitor C 11 A second resistor R 12 A second diode D 12 Anode of (2), fourth diode D 14 Cathode of (2), first diode D 11 Is connected to the anode of a second capacitor C 11 And the other end of (a) and v B Voltage connection of the point, second diode D 12 Cathode of and a third diode D 13 Is connected with the positive input terminal of the first comparator U11 and the third diode D respectively 13 Cathode, second resistor R 12 Another terminal of (1), a fourth diode D 14 Anode of (2), first capacitor C 11 Connected to a first capacitor C 11 Is grounded, a first diode D 11 Respectively with a first comparator U 11 And the first resistor R 11 Connected by a first resistor R 11 Is grounded, a first comparator U 11 Output of (2)Is connected with the input end of the first monostable trigger, and the output end of the first monostable trigger is connected with the RS trigger 1 Is connected.
FIG. 7 shows a switch tube Q according to an embodiment of the disclosure 3 The circuit structure schematic diagram of the ZVS detection module is two.
In one embodiment, as shown in FIG. 7, the switch Q 3 The ZVS detection module comprises: resistance voltage division sampling circuit and second comparator U 12 A second monostable trigger and a second RS trigger 2 (ii) a Resistance voltage division sampling circuit and second comparator U 12 Is connected to a second comparator U 12 The output of the first monostable flip-flop is connected with the input end of the first monostable flip-flop, and the output end of the first monostable flip-flop is connected with the RS trigger 2 Is connected.
Fig. 8 is a schematic flow chart illustrating an implementation process of a method for suppressing a dynamic voltage-second imbalance problem of an active clamp converter according to an embodiment of the present disclosure. As shown in fig. 8, the method includes: operation 101, get v B Point voltage value, switch tube Q 3 First turn-on signal Q of 3on1 And a switching tube Q 4 Turn-on signal Q of 4on (ii) a Operation 102, pair v B Point voltage value and turn-on signal Q 4on Analyzing and determining the switch tube Q 3 ZVS detection signal Q of 3ZVS (ii) a Operation 103, on the first on signal Q 3on1 And ZVS detection signal Q 3ZVS Performing AND operation to obtain the switching tube Q 3 Second on signal Q 3on2 (ii) a Operation 104, the second turn-on signal Q is generated by the PWM generation module 3on2 Processing to obtain a switching tube Q 3 Drive signal Q of 3GS To drive the switch tube Q 3 。
In operation 101, v B Point is a switch tube Q 3 And a switching tube Q 4 The connection point of (a); switch tube Q 3 First on signal Q 3on1 And a switching tube Q 4 Turn-on signal Q of 4on Switching tubes Q respectively generated by PWM modules in the prior art 3 And a switching tube Q 4 The drive signal of (1). In operation 102, the method proceeds by comparing the current v B Point voltage value and turn-on signal Q 4on Performing analysis processing, and when the analysis result is that the switch tube Q is satisfied 3 Under ZVS on condition, the ZVS detects the signal Q 3ZVS At high level, when the analysis result is that the switch tube Q is not satisfied 3 ZVS detection signal Q under ZVS ON condition 3ZVS Is low. In operation 103, the switch tube Q 3 Second on signal Q 3on2 To use the method disclosed by the embodiment of the disclosure, the switch tube Q is switched 3 Only when the first on signal Q is present 3on1 And ZVS detection signal Q 3ZVS When all are high level, determining the switch tube Q 3 Second on signal Q 3on2 High, otherwise low.
In one embodiment, operation 102 includes: at the on signal Q 4on Is low level and v B Determining ZVS detection signal Q when the point voltage value reaches the reference voltage 3ZVS Is at a high level; at the on signal Q 4on Is low level and v B When the point is 0, the ZVS detection signal Q is determined 3ZVS Is low.
Wherein the reference voltage may be a voltage value V of the closed-loop clamp capacitor L And dividing the voltage to obtain a corresponding value by a resistance voltage-dividing sampling circuit.
In order to better understand the above embodiments, two specific implementation scenarios are described below.
In one implementation scenario, the circuit shown in FIG. 6 is used as a switch transistor Q 4 In the on state, v B Point voltage is 0, comparator U 11 Negative terminal voltage u 11- Is a V CC -V D15 -V D11 In which V is D11 、V D15 Is a diode D 11 、D 15 Conducting voltage drop of, comparator U 11 Positive terminal voltage u 11+ Is a V CC -V D15 When the output of the comparator is high level; at the switching tube Q 4 At the moment of turn-off, if the peak value of the exciting inductance current is positive, the exciting current is applied to the switching tube Q 3 And Q 4 Parasitic capacitance C of 3 And C 4 Charging and discharging, v B The point voltage rises, the comparator U 11 Negative terminal voltage is V CC +v B -V D15 -V D11 Due to C 12 >>C 11 ，dv C11 /dt＝dv B /dt, comparator U 11 Positive terminal voltage u 11+ Is a V CC +v B -V D15 -R 12 C 11 dv B Dt, when R 12 C 11 dv B /dt>V D11 I.e. v B When the dot voltage rises faster, the comparator output is low, but when the comparator U rises faster 11 The positive terminal voltage drops to V CC +v B -V D12 -V D13 When the voltage is lower, the diode D 12 、D 13 The clamping circuit of the composition is clamped at V CC +v B -V D12 -V D13 ，V D12 、V D13 Is a diode D 12 、D 13 Conduction voltage drop of (1); when v is B When the point voltage rises to be basically unchanged, the comparator U 11 Positive terminal voltage is V CC +v B -V D15 Comparator U 11 Negative terminal voltage is V CC +v B -V D15 -V D11 When the output of the comparator is turned over to high level, the switching tube Q is indicated 3 With ZVS on condition, the monostable trigger gets the trigger signal and outputs high level to RS trigger 1 End S of, Q of the RS flip-flop output 3ZVS Changing to a high level; the working waveform of the circuit structure when the peak value of the exciting inductor current is greater than 0 is shown in fig. 9. If in the switch tube Q 4 When the exciting inductance current is negative at the moment of turn-off, v is B The point voltage is kept unchanged, the comparator output keeps high level, the monostable trigger can not obtain the trigger signal, the RS trigger outputs Q 3ZVS Keeping low level; at the switching tube Q 3 Moment of turn-off, v B The point voltage drops, the comparator U 11 Positive terminal voltage is V CC +v B -V D15 -R 12 C 11 dv B Dt, but when the comparator U 11 The positive terminal voltage rises to V CC +v B -V D15 +V D14 When the voltage is over, the voltage is controlled by the diode D 14 Clamped at V CC +v B -V D15 +V D14 ，V D14 Is a diode D 14 Conducting voltage drop of, comparator U 11 Negative terminal voltage is V CC +v B -V D15 -V D11 And the output of the comparator maintains high level, and the monostable trigger cannot obtain a trigger signal. When the switch tube Q 4 On-time, switch tube Q in digital controller 4 Turn-on signal Q of 4on At high, the signal is sent to the RS flip-flop RS 1 R terminal of (A), Q 3ZVS Reverting to a low level.
In another implementation scenario, the circuit shown in FIG. 7, comparator U 12 Negative terminal voltage v th1 Set as the voltage value V of the closed-loop clamp capacitor L The corresponding value obtained by voltage division of the resistor voltage-dividing sampling circuit in the figure is used as a switching tube Q 4 In the on state, v B Point voltage is 0, comparator U 12 Positive terminal voltage u 12+ Is 0, the comparator U 12 The output is low level; switch tube Q 4 Turning off, if the peak value of the exciting inductance current is positive, the exciting current is applied to the switching tube Q 3 And Q 4 Parasitic capacitance C of 3 And C 4 Charging and discharging, v B The point voltage rises when v B The point voltage value rises to V L Above, the switch tube Q 3 Having ZVS on condition, comparator U 12 The positive terminal voltage is greater than the negative terminal voltage v th1 The comparator output is turned to be high, the monostable trigger obtains a trigger signal and outputs high level to the RS trigger RS 2 End S of, Q of the RS flip-flop output 3ZVS Goes high if at the switch tube Q 4 When the exciting inductance current is negative at the moment of turn-off, v is B The point voltage is maintained unchanged, and the comparator U 12 The output maintains low level; when the switch tube Q 3 Off, v B The point voltage drops to a negative voltage v th1 The comparator output toggles low when below. When the switch tube Q 4 On-time, switch tube Q in digital controller 4 Turn-on signal Q of 4on At high, the signal is sent to the RS flip-flop RS 2 R terminal of (1), Q 3ZVS Reverting to a low level. FIG. 10 shows the peak value i of the exciting inductor current Lm_peak Greater than 0 the circuit is criticalA point operating waveform.
Fig. 11 and 12 show simulated waveform diagrams of a method for suppressing the dynamic voltage-second imbalance problem of an active clamp class converter according to an embodiment of the present disclosure. As shown in FIGS. 11 and 12, after the method of the present disclosure is adopted, when the converter is in full load and is in no load, the peak value i of the exciting inductor current is Lm_peak Continuously dropping, when it drops below 0, the switch tube Q 3 Without ZVS on condition, the switching tube Q in the period 3 The current of the exciting inductor is kept unchanged after reaching the peak value when the current is not switched on; when the current peak value of the exciting inductor rises to above 0 in the next switching period, the switching tube Q is switched on 3 And normal opening is performed under the ZVS opening condition. Voltage V of clamping capacitor in whole load shedding process L The phenomenon of sudden drop no longer occurs.
An embodiment of the present disclosure provides a device for suppressing a dynamic voltage-second imbalance problem of an active clamp converter, as shown in fig. 13, the device includes: an obtaining unit 1301 for obtaining v B Point voltage value, switch tube Q 3 First on signal Q 3on1 And a switching tube Q 4 Turn-on signal Q of 4on (ii) a An analysis unit 1302 for comparing v B Point voltage value and turn-on signal Q 4on Analyzing and processing to determine the switch tube Q 3 ZVS detection signal Q of 3ZVS (ii) a An arithmetic unit 1303 for applying the first turn-on signal Q 3on1 And ZVS detection signal Q 3ZVS Performing AND operation to obtain a switching tube Q 3 Second on signal Q 3on2 (ii) a A processing unit 1304 for generating the second turn-on signal Q by the PWM generation module 3on2 Processing to obtain a switching tube Q 3 Drive signal Q of 3GS To drive the switch tube Q 3 。
According to an embodiment of the present disclosure, the present disclosure also provides an electronic device including the above suppression circuit for the dynamic voltage-second imbalance problem of the active clamp type converter.
The detailed description and the advantageous effects of the electronic device according to the present disclosure refer to the above description of the suppression circuit for the dynamic voltage-second imbalance problem of the active clamp converter in fig. 6 and fig. 7, and are not repeated herein for brevity.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, and the present disclosure is not limited herein.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (7)
1. A method for suppressing the problem of dynamic volt-second unbalance of an active clamp type converter is characterized by comprising the following steps:
obtaining v B Point voltage value, switch tube Q 3 First on signal Q 3on1 And a switching tube Q 4 Turn-on signal Q of 4on ；
For v is to v B Point voltage value and said turn-on signal Q 4on Analyzing and processing to determine the switch tube Q 3 ZVS detection signal Q of 3ZVS ；
For the first open signal Q 3on1 And said ZVS detection signal Q 3ZVS Performing AND operation to obtain a switching tube Q 3 Second on signal Q 3on2 ；
The second opening signal Q is generated by a PWM generation module 3on2 Processing to obtain a switching tube Q 3 Drive signal Q of 3GS To drive the switch tube Q 3 。
2. The method of claim 1, wherein said pair of said v B Point voltage value and said turn-on signal Q 4on Analyzing and processing to determine the switch tube Q 3 ZVS detection signal Q 3ZVS The method comprises the following steps:
at the turn-on signal Q 4on Is low level and v is B Determining the ZVS detection signal Q when the point voltage value reaches the reference voltage 3ZVS Is at a high level;
at the turn-on signal Q 4on Is low level and said v B Determining the ZVS detection signal Q when the point is 0 3ZVS Is low.
3. An apparatus for suppressing a dynamic voltage-second imbalance problem of an active clamp type converter, the apparatus comprising:
an acquisition unit for acquiring v B Point voltage value, switch tube Q 3 First on signal Q 3on1 And a switching tube Q 4 Turn-on signal Q of 4on ；
An analysis unit for analyzing v B Point voltage value and said turn-on signal Q 4on Analyzing and processing to determine the switch tube Q 3 ZVS detection signal Q 3ZVS ；
An arithmetic unit for comparing the first turn-on signal Q 3on1 And said ZVS detection signal Q 3ZVS Performing AND operation to obtain the switching tube Q 3 Second on signal Q 3on2 ；
A processing unit for generating the second turn-on signal Q by the PWM generation module 3on2 Processing to obtain a switching tube Q 3 Drive signal Q of 3GS To drive the switch tube Q 3 。
4. A circuit for suppressing a dynamic volt-second imbalance problem of an active clamp type converter is characterized by comprising:
switch tube Q 3 The system comprises a ZVS detection module, a PWM generation module and an AND gate;
the AND gate comprises two input terminals, v B The voltage of the point passes through the switch tube Q 3 ZVS detection module generates detection signal Q 3ZVS The PWM generating module generates a first opening signal Q 3on1 Another input terminal connected to the AND gate, the detection signal Q 3ZVS And said first on signal Q 3on1 Generating a second on signal Q via the AND gate 3on2 Connected to said PWM generating module, said second turn-on signal Q 3on2 Generating Q via the PWM generation module 3 Drive signal Q of 3GS 。
5. The circuit of claim 4, wherein the switching tube Q 3 The ZVS detection module comprises:
a first capacitor C 11 A second capacitor C 12 A first resistor R 11 A second resistor R 12 A first diode D 11 A second diode D 12 A third diode D 13 A fourth diode D 14 A fifth diode D 15 A first comparator U 11 A first monostable flip-flop and a first RS flip-flop RS 1 ；
The fifth diode D 15 Anode and power supply V CC Connected, a fifth diode D 15 Respectively with a second capacitor C 11 A second resistor R 12 A second diode D 12 Anode of (2), fourth diode D 14 Cathode of (2), first diode D 11 Is connected to the anode of a second capacitor C 11 And the other end of (a) and v B Voltage connection of the point, second diode D 12 Cathode of and a third diode D 13 Is connected to a first comparator U 11 Respectively with a third diode D 13 Cathode, second resistance R 12 Another terminal of (1), a fourth diode D 14 Anode of, firstCapacitor C 11 Connected to a first capacitor C 11 The other end of which is grounded, a first diode D 11 Respectively with a first comparator U 11 And a first resistor R 11 Connected to a first resistor R 11 Is grounded, a first comparator U 11 The output of the first monostable flip-flop is connected with the input end of the first monostable flip-flop, and the output end of the first monostable flip-flop is connected with the RS trigger 1 Is connected.
6. The circuit of claim 4, wherein the switching tube Q 3 The ZVS detection module comprises:
resistance voltage division sampling circuit and second comparator U 12 A second monostable flip-flop and a second RS flip-flop RS 2 ；
Resistance voltage division sampling circuit and second comparator U 12 Is connected to a second comparator U 12 The output of the first monostable flip-flop is connected with the input end of the first monostable flip-flop, and the output end of the first monostable flip-flop is connected with the RS trigger 2 Is connected.
7. An electronic device, characterized in that the electronic device comprises: a suppression circuit for dynamic voltage-second imbalance problems of an active clamp class converter as claimed in any one of claims 4 to 6.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211203547.2A CN115632543A (en) | 2022-09-29 | 2022-09-29 | Method and circuit for inhibiting dynamic volt-second unbalance problem of active clamp converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211203547.2A CN115632543A (en) | 2022-09-29 | 2022-09-29 | Method and circuit for inhibiting dynamic volt-second unbalance problem of active clamp converter |
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