CN115632033A - Chip flip-chip bonding structure, preparation method thereof and chip packaging structure - Google Patents

Chip flip-chip bonding structure, preparation method thereof and chip packaging structure Download PDF

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Publication number
CN115632033A
CN115632033A CN202211127319.1A CN202211127319A CN115632033A CN 115632033 A CN115632033 A CN 115632033A CN 202211127319 A CN202211127319 A CN 202211127319A CN 115632033 A CN115632033 A CN 115632033A
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chip
substrate
underfill
area
filling material
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姜帅
甘志华
吴雷
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Beijing Qixing Huachuang Microelectronics Co ltd
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Beijing Qixing Huachuang Microelectronics Co ltd
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Priority to CN202211127319.1A priority Critical patent/CN115632033A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

The application relates to a flip chip bonding structure, a preparation method thereof and a chip packaging structure, wherein the flip chip bonding structure comprises a substrate, a chip and underfill, and at least one through hole penetrating through the substrate is arranged on a flip chip bonding area of the substrate; the chip is inversely welded on the substrate, and a glue filling area is formed between the chip and the substrate; underfill fills the underfill area and the through-holes. The method can improve the flowing speed of the filling material and effectively shorten the filling time; the flow of the filling material between the chip and the substrate gap can be regulated and controlled, and the generation of cavities in the glue filling area can be effectively reduced; the underfill in the through hole and the underfill in the underfill area are integrated, so that the adhesive force between the underfill and the substrate can be effectively increased, the redistribution effect of stress can be more obvious, and the reliability of flip chip bonding can be effectively improved; the deformation of the underfill can relieve mechanical stress generated by different thermal expansion coefficients of the chip and the substrate to a certain extent, so that the chip cannot be damaged due to thermal shock.

Description

Chip flip-chip bonding structure, preparation method thereof and chip packaging structure
Technical Field
The application relates to the technical field of microelectronic chip packaging, in particular to a flip chip bonding structure, a preparation method thereof and a chip packaging structure.
Background
The flip chip packaging can effectively reduce the length of the interconnection lead, increase the density of the I/O port, reduce the packaging size and improve the heat dissipation capacity of the chip. However, due to the large difference between the thermal expansion coefficients of the silicon chip and the organic substrate, the flip chip technology can only be applied to the ceramic substrate package for a long time. In order to make flip chip bonding applicable to organic substrate packaging, it is proposed to use a bottom underfill under the flip chip to reinforce the chip. Compared with the unfilled condition, the lower filler can reduce the stress level of the key welding spot by 0.1 to 0.25 and can prolong the fatigue life of the welding spot by 10 to 100 times.
The most common underfill filling method today is to flow the underfill between the chip and the substrate by capillary action, but the underfill flow problem is considered to be one of the bottlenecks of the flip chip process. Because the flow of the capillary underfill is generally slow and may not fill completely, resulting in voids in the package and non-uniformity of the resin/filler system. As integrated circuit process nodes continue to shrink, future flip chip packaging requirements include smaller bump pitch, smaller bump size, and larger chip size, which can cause capillary flow underfill processes to face significant challenges.
In order to solve the above problems, a non-flow type under packing has been proposed. This process is to apply underfill to the substrate, align and place the chip to the substrate, and then reflow to melt the solder to form the solder ball interconnects. The process avoids capillary flow of the lower filler, and combines the reflow of the tin soldering salient points and the curing of the lower filler into one step, thereby improving the production efficiency of the bottom filling process. However, this process requires a relatively high underfill material, requires a delayed curing capability and flux built-in capability for the underfill material, and also causes relatively severe voids due to outgassing from the underfill material, moisture in the substrate, or poor wetting during die attach, which may cause early failure of the device in a number of ways.
Another underfill process is to combine molding and underfill, called mold underfill. Mold underfill a transfer molding process is applied to flip chip packaging, filling the gap between the chip and the substrate with a mold compound, while encapsulating the entire chip. The process combines underfill and transfer molding into one step, which can reduce process time and improve mechanical stability. However, due to the poor fluidity of the molding compound, air is trapped under the chip, and a large cavity is formed, thereby affecting the reliability of the package.
In summary, the underfill flowing in the current flip-chip underfill process still has the problems of incomplete filling, voids and the like.
Disclosure of Invention
In order to reduce the phenomena that gaps between a chip and a substrate are not completely filled and cavities are easily generated, the application provides a flip chip bonding structure, a preparation method thereof and a chip packaging structure.
The application provides a flip chip bonding structure, a preparation method thereof and a chip packaging structure, which adopt the following technical scheme:
in a first aspect, a flip chip bonding structure includes:
the substrate is provided with at least one through hole penetrating through the substrate in a flip chip bonding area;
the chip is flip-chip welded on the substrate, and a glue filling area is formed between the chip and the substrate; and (c) a second step of,
and underfill, which fills the underfill area and the through hole.
By adopting the technical scheme, through the through holes arranged on the substrate, the filling material can flow into the glue filling area at the bottom of the chip under the action of air pressure by utilizing the negative pressure combined with the capillary action, so that the flowing speed of the filling material can be improved, and the filling time can be effectively shortened.
The position, the size and the number of the through holes are determined according to the size of the chip, the distribution position, the size, the distance and other parameters of the bonding pads, the flow of the filling material between the chip and the gap of the substrate can be regulated and controlled by adjusting the position, the size and the number of the through holes on the substrate, and the generation of cavities in the glue filling area can be effectively reduced.
After the filling material is filled in the glue filling area, the through holes on the substrate are also filled with the filling material, and after the filling material is solidified, the underfill in the through holes and the underfill in the glue filling area are integrated, so that the adhesive force between the underfill and the substrate can be effectively increased, the redistribution effect of stress can be more obvious, and the reliability of flip chip bonding can be effectively improved. The underfill is not arranged around the chip, so that the area of the substrate covered by the underfill can be saved, and the wiring area can be increased.
The underfill is formed after the filling material is cured, when the chip packaging structure is subjected to thermal shock, mechanical stress generated by the thermal expansion of the chip in the vertical direction is transmitted to the underfill, and the deformation of the underfill is not hindered at the through hole due to the existence of the through hole, so that the mechanical stress generated by the difference of the thermal expansion coefficients of the chip and the substrate can be removed to a certain extent by the deformation of the underfill in the through hole, and the chip cannot be damaged due to the thermal shock.
Optionally, the substrate is provided with a plurality of through holes in a flip-chip bonding area, and the opening density of the through holes decreases from the central area of the substrate to the edge area of the substrate.
By adopting the technical scheme, negative pressure is applied to the glue filling area, so that the filling materials around the glue filling area flow to the middle of the glue filling area, the generation of cavities can be reduced, and the filling time is shortened.
Optionally, the underfill is a thermally conductive adhesive.
Through adopting above-mentioned technical scheme, the heat accessible underfill that the chip produced transmits the underfill in the through-hole to the underfill that the underfill is regional to distribute away the heat, can improve the radiating efficiency of chip packaging structure below to the base plate.
Optionally, the underfill is disposed around the chip and around the underfill area.
By adopting the technical scheme, after the filling material is filled in the filling area, solidified underfill is remained around the chip. The underfill is formed after the filling material is cured, and when the chip packaging structure is subjected to thermal shock, the mechanical stress generated by the thermal expansion of the chip in the transverse direction is transferred to the underfill around the chip, so that the mechanical stress generated by the thermal expansion of the chip in the transverse direction can be relieved to a certain extent by the deformation of the underfill around the chip, and the chip cannot be damaged due to the thermal shock. When the underfill is a heat-conducting adhesive, the heat of the chip can be dissipated through the underfill around the chip.
In a second aspect, the present application further relates to a method for manufacturing a flip chip structure, comprising the following steps:
s1: providing a bearing seat;
s2: providing a substrate, forming at least one through hole on the substrate, and placing the substrate on the bearing seat to hollow out the through hole;
s3: providing a chip, flip-chip bonding the chip to the substrate, and forming a glue filling area between the chip and the substrate;
s4: adding a filling material around the glue filling area to seal the peripheral side of the glue filling area;
s5: applying negative pressure to the through hole under the substrate to make the filling material flow into the glue filling area under the action of atmospheric pressure;
s6: and after the filling material is filled in the glue filling area, curing the filling material in the glue filling area.
Through adopting above-mentioned technical scheme, compare in filling material and flow under capillary action, filling material's mobility is not good, leads to the filling time overlength, through be equipped with the through-hole on the base plate in this application, utilizes negative pressure to combine capillary action to make filling material flow into the filler area of chip bottom under the effect of atmospheric pressure, can improve filling material's flow speed, effectively shortens filling time.
The position, the size and the number of the through holes are determined according to the size of the chip, the distribution position, the size, the distance and other parameters of the bonding pads, the flow of the filling material between the chip and the gap of the substrate can be regulated and controlled by adjusting the position, the size and the number of the through holes on the substrate, and the generation of cavities in the glue filling area can be effectively reduced.
The filling material is filled around the glue filling area, so that the filling material has a sealing effect on the peripheral side of the glue filling area, and the peripheral side of the glue filling area is sealed by arranging the isolation layer on the peripheral side of the glue filling area.
After the filling material is filled in the glue filling area, the through holes on the substrate are also filled with the filling material, and after the filling material is solidified, the underfill in the through holes and the underfill in the glue filling area are integrated, so that the adhesive force between the underfill and the substrate can be effectively increased, the redistribution effect of stress can be more obvious, and the reliability of flip chip bonding can be effectively improved.
The filling material is solidified to form underfill, when the chip packaging structure is subjected to thermal shock, mechanical stress generated by the thermal expansion of the chip in the vertical direction is transmitted to the underfill, and the deformation of the underfill is not hindered at the through hole due to the existence of the through hole, so that the mechanical stress generated by the difference of the thermal expansion coefficients of the chip and the substrate can be relieved to a certain extent by the deformation of the underfill in the through hole; meanwhile, because the solidified underfill is remained around the chip, the mechanical stress generated by the thermal expansion of the chip in the transverse direction is transmitted to the underfill around the chip, so that the mechanical stress generated by the thermal expansion of the chip in the transverse direction can be relieved to a certain extent by the deformation of the underfill around the chip, and the chip cannot be damaged due to thermal shock.
Optionally, a plurality of through holes are formed in the flip chip bonding region of the substrate, and the forming density of the through holes decreases from the central region of the substrate to the edge region.
By adopting the technical scheme, negative pressure is applied to the glue filling area, so that the filling materials around the glue filling area all flow to the middle part of the glue filling area, the generation of cavities can be reduced, and the filling time is shortened; the density of the through holes in the edge area of the substrate is low, so that the loss of the filling material flowing out of the through holes can be reduced.
Optionally, the filling material is a heat-conducting glue.
Through adopting above-mentioned technical scheme, the heat accessible underfill that the chip produced transmits the underfill in the through-hole to the underfill that the underfill is regional to distribute away the heat, can improve the radiating efficiency of chip packaging structure below to the base plate.
Optionally, in step S5, while applying negative pressure to make the filling material flow into the glue filling area under the action of atmospheric pressure, continuously replenishing the filling material around the glue filling area, so as to keep the inventory of the filling material around the glue filling area in dynamic balance.
By adopting the technical scheme, the filling material always has a sealing effect on the peripheral side of the glue filling area, and the filling material is ensured to be smoothly filled in the glue filling area.
Optionally, the filling material is added around the chip, and a thickness of the chip between a top surface of the filling material attached to the outer sidewall of the chip and a bottom surface of the chip is 20% to 80% of a thickness of the chip.
By adopting the technical scheme, the filling material is ensured to always seal the peripheral side of the glue filling area.
Optionally, the height of the filling material decreases from the position close to the chip to the position far away from the chip, and the thickness of the filling material higher than the bottom surface of the chip is 0.2-1mm.
Through adopting above-mentioned technical scheme, avoid appearing the starving phenomenon around the filling area, guarantee that filling material plays sealed effect to filling area week side all the time.
In a third aspect, the present application further relates to a chip packaging structure, including the flip chip bonding structure as described in any one of the above.
By adopting the technical scheme, the flow speed of the filling material can be improved, the filling time is effectively shortened, and the generation of cavities is effectively reduced. The adhesive force between the underfill and the substrate is effectively increased, the redistribution effect of stress can be more obvious, and the reliability of flip chip bonding is effectively improved. The deformation of the underfill can relieve mechanical stress generated by thermal expansion of the chip to a certain extent, so that the chip cannot be damaged due to thermal shock.
In summary, the present application includes at least one of the following beneficial technical effects:
1. through the through holes arranged on the substrate, the filling material flows into the glue filling area at the bottom of the chip under the action of air pressure by utilizing the negative pressure and the capillary action, so that the flowing speed of the filling material can be improved, and the filling time can be effectively shortened. The flow of the filling material between the chip and the substrate gap can be regulated and controlled, and the generation of cavities in the glue filling area can be effectively reduced.
2. The filling material is filled around the glue filling area, so that the filling material has a sealing effect on the peripheral side of the glue filling area, the peripheral side of the glue filling area is sealed while the glue filling area is filled, the process steps are simplified, and the processing time is shortened.
3. After the filling material is solidified, the underfill in the through hole and the underfill in the underfill area are integrated, so that the adhesive force between the underfill and the substrate can be effectively increased, the redistribution effect of stress can be more obvious, and the reliability of flip chip bonding can be effectively improved.
4. The deformation of the underfill in the through hole can relieve mechanical stress generated by the difference of the thermal expansion coefficients of the chip and the substrate to a certain degree, and the deformation of the underfill around the chip can relieve the mechanical stress generated by the thermal expansion of the chip in the transverse direction to a certain degree, so that the chip can not be damaged due to thermal shock.
5. The filling material is heat-conducting glue, and the underfill in the heat accessible underfill area that the chip produced transmits to the through-hole to distribute away the heat, the underfill around the heat accessible chip of chip side distributes away the heat simultaneously, can improve the radiating efficiency of chip.
Drawings
FIG. 1 is a schematic view of steps S2-S3 in a method for manufacturing a flip chip structure in example 1 of the present application;
FIG. 2 is a cross-sectional view of the substrate and chip of FIG. 1;
fig. 3 is a schematic view of step S4 in the method for manufacturing a flip chip structure in example 1 of the present application;
FIG. 4 is a schematic structural view of a flip chip bonding structure of the chip in embodiment 2 of the present application;
FIG. 5 is a schematic structural view of a flip chip bonding structure of the chip in embodiment 4 of the present application;
fig. 6 is a schematic structural diagram of a through hole on a substrate in embodiment 5 of the present application.
Description of reference numerals: 1. a substrate; 11. a through hole; 2. a chip; 3. a glue filling area; 4. a filler material; 5. and (6) underfill.
Detailed Description
The present application is described in further detail below with reference to figures 1-6.
Example 1
The embodiment provides a method for preparing a flip chip bonding structure, which comprises the following steps:
s1: the bearing seat (not shown in the figure) is provided, the bearing seat plays a role in supporting the substrate 1, the flip chip bonding structure of the chip 2 is convenient to process, the bearing seat is made of rigid materials, deformation is not generated under the action of certain pressure, the shape of the bearing seat is not limited in the embodiment, and the bearing seat can be used for supporting the substrate 1 and enabling the substrate 1 to be hollowed out through the through hole 11.
S2: referring to fig. 1 and 2, a substrate 1 is provided, at least one through hole 11 penetrating through the substrate 1 is formed in a flip chip bonding area of the substrate 1, the through hole 11 can be cleaned after the through hole is formed by mechanical punching or laser punching, and the substrate 1 is placed on a bearing seat to hollow out the through hole 11.
S3: providing a chip 2, flip-chip-welding the chip 2 on a substrate 1, fixedly connecting a joint point of a source electrode and a drain electrode below the chip 2 with a wiring point on the substrate 1 in a solder ball welding mode, cleaning soldering flux after welding, and forming a glue filling area 3 between the chip 2 and the substrate 1.
S4: referring to fig. 3, a filler 4 is added around the underfill region 3 to seal the periphery of the underfill region 3, i.e., the height of the filler around the underfill region 3 is higher than the bottom surface of the chip 2. The material of the underfill 5 commonly used in the art can be selected as the filling material 4, and preferably, the filling material with better thermal conductivity is selected from the commonly used materials of the underfill 5.
S5: applying a negative pressure to the through hole 11 under the substrate 1 causes the filling material 4 to flow into the glue filling area 3. The filling material 4 is continuously supplemented to the periphery of the glue filling area 3 while the filling material 4 flows into the glue filling area 3 by applying negative pressure, so that the stock of the filling material 4 around the glue filling area 3 is kept in dynamic balance, the filling material 4 can always play a role in sealing the periphery of the glue filling area 3, and the filling material 4 is ensured to be smoothly filled into the glue filling area 3.
The positions, sizes and number of the through holes 11 are designed according to parameters such as the area of the chip 2, the distribution position, size and spacing of the bonding pads, the viscosity of the used filling adhesive, the required filling rate and the like, so that dead corners in the filling adhesive area 3 are avoided, and the filling material 4 is ensured to flow to all corners of the filling adhesive area 3 under the action of negative pressure.
In an optional embodiment, the number of the through holes 11 may be one, and the through holes 11 are disposed in the middle of the underfill area 3, in a preferred embodiment, the number of the through holes 11 may be multiple, the opening density of the through holes 11 decreases from the central area to the edge area of the substrate 1, and negative pressure is applied to the underfill area 3, so that the filling material around the underfill area 3 flows to the middle of the underfill area 3, thereby reducing the generation of voids and shortening the filling time.
In order to ensure the tightness of the glue filling area 3, a filling material 4 is added around the chip 2. If the height of the filling material 4 around the underfill area 3 is too high to exceed the top surface of the chip 2, the filling material 4 will flow onto the chip 2, which may damage the chip 2 during subsequent cleaning of the filling material 4. If the amount of the filler 4 remaining around the underfill region 3 is too small, a negative pressure is applied to the through hole 11 below the substrate 1 to cause the filler 4 to flow into the underfill region 3, and then the phenomenon of underfill tends to occur around the underfill region 3, failing to achieve the sealing effect.
Therefore, the distance a between the top surface of the filling material 4 attached to the outer sidewall of the chip 2 and the bottom surface of the chip 2 is 20% -80% of the thickness b of the chip 2, so that the filling material 4 is ensured to always seal the peripheral side of the glue filling region 3, and the filling material 4 is prevented from flowing onto the chip 2. The height of the filling material 4 is reduced from the direction close to the chip 2 to the direction far away from the chip 2, the thickness c of the filling material 4 higher than the bottom surface of the chip 2 is 0.2-1mm, and the filling material 4 is guaranteed to play a sealing role on the peripheral side of the glue filling area 3 all the time.
S6: after the underfill area 3 is filled with the underfill material 4, the underfill material 4 in the underfill area 3 is cured to form an underfill 5. When the glue adding amount around the glue filling area 3 is the same as the glue discharging amount of the through hole 11, it can be judged that the glue filling area 3 is filled with the filling material 4. After curing the filling material 4, the cured underfill 5 around the chip 2 may be removed.
Through adopting above-mentioned technical scheme, compare in filling material 4 and flow under capillary action, filling material 4's mobility is not good, leads to the filling time overlength, through being equipped with through-hole 11 on base plate 1 in this application, utilizes negative pressure to combine capillary action to make filling material 4 flow into the underfill region 3 of chip 2 bottom under the effect of atmospheric pressure, can strengthen filling material 4's mobility, effectively shortens filling time.
The positions, the sizes and the number of the through holes 11 are determined according to the parameters such as the size of the chip 2, the distribution position, the size and the distance of the bonding pads, the flow of the filling material 4 between the chip 2 and the gap of the substrate 1 can be regulated and controlled by regulating the positions, the sizes and the number of the through holes 11 on the substrate 1, and the generation of cavities in the glue filling area 3 can be effectively reduced.
The filling material 4 is filled around the glue filling area 3, so that the filling material 4 plays a role in sealing the peripheral side of the glue filling area 3, and the peripheral side of the glue filling area 3 is sealed by arranging the isolation layer on the peripheral side of the glue filling area 3.
After the filling material 4 is filled in the glue filling area 3, the through hole 11 on the substrate 1 is also filled with the filling material 4, and after the filling material 4 is solidified, the underfill 5 in the through hole 11 and the underfill 5 in the glue filling area 3 are integrated, so that the adhesive force between the underfill 5 and the substrate 1 can be effectively increased, the redistribution effect of stress can be more obvious, and the reliability of flip chip bonding can be effectively improved.
After the filling material 4 is cured, when the chip 2 package structure is subjected to thermal shock, the mechanical stress generated in the vertical direction by the thermal expansion of the chip 2 is transmitted to the underfill 5, and due to the existence of the through hole 11, the deformation of the underfill 5 is not hindered at the through hole 11, so that the mechanical stress generated in the vertical direction by the thermal expansion of the chip 2 can be removed to a certain extent by the deformation of the underfill 5 in the through hole 11. Meanwhile, because the solidified underfill 5 remains around the chip 2, the mechanical stress generated by the thermal expansion of the chip 2 in the transverse direction is transferred to the underfill 5 around the chip 2, so that the mechanical stress generated by the thermal expansion of the chip 2 in the transverse direction can be removed to a certain extent by the deformation of the underfill 5 around the chip 2, and the whole structure of the package structure of the chip 2 is not damaged by thermal shock.
Example 2
The embodiment of the application discloses a flip chip bonding structure. Referring to fig. 4, the flip chip bonding structure includes a substrate 1, a chip 2, and an underfill 5.
The substrate 1 may be made of, but not limited to, an inorganic material such as a wafer, glass, ceramic, quartz, silicon carbide, or alumina, or an organic material such as epoxy resin or polyurethane. The substrate 1 is provided with at least one through hole 11, and the shape, size and number of the through holes 11 are not limited. The chip 2 is inversely welded on the substrate 1, the joint point of the source electrode and the drain electrode below the chip 2 is fixedly connected with the wiring point on the substrate 1 in a solder ball welding mode, and compared with a bonding mode, the solder ball welding mode greatly reduces the conduction impedance from the drain electrode and the source electrode of the device to the substrate 1 because a bonding wire is eliminated, and greatly reduces the parasitic influence caused by the bonding wire.
An underfill area 3 is formed between the chip 2 and the substrate 1, and the underfill 5 fills the underfill area 3 and the through hole 11. Through the through hole 11 arranged on the substrate 1, the filling material 4 can flow into the glue filling area 3 at the bottom of the chip 2 under the action of air pressure by utilizing the combination of negative pressure and capillary action, so that the flowability of the filling material 4 can be enhanced, and the filling time can be effectively shortened.
The positions, sizes and number of the through holes 11 can be designed according to parameters such as the size of the chip 2, the distribution position, the size and the distance of the bonding pads, one through hole 11 or a plurality of through holes 11 are arranged, dead angles generated in the glue filling area 3 are avoided due to the arrangement of the positions, the sizes and the number of the through holes 11, and the filling material 4 is enabled to flow to all corners of the glue filling area 3 under the action of negative pressure.
Through adjusting the position, size and quantity of through-hole 11 on base plate 1, can regulate and control the flow of filler material 4 between chip 2 and base plate 1 gap, can effectively reduce the production of cavity in the filler region 3.
In this embodiment, the through hole 11 is disposed below the middle of the glue filling area 3, and negative pressure is applied to the glue filling area 3, so that the filling material around the glue filling area 3 flows to the middle of the glue filling area 3, thereby reducing the generation of voids and shortening the filling time.
After the filling material 4 is filled in the glue filling area 3, the through hole 11 on the substrate 1 is also filled with the filling material 4, and after the filling material 4 is solidified, the underfill 5 in the through hole 11 and the underfill 5 in the glue filling area 3 are integrated, so that the adhesive force between the underfill 5 and the substrate 1 can be effectively increased, the redistribution effect of stress can be more obvious, and the reliability of flip chip bonding can be effectively improved.
The underfill 5 remaining around the chip 2 is removed, and the area of the substrate 1 covered with the adhesive can be saved, so that the wiring area can be increased.
After the filling material 4 is cured, when the chip 2 package structure is subjected to thermal shock, the mechanical stress generated by the thermal expansion of the chip 2 in the vertical direction is transmitted to the underfill 5, and due to the existence of the through hole 11, the deformation of the underfill 5 is not hindered in the through hole 11, so that the mechanical stress generated by the thermal expansion of the chip 2 in the vertical direction can be removed to a certain extent by the deformation of the underfill 5 in the through hole 11, and the whole structure of the chip 2 package structure cannot be damaged due to the thermal shock.
Example 3
Embodiment 3 is different from embodiment 2 in that the underfill 5 is a thermally conductive adhesive, and may be, but is not limited to, an epoxy resin adhesive, a thermally conductive silicone adhesive, or the like with good thermal conductivity. The heat generated by the chip 2 can be transferred to the underfill 5 in the through hole 11 through the underfill 5 in the underfill area 3, so that the heat can be dissipated, and the efficiency of the chip 2 packaging structure for dissipating heat below the substrate 1 can be improved.
Example 4
Referring to fig. 5, embodiment 4 is different from embodiment 3 in that underfill 5 is provided around the chip 2 and around the underfill area 3, and after the underfill area 3 is filled with the underfill 4, the cured underfill 4 remains around the chip 2, and the underfill 4 around the chip 2 is less and does not need to be cleaned. After the filling material 4 is cured, the underfill 5 remains around the chip 2, and when the chip 2 package structure is subjected to thermal shock, the mechanical stress generated in the transverse direction by the thermal expansion of the chip 2 is transmitted to the underfill 5 around the chip 2, so that the mechanical stress generated in the transverse direction by the thermal expansion of the chip 2 can be removed to a certain extent by the deformation of the underfill 5 around the chip 2, and the chip is not damaged by the thermal shock. While the heat of the chip 2 can be dissipated through the underfill 5 around the chip 2.
Example 5
Referring to fig. 6, the difference between embodiment 5 and embodiment 2 is that a plurality of through holes 11 are formed in the substrate 1, the through holes 11 are distributed in a cross shape, the through holes 11 centrally arranged in the middle of the substrate 1 are opposite to the middle of the glue filling area 3, and negative pressure is applied to the glue filling area 3, so that the filling material around the glue filling area 3 flows to the middle of the glue filling area 3, thereby reducing the generation of voids and shortening the filling time. In other embodiments, the through holes 11 may also be radially distributed from the axis of the substrate 1. The density of the through holes 11 in the central area of the substrate 1 is high, so as to enhance the flow of the filling material 4 from the edge of the glue filling area 3 to the central area, improve the filling effect of the filling material 4 and shorten the filling time.
The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims (10)

1. A flip chip bonding structure, comprising:
the substrate (1), the substrate (1) is provided with at least one through hole (11) penetrating through the substrate (1) in a flip chip bonding area;
the chip (2) is in flip chip bonding to the substrate (1), and a glue filling area (3) is formed between the chip (2) and the substrate (1); and the number of the first and second groups,
and the underfill (5) is filled in the underfill area (3) and the through hole (11).
2. The flip chip bonding structure of claim 1, wherein the substrate (1) is provided with a plurality of through holes (11) in a flip chip bonding region, and the opening density of the through holes (11) decreases from a central region to an edge region of the substrate (1).
3. The flip chip bonding structure according to claim 1 or 2, wherein the underfill (5) is a thermally conductive adhesive; and/or the presence of a gas in the gas,
the underfill (5) is arranged around the chip (2) and around the underfill area (3).
4. A preparation method of a flip chip bonding structure is characterized by comprising the following steps:
s1: providing a bearing seat;
s2: providing a substrate (1), forming at least one through hole (11) in the substrate (1), and placing the substrate (1) on the bearing seat to hollow out the through hole (11);
s3: providing a chip (2), flip-chip bonding the chip (2) to the substrate (1), and forming a glue filling area (3) between the chip (2) and the substrate (1);
s4: adding a filling material (4) around the glue filling area (3) to seal the peripheral side of the glue filling area (3);
s5: applying a negative pressure to the through hole (11) below the substrate (1) to make the filling material (4) flow into the glue filling area (3) under the action of atmospheric pressure;
s6: and after the filling material (4) fills the glue filling area (3), curing the filling material (4) in the glue filling area (3).
5. The method for manufacturing a flip chip bonded structure according to claim 4, wherein in step S2, a plurality of through holes (11) are formed in the flip chip bonding region of the substrate (1), and the forming density of the through holes (11) decreases from the central region to the edge region of the substrate (1).
6. The method for manufacturing a flip chip bonded structure according to claim 4, wherein the filling material (4) is a thermally conductive paste.
7. The method of manufacturing a flip chip bonded structure according to claim 4, wherein in step S5, the filling material (4) is continuously replenished around the glue filling region (3) while the filling material (4) is flowed into the glue filling region (3) under the action of atmospheric pressure by applying negative pressure, so that the inventory of the filling material (4) around the glue filling region (3) is kept in dynamic balance.
8. The method for manufacturing the flip chip bonding structure according to any one of claims 4 to 7, wherein the filling material (4) is added around the chip (2), and the distance between the top surface of the filling material (4) attached to the outer sidewall of the chip (2) and the bottom surface of the chip (2) is 20 to 80 percent of the thickness of the chip (2).
9. The method for manufacturing the flip chip bonding structure according to claim 8, wherein the height of the filling material (4) is decreased from the position close to the chip (2) to the position far away from the chip (2), and the thickness of the filling material (4) with the height higher than the bottom surface of the chip (2) is 0.2-1mm.
10. A chip package structure comprising the flip chip bonding structure according to any one of claims 1 to 3.
CN202211127319.1A 2022-09-16 2022-09-16 Chip flip-chip bonding structure, preparation method thereof and chip packaging structure Pending CN115632033A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116093039A (en) * 2023-03-01 2023-05-09 上海韬润半导体有限公司 Chip packaging structure and packaging method
CN116154609A (en) * 2023-04-04 2023-05-23 深圳市光为光通信科技有限公司 Photoelectric co-packaging method based on VCSEL (vertical cavity surface emitting laser) laser

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US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
JP2007019197A (en) * 2005-07-07 2007-01-25 Apic Yamada Corp Wiring board, underfill method and semiconductor device
US20090229513A1 (en) * 2008-03-12 2009-09-17 International Business Machines Corporation Underfill Air Vent for Flipchip BGA
US20110169157A1 (en) * 2010-01-13 2011-07-14 Wen-Jeng Fan Substrate and flip chip package with gradational pad pitches

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Publication number Priority date Publication date Assignee Title
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
JP2007019197A (en) * 2005-07-07 2007-01-25 Apic Yamada Corp Wiring board, underfill method and semiconductor device
US20090229513A1 (en) * 2008-03-12 2009-09-17 International Business Machines Corporation Underfill Air Vent for Flipchip BGA
US20110169157A1 (en) * 2010-01-13 2011-07-14 Wen-Jeng Fan Substrate and flip chip package with gradational pad pitches

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116093039A (en) * 2023-03-01 2023-05-09 上海韬润半导体有限公司 Chip packaging structure and packaging method
CN116154609A (en) * 2023-04-04 2023-05-23 深圳市光为光通信科技有限公司 Photoelectric co-packaging method based on VCSEL (vertical cavity surface emitting laser) laser

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