CN115629445A - Write field splicing structure and process for large-scale silicon-based photonic chip design - Google Patents
Write field splicing structure and process for large-scale silicon-based photonic chip design Download PDFInfo
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- CN115629445A CN115629445A CN202211478745.XA CN202211478745A CN115629445A CN 115629445 A CN115629445 A CN 115629445A CN 202211478745 A CN202211478745 A CN 202211478745A CN 115629445 A CN115629445 A CN 115629445A
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/1228—Tapered waveguides, e.g. integrated spot-size transformers
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/131—Integrated optical circuits characterised by the manufacturing method by using epitaxial growth
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12035—Materials
- G02B2006/12038—Glass (SiO2 based materials)
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
- G02B2006/12176—Etching
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
- G02B2006/12178—Epitaxial growth
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention discloses a write field splicing structure and a process for large-scale silicon-based photonic chip design, which are used for communicating optical signals of subsystems in adjacent maximum exposure areas, and comprise tapered waveguides connected with output waveguides of the subsystems, alignment marks arranged in the maximum exposure areas where the subsystems are located and connecting waveguides, wherein the connecting waveguides are used for connecting the tapered waveguides in the adjacent maximum exposure areas, optical signals output by the subsystems through the waveguides are coupled to the connecting waveguides through the tapered waveguides, then are coupled to the tapered waveguides in the adjacent exposure areas from the connecting waveguides, and finally the optical signals are transmitted to another subsystem. The invention breaks through the limitation of the maximum exposure area, prepares the ultra-large-scale silicon-based photonic chip, reduces the photoelectric packaging difficulty of the silicon-based photonic chip, has high optical transmission efficiency, has low requirement on the line width of the process and has high process tolerance.
Description
Technical Field
The invention relates to the technical field of large-scale silicon-based photonic chip design, in particular to a write field splicing structure and a write field splicing process for large-scale silicon-based photonic chip design.
Background
In recent years, due to the advantages of compatibility of CMOS processes, large-scale integration, low cost, and the like, silicon-based photonics has become a hot spot for research by researchers. Silicon-based photonics has important application prospects in the fields of optical signal exchange, photon computation, optical phased arrays, microwave photonic systems and the like, in addition to photonic transceivers for communication. With the development of these fields, the integration of silicon-based photonic devices on an increasingly large scale is becoming a highly interesting research direction. In the fabrication of various silicon-based photonic chips, uv lithography is an essential and important process step. However, the design size of silicon-based photonic chips cannot be typically larger than 2-3cm, limited by the maximum exposure area of the flow foundry uv lithography apparatus. This limits the integration of silicon-based photonic devices on a larger scale. How to break through the limitation and communicate the optical signals between the adjacent maximum exposure areas becomes a problem to be solved at present.
Disclosure of Invention
The invention aims to provide a write field splicing structure and a write field splicing process for large-scale silicon-based photonic chip design, so as to overcome the defects in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
the invention discloses a write field splicing structure for large-scale silicon-based photonic chip design, which is used for communicating optical signals of subsystems in adjacent maximum exposure areas, and comprises a tapered waveguide connected with an output waveguide of the subsystem, an alignment mark arranged in the maximum exposure area where the subsystem is located and a connecting waveguide, wherein the connecting waveguide is used for connecting the tapered waveguide in the adjacent maximum exposure area, an optical signal output by the subsystem through the waveguide is coupled to the connecting waveguide through the tapered waveguide, then is coupled to the tapered waveguide in the adjacent exposure area from the connecting waveguide, and finally is transmitted to another subsystem.
Preferably, the tapered waveguide has a linear shape including, but not limited to, linear and parabolic shapes.
Preferably, the structure of the alignment mark is determined according to design requirements, and specifically includes a cross alignment mark.
Preferably, the material of the tapered waveguide is a silicon material, and the material of the connecting waveguide is a material with a refractive index larger than that of SiO 2 The material of (1).
Preferably, the connecting waveguide is a straight waveguide or a symmetrical tapered waveguide.
Preferably, the connection waveguide and the tapered waveguide are separated by SiO 2 A layer on top of the connection waveguide having SiO 2 And (4) an upper cladding layer.
The invention discloses a write field splicing process for large-scale silicon-based photonic chip design, which comprises the following steps:
s1: preparing a structure of a silicon material layer, wherein the structure comprises a subsystem and an output waveguide, a tapered waveguide and an alignment mark of the subsystem;
s2: growing SiO on the prepared silicon material layer 2 A layer;
s3: carrying out a flattening process, and growing a material for preparing the connecting waveguide after the flattening process;
s4: by means of the alignment mark structure b, a connecting waveguide is prepared after photoetching and etching processes;
s5: growing SiO on top of connecting waveguide 2 And (4) an upper cladding layer.
Preferably, the process can be carried out after flow sheet, and the process flow after flow sheet can be replaced by the following steps:
p1, removing SiO with specified thickness in the region where the connecting waveguide is positioned by etching 2 A layer;
p2, growing a material with a specified thickness for preparing the connecting waveguide;
p3, preparing a connecting waveguide by means of the alignment mark structure b through photoetching and etching processes;
p4, growing SiO on top of the connecting waveguide 2 And (4) an upper cladding layer.
The invention has the beneficial effects that:
1. the invention breaks through the limitation of the maximum exposure area and prepares the ultra-large scale silicon-based photonic chip;
2. the photoelectric packaging difficulty of the silicon-based photonic chip is reduced: the area of the photonic chip is increased, and the photoelectric packaging difficulty of the photonic chip is reduced;
3. has high light transmission efficiency: the optical transmission efficiency close to 100% can be realized theoretically thanks to the high optical field coupling efficiency of the coupling mode theory;
4. the line width requirement on the process is low: smaller line width means higher process requirements, and the invention can realize high optical transmission efficiency under larger process line width;
5. with high process tolerances: in the process of implementing the process, certain errors exist. For the proposed structure, the alignment between the tapered waveguide structure and the connecting waveguide and the spacing between the two are two important parameters. The design can make the process error of the two parameters have less influence on the transmission efficiency of the optical transmission, namely, the design has high process tolerance.
Drawings
FIG. 1 is a schematic diagram of a write field stitching scheme proposed by the present invention;
FIG. 2 is a schematic diagram of an embodiment of the present invention;
FIG. 3 shows different Si 3 N 4 And the optical transmission efficiency of the TE mode under the alignment deviation of the Si waveguide;
FIG. 4 shows different Si 3 N 4 And the optical transmission efficiency of TE mode at the interval of Si waveguide.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood, however, that the description herein of specific embodiments is only intended to illustrate the invention and not to limit the scope of the invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
As shown in FIG. 1, an embodiment of the present invention provides a method forThe write field splicing structure designed by the large-scale silicon-based photonic chip utilizes a certain structure to carry out optical signal communication on subsystems in adjacent maximum exposure areas, wherein the number of the maximum exposure areas can be adjusted according to needs, and specifically, the structure for the optical signal communication comprises a structure a, a structure b and a structure c, wherein the structure a is a tapered waveguide structure, the linear type of the structure a can be linear, parabolic or other designed linear types, and the structure a is connected with the output waveguide of the subsystems; the structure b is an alignment mark, can be a cross alignment mark determined according to requirements and is arranged in the maximum exposure area where the subsystem is located; the structure c is a waveguide structure, is positioned in the region between two adjacent subsystems, can be a straight waveguide or a symmetrical tapered waveguide with a certain linear shape, and is made of a material with a refractive index larger than that of SiO 2 The material of (a); a layer of SiO is arranged between the structure a and the structure c 2 The material with the thickness determined according to actual needs and the top of the structure c is provided with SiO 2 And (4) an upper cladding layer.
The schematic diagram of the write field splicing scheme is shown in fig. 1, in which a dashed box represents a maximum exposure area, and the connection of two maximum exposure areas is illustrated in the diagram, and the practical application is not limited to two. According to the scheme, according to a coupled mode theory, an optical signal output by a subsystem a through a waveguide is coupled to a structure c through the structure a, then is coupled to the structure a in an adjacent exposure area from the structure c, and finally is transmitted to a subsystem b; and vice versa. This enables optical signal communication between two subsystems of adjacent maximum exposure areas.
The embodiment of the invention also provides a write field splicing process for designing the large-scale silicon-based photonic chip, which comprises the following specific process implementation processes: firstly, a structure of a silicon material layer is prepared, wherein the structure comprises a subsystem a, an output waveguide, a structure a and a structure b, and the preparation of the layer structure is limited by the maximum exposure area. Then, siO with a certain thickness is grown 2 And (3) a layer. After the planarization process, a certain thickness of material b is grown. And then, with the help of the alignment mark structure b, preparing a structure c after photoetching, etching and other processes. It is clear that the exposure area is smaller than the maximum exposure area. Finally growing SiO 2 And (4) an upper cladding layer.
At present, the tape-out foundry has not developed the above-described write field splicing scheme, which requires the self-preparation of structure c. The specific process implementation process is as follows: firstly, in the region of the structure c, removing SiO with a certain thickness by etching 2 And (3) a layer. Next, a certain thickness of material b is grown. And then, with the help of the alignment mark structure b, preparing a structure c after photoetching, etching and other processes. Finally growing SiO 2 And (4) an upper cladding layer.
The structure diagram and specific parameters of the embodiment of the invention are shown in fig. 2, and corresponding to the name in fig. 1, the material b is selected from Si 3 N 4 A material; structure a is a linear tapered waveguide structure with a thickness of 0.22 μm and tip and waveguide widths of 0.18 and 0.5 μm, respectively; the structure c is a straight waveguide structure, the thickness is 0.35 mu m, and the width is 2 mu m; the distance between the two was 0.25. Mu.m. Through simulation optimization, when the length of the structure a is 110 μm, the TE mode light transmission efficiency from the input of the Si waveguide at the left end to the output of the Si waveguide at the right end is the maximum, and is 99.17%. The minimum line width of the Si structure of the embodiment of the invention is 0.18 mu m, and Si 3 N 4 The minimum line width of the structure is 2 mu m, and the sizes greatly reduce the process difficulty of micro-nano processing centers of flow film generation factories and common scientific research units.
FIG. 3 shows Si 3 N 4 And the influence of the alignment deviation of the Si waveguide on the TE mode optical transmission efficiency, it can be seen that the optical transmission efficiency is decreased by only about 3.45% when the alignment deviation is 0.5 μm. FIG. 4 shows Si 3 N 4 And the influence of the interval deviation with the Si waveguide on the TE mode light transmission efficiency, it can be seen that the light transmission efficiency is decreased by about 2.27% at the maximum within a range of the interval deviation ± 0.04 μm. At present, the alignment precision of a photoetching machine in a flow film factory is below 0.1 mu m, and even for the micro-nano processing conditions of common scientific research units, the highest alignment precision of laser direct writing equipment can also reach 0.1 mu m. For the control of the interval between the two, the current process condition can be controlled within the range of +/-0.04 μm. Therefore, the structural design and parameters of the present embodiment have high process tolerance, and the optical transmission efficiency can be maintained under the current process conditions and levels.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents or improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A write field splicing structure for large-scale silicon-based photonic chip design is used for carrying out optical signal communication on subsystems in adjacent maximum exposure areas, and is characterized in that: the system comprises a tapered waveguide connected with an output waveguide of a subsystem, an alignment mark arranged at the maximum exposure area of the subsystem, and a connecting waveguide used for connecting the tapered waveguides of the adjacent maximum exposure areas, wherein an optical signal output by the subsystem through the waveguide is coupled to the connecting waveguide through the tapered waveguide, then coupled to the tapered waveguide in the adjacent exposure area from the connecting waveguide, and finally transmitted to another subsystem.
2. The write field mosaic for a large scale silicon-based photonic chip design of claim 1, wherein: the linear form of the tapered waveguide includes, but is not limited to, linear and parabolic.
3. The write field mosaic structure for large scale silicon-based photonic chip design according to claim 1, wherein: the structure of the alignment mark is determined according to design requirements, and specifically comprises a cross alignment mark.
4. The write field mosaic structure for large scale silicon-based photonic chip design according to claim 1, wherein: the material of the tapered waveguide is silicon material, and the material of the connecting waveguide is selected to have refractive index larger than SiO 2 The material of (1).
5. The write field mosaic structure for large scale silicon-based photonic chip design according to claim 1, wherein: the connecting waveguide is a straight waveguide or a symmetrical conical waveguide.
6. The write field mosaic structure for large scale silicon-based photonic chip design according to claim 1, wherein: siO is arranged between the connecting waveguide and the tapered waveguide 2 A layer on top of the connection waveguide having SiO 2 And (4) an upper cladding layer.
7. A write field splicing process for large-scale silicon-based photonic chip design is characterized in that: the process comprises the following steps:
s1: preparing a structure of a silicon material layer, wherein the structure comprises a subsystem and an output waveguide, a tapered waveguide and an alignment mark of the subsystem;
s2: growing SiO on the prepared silicon material layer 2 A layer;
s3: carrying out a flattening process, and growing a material for preparing the connecting waveguide after the flattening process;
s4: by means of the alignment mark, preparing a connecting waveguide after photoetching and etching processes;
s5: growing SiO on top of connecting waveguide 2 And (4) an upper cladding layer.
8. The write field tiling process for large scale silicon-based photonic chip design according to claim 7, wherein: the implementation of the process can be carried out after flow sheet, and the process flow after flow sheet can be replaced by the following steps:
p1, in the region where the connecting waveguide is located, removing SiO with a specified thickness by etching 2 A layer;
p2, growing a material with a specified thickness for preparing the connecting waveguide;
p3, by means of the alignment mark, preparing and obtaining a connecting waveguide after photoetching and etching processes;
p4, growing SiO on the top of the connecting waveguide 2 And (4) an upper cladding layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6517997B1 (en) * | 1999-05-29 | 2003-02-11 | Bookham Technology Plc | Production of an integrated optical device |
| US20110267594A1 (en) * | 2010-04-29 | 2011-11-03 | Samsung Electronics Co., Ltd. | Maskless exposure apparatus and stitching exposure method using the same |
| CN109143466A (en) * | 2018-08-31 | 2019-01-04 | 武汉光迅科技股份有限公司 | A kind of hybrid integrated silicon optical chip, optical device and chip manufacture method |
| CN111983899A (en) * | 2020-06-11 | 2020-11-24 | 百及纳米科技(上海)有限公司 | Sub-nanometer-level high-precision photoetching writing field splicing method, photoetching machine system used by same, wafer and electron beam drift measuring method |
| CN113764262A (en) * | 2021-07-19 | 2021-12-07 | 中国科学院微电子研究所 | Preparation method and equipment of large-size high-precision chip |
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- 2022-11-24 CN CN202211478745.XA patent/CN115629445B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6517997B1 (en) * | 1999-05-29 | 2003-02-11 | Bookham Technology Plc | Production of an integrated optical device |
| US20110267594A1 (en) * | 2010-04-29 | 2011-11-03 | Samsung Electronics Co., Ltd. | Maskless exposure apparatus and stitching exposure method using the same |
| CN109143466A (en) * | 2018-08-31 | 2019-01-04 | 武汉光迅科技股份有限公司 | A kind of hybrid integrated silicon optical chip, optical device and chip manufacture method |
| CN111983899A (en) * | 2020-06-11 | 2020-11-24 | 百及纳米科技(上海)有限公司 | Sub-nanometer-level high-precision photoetching writing field splicing method, photoetching machine system used by same, wafer and electron beam drift measuring method |
| CN113764262A (en) * | 2021-07-19 | 2021-12-07 | 中国科学院微电子研究所 | Preparation method and equipment of large-size high-precision chip |
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