CN115603737A - Locking method and system for clock data recovery - Google Patents
Locking method and system for clock data recovery Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The invention provides a locking method and a system for clock data recovery, which comprises the following steps: current Vctl acquisition step: acquiring the current temperature of a clock data recovery chip CDR, determining a corresponding Vctl value according to the current temperature, and marking as TVctl, wherein Vctl represents voltage control; a locking judgment step: and recording the locked Vctl as LVctl, and comparing the LVctl with the TVctl to judge whether locking is finished. The CDR locking time is short, so that the light emitting time and the main/standby switching time of the optical module are short; the locking quality of the CDR is good, so that the receiving sensitivity of the optical module is good.
Description
Technical Field
The present invention relates to the technical field of clock data recovery locking, and in particular, to a locking method and system for clock data recovery. In particular, it preferably relates to a locking method and system of CDRs.
Background
The CDR is widely applied to an optical module, and the locking method of the CDR seriously affects the locking time, the light emitting time, and the receiving sensitivity of the optical module. The optical module generally puts requirements on the locking time and the locking quality of the CDR, for example, the locking time of the optical module is less than 20ms because the active/standby switching time of the server is 50 ms; the MSA protocol proposes that the optical module is 300ms from power-up to light-out. If CDR locking takes too much time, the optical module cannot meet these requirements. The locking quality is embodied in sensitivity, the locking quality is good, the sensitivity is high, otherwise, the sensitivity is low. English of CDR is called clock data recovery, chinese translation is clock data recovery; MSA: a multi-source agreement.
The invention patent document with publication number CN113114225A discloses a clock data recovery circuit and an operation method thereof. The techniques of this disclosure are used to implement clock data recovery circuits with improved trends, such as pull-up and/or pull-down trends. In various embodiments, the clock data recovery circuit includes a phase detector for receiving an input signal and outputting a reference clock signal. The phase detector then outputs two signals to the charge pump. The output of the charge pump drives the oscillator to control the voltage to rise or fall according to the current from the charge pump. The lock detector detects whether lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. Lock is indicated when the circuit settles to a frequency substantially close to the input signal and the oscillator control voltage is substantially close to the threshold voltage. The controller circuit may control the sweeping of the circuit's available frequency range until a lock-in occurs.
Chinese patent publication No. CN107682007A discloses a fast-locking low-jitter clock data recovery circuit based on a dual-loop, in which a frequency band switching circuit, a multi-band VCO, a resistance voltage dividing circuit, an alternative circuit, and a low-pass filter form a frequency-locked loop; the alternative circuit, the low-pass filter, the multiband VCO, the BBPD and the 4 charge pumps form a phase-locked loop; the frequency band switching circuit is used for outputting a frequency band control word and a loop selection signal according to an output clock clk0 and a reference clock clk _ ref of the multi-band VCO; the resistance voltage division circuit is used for dividing the power voltage vdd, and the voltage division output end of the resistance voltage division circuit is connected with the frequency locking loop input end of the alternative circuit; the alternative circuit is used for gating the frequency-locked loop or the phase-locked loop according to the loop selection signal.
For the above related technologies, the inventor considers that the locking time and the locking quality are not considered too much in the existing numerous CDR locking methods, which causes the long light emitting time and the main/standby switching time of the optical module, and also causes the poor receiving sensitivity of the optical module.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a locking method and a locking system for clock data recovery.
The locking method for clock data recovery provided by the invention comprises the following steps:
current Vctl acquisition step: acquiring the current temperature of a clock data recovery chip CDR, determining a corresponding Vctl value according to the current temperature, and marking as TVctl, wherein Vctl represents voltage control;
a locking judgment step: and recording the locked Vctl as LVctl, and comparing the LVctl with the TVctl to judge whether locking is finished.
Preferably, the locking method further comprises a chip testing step;
the chip testing step comprises the following steps:
a phase difference value obtaining step: testing the characteristics of a plurality of chip voltage-controlled oscillators, scanning the frequency bands and Vctl of the voltage-controlled oscillators to obtain test data, and counting the test data, wherein the difference between the Vctl of adjacent frequency bands under the same frequency is x;
acquiring a temperature relation: fixing a frequency band, scanning Vctl at different temperatures, and fitting the relation between the temperature T and the Vctl according to statistics:
Vctl＝a+bT
wherein a and b represent constants;
in the current Vctl obtaining step, a temperature sensor integrated in the clock data recovery measures the current temperature of the chip, and the current Vctl value is determined according to the relation between the temperature T and the Vctl in the temperature relational expression obtaining step and is marked as TVctl.
Preferably, the locking method further comprises the steps of:
TBctl obtaining step: selecting software-controlled Vctl by a multi-path selector, recording the software-controlled Vctl as SVctl, setting the SVctl value as TVctl, then scanning a frequency band, selecting the frequency band when a phase error accumulator is a preset value according to the phase error accumulator, recording the frequency band as TBctl, and setting the TBctl into clock data recovery;
and SNR calculation step: the balance controller controls signal balance, simultaneously selects Vctl generated by a loop from the multi-path selector, records the Vctl as AVctl, closes a clock data recovery loop, and then an analog-digital converter (ADC) samples an input signal and calculates a signal-to-noise ratio (SNR);
an SNR judging step: if the SNR is larger than the locking threshold, entering a locking judgment step; and if the SNR is less than or equal to the locked threshold, sequentially setting the band value as a TBctl value + a first preset value, a TBctl value-the first preset value, a TBctl value + a second preset value and a TBctl value-the second preset value according to the cycle number, repeating the SNR calculation step, and entering the current Vctl acquisition step if the SNR is still less than or equal to the threshold after four cycles.
Preferably, in the step of determining locking, the LVctl and the TVctl are compared, and if the difference is less than or equal to x determined in the step of obtaining the phase difference value, locking is completed; if the difference is larger than x, the selection of the frequency band is deviated, the correct frequency band value is estimated according to the LVctl value, and the SNR calculation step is repeated.
Preferably, in the lock determination step, the (LVctl-TVctl)/x is rounded and recorded as [ (LVctl-TVctl)/x ], the band value is configured as the current band value + [ (LVctl-TVctl)/x ], and the SNR calculation step is repeated.
According to the locking system for clock data recovery provided by the invention, the locking method for clock data recovery is applied, and comprises the following modules:
the current Vctl acquisition module: acquiring the current temperature of a clock data recovery chip CDR, determining a corresponding Vctl value according to the current temperature, and marking as TVctl, wherein Vctl represents voltage control;
a locking judgment module: and recording the locked Vctl as LVctl, and comparing the LVctl with the TVctl to judge whether locking is finished.
Preferably, the locking system further comprises a chip test module;
the chip testing module comprises the following modules:
a phase difference value acquisition module: testing the characteristics of a plurality of chip voltage-controlled oscillators, scanning the frequency bands and Vctl of the voltage-controlled oscillators to obtain test data, and counting the test data, wherein the difference x between the Vctl of adjacent frequency bands under the same frequency;
a temperature relation obtaining module: fixing a frequency band, scanning Vctl at different temperatures, and statistically fitting the relationship between the temperature T and the Vctl:
Vctl＝a+bT
wherein a and b represent constants;
in the current Vctl acquisition module, a temperature sensor integrated in clock data recovery measures the current temperature of the chip, and the current Vctl value is determined according to the relationship between the temperature T and the Vctl in the temperature relational expression acquisition module and is recorded as TVctl.
Preferably, the locking system further comprises the following modules:
a TBctl acquisition module: selecting software-controlled Vctl by a multi-path selector, recording the Vctl as SVctl, setting the SVctl value as TVctl, then scanning a frequency band, selecting the frequency band with a phase error accumulator as a preset value according to the phase error accumulator, recording the frequency band as TBctl, and setting the TBctl into clock data recovery;
an SNR calculation module: the balance controller controls signal balance, simultaneously selects Vctl generated by a loop from the multi-path selector, records the Vctl as AVctl, closes a clock data recovery loop, and then an analog-digital converter (ADC) samples an input signal and calculates a signal-to-noise ratio (SNR);
an SNR judgment module: if the SNR is larger than the threshold of locking, entering a locking judgment module; and if the SNR is less than or equal to the locked threshold, setting the band value as a TBctl value + a first preset value, a TBctl value-a first preset value, a TBctl value + a second preset value and a TBctl value-a second preset value in sequence according to the cycle number, repeating the SNR calculation module, and entering a current Vctl acquisition module if the SNR is still less than or equal to the threshold after four cycles.
Preferably, in the locking judgment module, the LVctl and the TVctl are compared, and if the difference is less than or equal to x determined in the phase difference value acquisition module, locking is completed; if the difference is larger than x, the selection of the frequency band is deviated, the correct frequency band value is calculated according to the LVctl value, and the SNR calculation module is repeated.
Preferably, in the lock determination module, the (LVctl-TVctl)/x is rounded and marked as [ (LVctl-TVctl)/x ], the band value is configured as the current band value + [ (LVctl-TVctl)/x ], and the SNR calculation module is repeated.
Compared with the prior art, the invention has the following beneficial effects:
1. the CDR locking time is short, so that the light emitting time and the main/standby switching time of the optical module are short;
2. the locking quality of the CDR is good, so that the receiving sensitivity of the optical module is good;
3. the CDR locking method of the invention is easy to realize.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a CDR structure diagram;
FIG. 2 is a CDR lock flow diagram;
FIG. 3 is a graph of frequency versus VCO, vctl;
fig. 4 is a graph of temperature versus Vctl.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will aid those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any manner. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the concept of the invention. All falling within the scope of the present invention.
The embodiment of the invention discloses a CDR locking method, the CDR structure is shown in figure 1: the VCO is a voltage controlled oscillator and has two control sections, one for band control (Bctl) and one for voltage control (Vctl). Bctl is band control, which is coarse tuning, corresponding to the selection of a frequency range, the VCO of the invention has 64 bands, which take on the range [0 63]. Vctl is voltage controlled, fine tuned, equivalent to selecting a certain frequency within this frequency range, and the VCO of the present invention has 64 Vctl, which take on the value range [0 63]. Once CDR is locked, the frequency band does not change, and Vctl tracks the input signal, which changes with changes in input signal, temperature.
PD is a phase detector that compares the phase difference of the input signal (high frequency compensated input signal) and the VCO output signal. The phase difference and the loop filter together produce Avctl. The input signal is externally applied to the CDR. The VCO is a voltage-controlled oscillator, and the output frequency thereof corresponds to the input control voltage, and a sine wave of one frequency is output when one voltage is input.
The phase error accumulator is an indication of the frequency difference, with a larger value indicating a closer input signal frequency to the VCO output frequency. Equalization is the high frequency compensation of the input signal.
The direction of the head reduction in fig. 1 is the flow direction of the signal inside the chip. The storage module is used for storing data sampled by the ADC into a RAM (random access memory) in the CDR, and then software calculates the SNR according to the data; the loop filter and the phase discriminator together generate Avctl; the DAC is a digital to analog conversion that produces Svctl. RAM is called Random Access Memory, and Chinese translation is RAM.
The CDR locking process is shown in fig. 2, and includes the following steps:
step 1: the Chip (CDR) VCO is tested for characteristics, and a sufficient number of chips (e.g., 10 chips) are tested. The frequency band and Vctl of the VCO are scanned at three temperatures, for example, 25 degrees, to obtain the following test results, and statistics are performed on these data, and Vctl of adjacent frequency bands at the same frequency are different by x, as shown in fig. 3. Three temperatures refer to-40 degrees, 25 degrees and 85 degrees.
Fixed frequency band, scanning Vctl at different temperatures, as shown in fig. 4, according to a statistically fitted relationship of temperature T and Vctl: vctl = a + bT. a and b are both constants. In FIG. 4, m is the value of Vctl at-40 degrees, n is the value of Vctl at 25 degrees, and l is the value of Vctl at 85 degrees.
Step 2: and (2) measuring the current temperature of the chip by using a temperature sensor integrated in the CDR, and determining the current value of Vctl according to the relation between the temperature T and the Vctl in the step 1, and marking as TVctl (Tvctl). The temperature sensor is integrated inside the chip and the temperature can be obtained by reading the register.
And step 3: the multiplexer is selected to software controlled Vctl (denoted as SVctl, SVctl), the value is set to TVctl, then 64 frequency bands are scanned, the frequency band at the maximum value is selected according to the phase error accumulator and denoted as TBctl (TBctl), the frequency band being the closest to the target frequency, and the TBctl is set to the CDR (VCO). Software controlled Vctl is obtained by writing chip internal registers. That is, a phase error accumulator is queried, and a frequency band corresponding to the accumulator having the maximum value is denoted as TBctl (TBctl).
And 4, step 4: the equalization control module controls signal equalization, selects a multi-path selector to Vctl (marked as AVctl) generated by a loop, closes a CDR loop, and then an ADC samples an input signal (the input signal after high-frequency compensation) and calculates SNR. The Vctl generated by the loop is obtained by reading the chip registers. The ADC is called Analog-to-Digital Converter in English, and the Chinese translation is an Analog-to-Digital Converter. The DAC is known as a Digital-to-Analog Converter in english, and the chinese translation is a Digital-to-Analog Converter. SNR is called signal-to-noise ratio in English, and Chinese translation is signal-to-noise ratio.
And 5: if the SNR is larger than the set locking threshold at the moment, the next step is carried out. Otherwise, the band values are set as TBctl values +1/-1 and +2/-2 (i is 4 values +1, -1, +2, -2, i.e., plus one, minus one, plus two, minus two), and step 4 is repeated, and step 2 is entered if the SNR is still less than the threshold after four cycles.
Step 6: and comparing the locked Vctl value (recorded as LVctl) with the TVctl, and if the difference is within x determined in the first step, completing locking. If the difference is larger than x, it indicates that the selection of the frequency band has deviation, and the correct frequency band value is calculated according to the LVctl value. And (LVctl-TVctl)/x is rounded (denoted as [ (LVctl-TVctl)/x ]), the band value is configured to be the current band value + [ (LVctl-TVctl)/x ], and the step 4 is repeated. The current band value is TBctl. The locked value of Vctl is obtained by reading the register.
The embodiment of the invention discloses a locking method for clock data recovery, which comprises the following steps:
the chip testing step comprises a phase difference value obtaining step and a temperature relation obtaining step. A phase difference value obtaining step: the method comprises the steps of testing the characteristics of a plurality of chip voltage-controlled oscillators, scanning the frequency bands and Vctl of the voltage-controlled oscillators to obtain test data, counting the test data, and enabling the difference between the Vctl of adjacent frequency bands to be x under the same frequency. A temperature relation obtaining step: fixing a frequency band, scanning Vctl at different temperatures, and fitting the relation between the temperature T and the Vctl according to statistics:
Vctl＝a+bT
wherein a and b represent constants.
Current Vctl acquisition step: and acquiring the current temperature of the clock data recovery chip CDR, determining a corresponding Vctl value according to the current temperature, and marking as TVctl, wherein Vctl represents voltage control. And measuring the current temperature of the chip by a temperature sensor integrated in the clock data recovery, and determining the current value of Vctl according to the relationship between the temperature T and the Vctl in the temperature relational expression acquisition step, and recording the value as TVctl.
TBctl obtaining step: and selecting software-controlled Vctl by the multi-path selector, recording the Vctl as SVctl, setting the SVctl value as TVctl, scanning a frequency band, selecting the frequency band when the phase error accumulator is a preset value (maximum value) according to the phase error accumulator, recording the frequency band as TBctl, and setting the TBctl into clock data recovery. Namely, a phase error accumulator is inquired, a frequency band corresponding to the maximum accumulator is marked as TBctl, and the TBctl is set in a clock data recovery chip.
And SNR calculation step: and the balance controller controls signal balance, simultaneously selects Vctl generated by the loop from the multi-path selector, records the Vctl as AVctl, closes the clock data recovery loop, and then samples the input signal by the analog-to-digital converter ADC and calculates the signal-to-noise ratio SNR.
An SNR judging step: if the SNR is larger than the locking threshold, entering a locking judgment step; and if the SNR is less than or equal to the locked threshold, sequentially setting the band value as a TBctl value + a first preset value, a TBctl value-the first preset value, a TBctl value + a second preset value and a TBctl value-the second preset value according to the cycle number, repeating the SNR calculation step, and entering the current Vctl acquisition step if the SNR is still less than or equal to the threshold after four cycles.
A locking judgment step: and recording the locked Vctl as LVctl, and comparing the LVctl with the TVctl to judge whether locking is finished. Comparing the LVctl with the TVctl, and if the difference is less than or equal to x determined in the phase difference value acquisition step, completing locking; if the difference is larger than x, the selection of the frequency band is deviated, the correct frequency band value is estimated according to the LVctl value, and the SNR calculation step is repeated. And (LVctl-TVctl)/x is rounded and is marked as [ (LVctl-TVctl)/x ], the frequency band value is configured to be the current frequency band value + [ (LVctl-TVctl)/x ], and the SNR calculation step is repeated.
The embodiment of the invention also discloses a locking system of the CDR, which applies a locking method of clock data recovery and comprises the following modules:
the chip testing module comprises a phase difference value acquisition module and a temperature relational expression acquisition module. A phase difference value acquisition module: testing the characteristics of a plurality of chip voltage-controlled oscillators, scanning the frequency bands and Vctl of the voltage-controlled oscillators to obtain test data, counting the test data, and obtaining the difference x between the Vctl of adjacent frequency bands under the same frequency. A temperature relation obtaining module: fixing a frequency band, scanning Vctl at different temperatures, and statistically fitting the relationship between the temperature T and the Vctl:
Vctl＝a+bT
wherein a and b represent constants.
The current Vctl acquisition module: and acquiring the current temperature of the CDR of the clock data recovery chip, determining a corresponding Vctl value according to the current temperature, and marking as TVctl, wherein Vctl represents voltage control. And a temperature sensor integrated in the clock data recovery measures the current temperature of the chip, and the current value of Vctl is determined according to the relation between the temperature T and the Vctl in the temperature relational expression acquisition module and is marked as TVctl.
A TBctl acquisition module: and selecting software-controlled Vctl by the multi-path selector, recording the Vctl as SVctl, setting the SVctl value as TVctl, scanning a frequency band, selecting the frequency band when the phase error accumulator is a preset value (maximum value) according to the phase error accumulator, recording the frequency band as TBctl, and setting the TBctl into clock data recovery. And inquiring a phase error accumulator, recording a frequency band corresponding to the accumulator when the accumulator is maximum as TBctl, and setting the TBctl into a clock data recovery chip.
An SNR calculation module: and the balance controller controls signal balance, simultaneously selects Vctl generated by the loop from the multi-path selector, records the Vctl as AVctl, closes the clock data recovery loop, and then samples an input signal by the analog-digital converter ADC and calculates the signal-to-noise ratio SNR.
An SNR judgment module: if the SNR is larger than the locking threshold, entering a locking judgment module; and if the SNR is less than or equal to the locked threshold, setting the band value as a TBctl value + a first preset value, a TBctl value-a first preset value, a TBctl value + a second preset value and a TBctl value-a second preset value in sequence according to the cycle number, repeating the SNR calculation module, and entering a current Vctl acquisition module if the SNR is still less than or equal to the threshold after four cycles.
A locking judgment module: and recording the locked Vctl as LVctl, and comparing the LVctl with the TVctl to judge whether locking is finished. Comparing the LVctl with the TVctl, and if the difference is less than or equal to x determined in the phase difference value acquisition module, completing locking; if the difference is larger than x, the selection of the frequency band is deviated, the correct frequency band value is calculated according to the LVctl value, and the SNR calculation module is repeated. And (LVctl-TVctl)/x is rounded and is marked as [ (LVctl-TVctl)/x ], the frequency band value is configured to be the current frequency band value + [ (LVctl-TVctl)/x ], and the SNR calculation module is repeated.
Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for realizing various functions can also be regarded as structures in both software modules and hardware components for realizing the methods.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A locking method for clock data recovery is characterized by comprising the following steps:
current Vctl acquisition step: acquiring the current temperature of a clock data recovery chip CDR, determining a corresponding Vctl value according to the current temperature, and marking as TVctl, wherein Vctl represents voltage control;
a locking judgment step: and recording the locked Vctl as LVctl, and comparing the LVctl with the TVctl to judge whether locking is finished.
2. The locking method for clock data recovery according to claim 1, wherein the locking method further comprises a chip test step;
the chip testing step comprises the following steps:
a phase difference value obtaining step: testing the characteristics of a plurality of chip voltage-controlled oscillators, scanning the frequency bands and Vctl of the voltage-controlled oscillators to obtain test data, and counting the test data, wherein the difference x between the Vctl of adjacent frequency bands under the same frequency;
acquiring a temperature relation: fixing a frequency band, scanning Vctl at different temperatures, and fitting the relation between the temperature T and the Vctl according to statistics:
Vctl＝a+bT
wherein a and b represent constants;
in the current Vctl obtaining step, a temperature sensor integrated in the clock data recovery measures the current temperature of the chip, and the current Vctl value is determined according to the relationship between the temperature T and the Vctl in the temperature relational expression obtaining step and is recorded as TVctl.
3. The locking method for clock data recovery according to claim 2, wherein the locking method further comprises the steps of:
TBctl obtaining step: selecting software-controlled Vctl by a multi-path selector, recording the Vctl as SVctl, setting the SVctl value as TVctl, then scanning a frequency band, selecting the frequency band with a phase error accumulator as a preset value according to the phase error accumulator, recording the frequency band as TBctl, and setting the TBctl into clock data recovery;
and SNR calculation step: the balance controller controls signal balance, simultaneously selects Vctl generated by a loop from the multi-path selector, records the Vctl as AVctl, closes a clock data recovery loop, and then an analog-digital converter (ADC) samples an input signal and calculates a signal-to-noise ratio (SNR);
an SNR judging step: if the SNR is larger than the locking threshold, entering a locking judgment step; and if the SNR is less than or equal to the locked threshold, setting the band value as a TBctl value + a first preset value, a TBctl value-a first preset value, a TBctl value + a second preset value and a TBctl value-a second preset value in sequence according to the cycle number, repeating the SNR calculation step again, and entering the current Vctl acquisition step if the SNR is still less than or equal to the threshold after four cycles.
4. The locking method for clock data recovery according to claim 3, wherein in the locking determination step, LVctl and TVctl are compared, and if the difference is less than or equal to x determined in the phase difference value acquisition step, locking is completed; if the difference is larger than x, the selection of the frequency band is deviated, the correct frequency band value is estimated according to the LVctl value, and the SNR calculation step is repeated.
5. The method of claim 4, wherein in the step of determining locking, the step of SNR calculation is repeated by rounding (LVctl-TVctl)/x, which is denoted as [ (LVctl-TVctl)/x ], and configuring the band value as the current band value + [ (LVctl-TVctl)/x ].
6. A locking system for clock data recovery, characterized in that, the locking method for clock data recovery according to any one of claims 1-5 is applied, and comprises the following modules:
the current Vctl acquisition module: acquiring the current temperature of a clock data recovery chip CDR, determining a corresponding Vctl value according to the current temperature, and marking as TVctl, wherein Vctl represents voltage control;
a locking judgment module: and recording the locked Vctl as LVctl, and comparing the LVctl with the TVctl to judge whether locking is finished.
7. The clock-data recovery locking system of claim 6, further comprising a chip test module;
the chip testing module comprises the following modules:
a phase difference value acquisition module: testing the characteristics of a plurality of chip voltage-controlled oscillators, scanning the frequency bands and Vctl of the voltage-controlled oscillators to obtain test data, and counting the test data, wherein the difference x between the Vctl of adjacent frequency bands under the same frequency;
a temperature relation obtaining module: fixing a frequency band, scanning Vctl at different temperatures, and fitting the relation between the temperature T and the Vctl according to statistics:
Vctl＝a+bT
wherein a and b represent constants;
in the current Vctl acquisition module, a temperature sensor integrated in clock data recovery measures the current temperature of the chip, and the current Vctl value is determined according to the relationship between the temperature T and the Vctl in the temperature relational expression acquisition module and is marked as TVctl.
8. The clock data recovery locking system of claim 7, further comprising:
a TBctl acquisition module: selecting software-controlled Vctl by a multi-path selector, recording the Vctl as SVctl, setting the SVctl value as TVctl, then scanning a frequency band, selecting the frequency band with a phase error accumulator as a preset value according to the phase error accumulator, recording the frequency band as TBctl, and setting the TBctl into clock data recovery;
an SNR calculation module: the balance controller controls signal balance, simultaneously selects Vctl generated by a loop from the multi-path selector, records the Vctl as AVctl, closes a clock data recovery loop, and then samples an input signal and calculates a signal-to-noise ratio (SNR) by the analog-to-digital converter (ADC);
an SNR judgment module: if the SNR is larger than the locking threshold, entering a locking judgment module; and if the SNR is less than or equal to the locked threshold, setting the band value as a TBctl value + a first preset value, a TBctl value-a first preset value, a TBctl value + a second preset value and a TBctl value-a second preset value in sequence according to the cycle number, repeating the SNR calculation module, and entering a current Vctl acquisition module if the SNR is still less than or equal to the threshold after four cycles.
9. The clock data recovery locking system of claim 8, wherein in the locking determination module, the LVctl and the TVctl are compared, and if the difference is less than or equal to x determined in the phase difference acquisition module, the locking is completed; if the difference is larger than x, the selection of the frequency band is deviated, the correct frequency band value is calculated according to the LVctl value, and the SNR calculation module is repeated.
10. The system of claim 9, wherein in the lock determination module, the SNR calculation module is repeated by rounding (LVctl-TVctl)/x, which is denoted as [ (LVctl-TVctl)/x ], and configuring the frequency band value as the current frequency band value + [ (LVctl-TVctl)/x ].
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211136845.4A CN115603737A (en) | 2022-09-19 | 2022-09-19 | Locking method and system for clock data recovery |
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| CN202211136845.4A CN115603737A (en) | 2022-09-19 | 2022-09-19 | Locking method and system for clock data recovery |
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