CN115599718A - DMA transmission method and control component - Google Patents

Abstract

The application relates to a DMA transmission method and a control component. The method comprises the following steps: allocating continuous cache space in a cache of DMA equipment for the IO command, and generating a first DMA command according to each descriptor in an SCL of the IO command; initiating a first DMA transfer based on the first DMA command; distributing one or more Data Transmission Unit (DTU) for the IO command, and generating a DMA command group according to each DTU, wherein the DMA command group comprises one or more second DMA commands; a second DMA transfer is initiated based on the second DMA command. The present application provides a DMA command scheme that generates two DMA transfers.

Description

DMA transmission method and control component

Technical Field

The present application relates to a DMA transfer technology, and in particular, to a DMA transfer method and a control unit.

Background

DMA (Direct Memory Access) is a technology for directly moving data between memories without depending on a CPU. DMA technology is used in a variety of electronic devices. In the present application, a solid-state storage device is taken as an example to introduce the technical scheme for optimizing DMA transfer by using cache. FIG. 1 illustrates a block diagram of a solid-state storage device. The solid-state storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, feRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to an interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

Fig. 2 shows a schematic diagram of a prior art DMA transfer.

Taking DMA transfer between the host and the solid-state storage device as an example, data in the host memory 210 is moved to the device memory 220 of the storage device by the DMA device.

Host memory 210 stores data to be moved by the DMA device to device memory 220. The move of data from the host memory 210 to the device memory 220 is performed according to the DMA command group (L1, L2, L3, or L4). The DMA command identifier includes a plurality of DMA commands, each DMA command indicating a data move. Examples of data length such as source address (e.g., host memory 210 address), destination address (e.g., device memory 220 address) and transfer are referred to in the DMA command. Taking DMA command group L2 as an example, which includes 6 DMA commands, referring to FIG. 2, DMA command 0 indicates to start from source address 0x0000, move data of length 0x0800 to destination address 0x0800, DMA command 1 indicates to start from source address 0x0800, move data of length 0x04000 to destination address 0x2400. The numbers indicating the memory addresses in fig. 2 are all 16-ary, and for the sake of brevity, the "0x" designation preceding the 16-ary number is omitted.

To increase memory utilization, the DMA commands may indicate that data is to be moved and stored in both the host memory 210 and the device memory 220 in a non-sequential manner. The data indicated by the DMA command group L2 is stored in 3 areas in the host memory 210 and 6 areas (areas indicated by hatching with horizontal lines) in the device memory. However, multiple pieces of data in the memory are not conducive to optimization of data transfer, and more DMA commands add complexity to provide each piece of data with a DMA command for transfer.

Host memory 210 and/or device memory 220 each include multiple pages of memory, each page being, for example, 4KB in size. A control component of the host and/or the storage device generates and provides DMA commands to the DMA device. If the host generates a DMA command, the host manages allocation and release of the host memory 210 and the device memory 220; if the storage device generates a DMA command, the control component of the storage device manages allocation and release of the host memory 210 and the device memory 220; or the host generates DMA commands in cooperation with the storage device, the host managing its own host memory 210 and the device's control unit managing its own device memory 220.

Disclosure of Invention

In order to avoid multi-chip storage of data in the storage device and accelerate DMA transmission, continuous storage space is distributed for IO commands in the cache of the DMA device, so that the number of DMA commands is reduced under some conditions, and the complexity of the DMA transmission process is reduced; the continuous memory space also facilitates optimizing data transfers, thereby speeding up the DMA transfer process. In order to realize the purpose of accelerating DMA transmission, DMA commands need to be generated on the basis of allocating continuous storage space for IO commands in the cache of DMA equipment.

According to a first aspect of the present application, there is provided a method of a first DMA transfer according to the first aspect of the present application, comprising: allocating continuous cache space in a cache of DMA equipment for an IO command, acquiring an SGL (secure gateway) according to the IO command, and generating a first DMA command according to each descriptor in an SCL (service level control), wherein the first DMA command is used for describing DMA transmission from a first memory space to the cache space of the DMA equipment; initiating a first DMA transfer based on the first DMA command; one or more Data Transmission Unit (DTU) is distributed for the IO command, a DMA command group is generated according to each DTU, the DMA command group comprises one or more second DMA commands, and the second DMA commands are used for describing DMA transmission from the cache space to a second memory space; a second DMA transfer is initiated based on the second DMA command.

According to the first DMA transfer method of the first aspect of the present application, there is provided a second DMA transfer method of the first aspect of the present application, where the first DMA command is generated according to each descriptor in the SCL, and the method includes: generating a first DMA command according to each hole descriptor in the SCL; and generating a first DMA command according to each data block descriptor in the SCL.

According to the first or second DMA transfer method of the first aspect of the present application, there is provided a third DMA transfer method of the first aspect of the present application, in which a continuous buffer space is allocated in a buffer of a DMA device for an IO command, the method including: each first DMA command is allocated contiguous DMA device cache space.

According to the third DMA transfer method of the first aspect of the present application, there is provided the fourth DMA transfer method of the first aspect of the present application, the buffer spaces allocated to the first DMA command generated by the adjacent descriptors in the SCL are adjacent, and the buffer space corresponding to the first DMA command generated by the subsequent descriptor is located after the buffer space corresponding to the first DMA command generated by the previous descriptor.

According to a fourth DMA transfer method of the first aspect of the present application, there is provided a fifth DMA transfer method of the first aspect of the present application, in which an address of a cache space allocated to a first DMA command generated by a first descriptor is a first address; the address of the buffer space allocated to the first DMA command generated by the second descriptor is a second address, wherein the first descriptor and the second descriptor are consecutive data block descriptors or hole descriptors in the SCL, and the second address is equal to the first address plus the size of data to be transferred by the first DMA command generated by the second descriptor.

According to a first aspect of the present invention, there is provided a method of DMA transfer according to the first aspect of the present invention, wherein, for a segment descriptor in an SGL, which is used to fetch a next SGL segment and includes one or more SGL descriptors, no DMA command is generated.

According to the method for DMA transfer according to any one of the first to fifth aspects of the present application, there is provided a seventh DMA transfer method according to the first aspect of the present application, where, according to a first DMA command generated by a hole descriptor, invalid data is to be filled in a cache of a DMA device corresponding to the first DMA command, so that data indicated by a subsequent first DMA command can be written into a correct location.

According to a method of DMA transfer according to any one of the first to seventh aspects of the present application, there is provided a method of eighth DMA transfer according to the first aspect of the present application, wherein the first DMA command indicates a source address, a destination address, and a length of data to be transferred; and responding to the fact that the IO command is a write command, and generating a first DMA command according to the hole descriptor, wherein a source address in the first DMA command is empty, and a destination address is a position of data written in a cache of the current DMA device.

According to a method of an eighth DMA transfer according to the first aspect of the present application, there is provided a method of a ninth DMA transfer according to the first aspect of the present application, wherein the destination address of the first DMA command is indicated based on a write pointer indicating a location in a cache of the DMA device where data is to be written.

According to a ninth DMA transfer method of the first aspect of the present application, there is provided the tenth DMA transfer method of the first aspect of the present application, wherein, in response to the IO command being a read command, the source address of the first DMA command is indicated based on a read pointer indicating a location where data is currently read from a cache of a DMA device.

According to a tenth DMA transfer method of the first aspect of the present application, there is provided the eleventh DMA transfer method of the first aspect of the present application, wherein in response to completion of writing data into a buffer memory of the DMA device, the write pointer is updated based on a length of data to be transferred indicated by the first DMA command; or in response to completion of reading data from the buffer of the DMA device, update the read pointer based on the length of data to be transferred as indicated by the first DMA command.

According to the method of DMA transfer of any one of the first to eleventh aspects of the first aspect of the present application, there is provided a method of twelfth DMA transfer according to the first aspect of the present application, further comprising: one or more buffers housing DTUs are allocated in the second memory for IO commands.

According to a twelfth DMA transfer method of the first aspect of the present application, there is provided the thirteenth DMA transfer method of the first aspect of the present application, wherein if one or more DTU-accommodating buffers allocated from the second memory are not consecutive, the buffers include a plurality of memory regions, and the sum of the plurality of memory regions is 4KB.

According to a thirteenth DMA transfer method of the first aspect of the present application, there is provided the fourteenth DMA transfer method of the first aspect of the present application, wherein, in response to a cache discontinuity accommodating DTUs, one second DMA command is generated from each memory area of each DTU.

According to a fourteenth method of DMA transfer of the first aspect of the present application, there is provided the method of a fifteenth DMA transfer of the first aspect of the present application, the second DMA command indicating a location of a current read of data from a DMA device cache, a size of data to be transferred, and a location of a storage area in the second memory; and updating the position of reading data from the DMA device cache based on the size of the data to be transmitted.

According to a fifteenth DMA transfer method of the first aspect of the present application, there is provided the sixteenth DMA transfer method of the first aspect of the present application, wherein, in response to the presence of invalid data from data to be read in the DMA device cache space based on a second DMA command in which a range in which the invalid data is stored in the DMA device cache space is also marked.

According to a sixteenth DMA transfer method of the first aspect of the present application, there is provided the seventeenth DMA transfer method of the first aspect of the present application, wherein in response to the second DMA command to process a marked invalid data range, an invalid signal indicating that the data is invalid is generated on the bus upon transfer to the invalid data portion.

According to a seventeenth DMA transfer method of the first aspect of the present application, there is provided the eighteenth DMA transfer method of the first aspect of the present application, wherein the invalidate signal is a WSTRB signal indicating invalidation of data in compliance with an AXI protocol.

According to a second aspect of the present application, there is provided a first control component according to the second aspect of the present application, comprising: an SGL unit and a DMA device; the SGL unit, in response to receiving an IO command, allocates continuous cache space for the IO command in a cache of DMA equipment, acquires the SGL according to the IO command, and generates a first DMA command according to each descriptor in the SCL, wherein the first DMA command is used for describing DMA transmission from a first memory space to the cache space of the DMA equipment; one or more Data Transmission Unit (DTU) is distributed for the IO command, a DMA command group is generated according to each DTU, the DMA command group comprises one or more second DMA commands, and the second DMA commands are used for describing DMA transmission from the cache space to the second memory space; the DMA device initiating a first DMA transfer based on the first DMA command; and initiating a second DMA transfer based on the second DMA command.

According to a first control section of a second aspect of the present application, there is provided a second control section of the second aspect of the present application, the DMA apparatus for moving data from a first memory to a second memory, comprising: the system comprises a first DMA module, a second DMA module and a cache; the first DMA module is used for DMA transmission of data to be transmitted from the first memory space to the cache space according to each first DMA command; the second DMA module DMA transfers data to be transferred from the buffer space to the second memory space in accordance with each of the second DMA commands.

According to a second control component of the second aspect of the present application, there is provided a third control component of the second aspect of the present application, wherein the SGL unit allocates one or more DTU-accommodating buffers in the second memory for IO commands.

According to the third control means of the second aspect of the present application, there is provided the fourth control means of the second aspect of the present application, wherein if one or more buffers accommodating DTUs allocated from the second memory are not consecutive, the buffers include a plurality of memory regions, and the sum of the capacities of the plurality of memory regions is 4KB.

According to a fourth control unit of the second aspect of the present application, there is provided the fifth control unit of the second aspect of the present application, wherein in response to a cache discontinuity accommodating DTUs, the SGL unit generates one second DMA command per memory area per DTU.

According to a fifth control means of the second aspect of the present application, there is provided the sixth control means of the second aspect of the present application, wherein in response to the presence of invalid data from data to be read in the DMA device cache space based on a second DMA command, the SGL unit further marks in the second DMA command a range in which the invalid data is stored in the DMA device cache space.

According to a sixth controlling means of the second aspect of the present application, there is provided the seventh controlling means of the second aspect of the present application, wherein the second DMA module generates an invalid signal indicating that the data is invalid on the bus when transferring to the invalid data section in response to processing the second DMA command marking the invalid data range.

According to a third aspect of the present application, there is provided a memory device according to the third aspect of the present application, comprising the control unit according to the second aspect, and further comprising a first memory or a second memory, wherein the first memory and the second memory are both memories coupled to the outside of the DMA device.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to these drawings.

FIG. 1 illustrates a block diagram of a solid-state storage device;

FIG. 2 shows a schematic diagram of a prior art DMA transfer;

fig. 3 is a schematic diagram illustrating a data transmission process provided by an embodiment of the present application;

FIG. 4A is a block diagram illustrating a control component provided in an embodiment of the present application;

FIG. 4B is a block diagram illustrating a DMA transfer provided by an embodiment of the present application;

fig. 5A is a schematic diagram illustrating allocation of a buffer space of a DMA device according to an embodiment of the present application;

fig. 5B is a schematic diagram illustrating an allocation of a storage space for a data transmission unit DTU according to an embodiment of the present application;

FIG. 6A is a flow chart illustrating DMA transfer according to an embodiment of the present application;

FIG. 6B is a diagram illustrating DMA transfers provided by embodiments of the present application;

FIG. 6C is a diagram illustrating a DMA command generated according to an IO command according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments obtained by a person skilled in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

Generally, the NVMe command needs to describe the length of data to be accessed and the address information of the data to be accessed, wherein the address information of the data to be accessed is described by the SGL descriptor, and the SGL descriptor is provided with continuous logical addresses according to the length of the data to be accessed. The storage device shown in fig. 1 transmits and processes data to be accessed by the storage device based on NVMe commands, and a data transmission process is described below with reference to fig. 3.

Fig. 3 shows a schematic diagram of a data transmission process provided in an embodiment of the present application. As shown in fig. 3, NVMe commands (e.g., IO commands) describe a contiguous LBA space of 13KB in length (LBA x through LBAx +26 in fig. 3, each LBA can represent 0.5 KB) that represents the need for the host to transfer 13KB of data into the SSD as indicated by the NVMe commands, but where only 11KB of data is actually needed, so there are 2KB holes in the 13KB contiguous LBA space (no need to transfer data to the holes). In host memory, these 11KB data can be accommodated by non-contiguous blocks of memory. For example, 11KB of data may be placed into 3 different sizes of memory, such as 3KB of data block a, 4KB of data block B, and 4KB of data block C in fig. 3. Wherein the 2KB void in the LBA space is in the region of 7KB to 9KB from the LBAx (shaded portion in FIG. 3).

In particular, the data transmission scenario described above is described in connection with SGL. In fig. 3 the SGL uses 3 segment descriptors SGL segment (e.g., SGL segment0, SGL segment1, and SGL segment 2). Therein, SGL Segment0 describes moving 3KB of data block A to the 3KB space starting at LBA x (i.e., LBA x + 6). Meanwhile, SGL segment0 also describes the Address of data block a (Address = a) and the Address of the next SGL segment1 (Address = segment 1). SGL Segment1 describes the movement of 4KB of data block B to the next 4KB of LBA space (i.e., LBA x +6, LBA x + 14). Meanwhile, SGL segment1 also describes the Address of data block B (Address = B), further describes that LBA space is followed by 2KB space as a hole (called bit blocked descriptor, (LBA x +14, LBA x + 18)), and describes the Address of next SGL segment1 (Address = segment 1). While SGL Segment2 describes the movement of 4KB of data of block C to the next 4KB of space (LBA x +18, LBA x + 26) of LBA space. Meanwhile, segment2 also describes the Address of data block C (Address = C) and the last segment of the SGL of the write command which is the current segment. Each segment descriptor SGL segment is used to describe one or more SGL descriptors and to describe the next SGL segment, where each segment descriptor SGL segment describes one or more SGL descriptors including a data block descriptor and a hole descriptor; and the data block descriptor is used to describe the data block, such as the descriptor in SGL Segment0 that describes the 3KB data of data block a; the hole descriptor is used to describe a hole, such as the descriptor in SGL segment1 that describes a 2KB hole.

Fig. 4A shows a block diagram of a control unit according to an embodiment of the present application.

By way of example, as shown in fig. 4A, the control unit includes a DMA device and an SGL unit; the SGL unit is coupled to a host ((not labeled in the figure)) and coupled to the DMA device through a host interface, acquires an NVMe command (such as an IO command) from the host through the host interface, and analyzes the NVMe command to obtain an SGL. After the NVMe commands are parsed by the SGL, one or more DMA command groups may be generated according to information described by one or more SGL descriptors in the SGL. DMA commands (e.g., data move commands) in the DMA command group are processed by the DMA device to move data to or read data from a memory (hereinafter, memory 2) in the storage device, such as a DRAM or SRAM memory, rather than an NVM chip (i.e., non-volatile memory). In the data transmission process, for example, the NVMe protocol defines that the data length transmitted is equal to the data length indicated by the NVMe command, and then the NVMe command is considered to be processed completely; based on this, when there is a hole in the address space corresponding to the continuous logical address indicated by the NVMe command, the length of the hole is counted into the data length to be transmitted by the NVMe command specified by the protocol, and whether the data corresponding to the NVMe command is moved is identified according to the accumulated transmitted data length. However, since the data stored in the hole corresponds to the NVMe command, the NVMe command is invalid data, and it is generally not desirable to store the data in the hole or move the data in the hole to the host in the NVMe command processing process. The present application expects that when the check information is calculated, the received data length does not include the hole length, but the data length to be transmitted includes the hole length, etc., and based on this, invalid data corresponding to the hole needs to be subjected to a dummy move in the data moving process, wherein the dummy move operation is to transmit the invalid data without storing the invalid data in a memory (such as a DRAM).

FIG. 4B is a block diagram illustrating a DMA transfer according to an embodiment of the present application.

By way of example, in fig. 4b, the DMA device includes a DMA module 1, a DMA module 2, and a cache. The DMA device is coupled to a memory 1 in the host. The DMA device is further coupled to a memory 2 in the storage device. The memory 2 is for example integrated inside a control unit of the memory device, so that the memory 2 has a relatively high access speed and a relatively high cost per unit of storage capacity, for example the memory 2 is an SRAM or a DRAM. In addition, the memory 2 may also serve as an external memory coupled to the control unit. The DMA module 1 performs data transfer between the memory 1 and the buffer of the DMA device, and the DMA module 2 performs data transfer between the buffer of the DMA device and the memory 2. As the storage device, to provide a storage function, the control section also writes data moved from the host to the memory 2 into the NVM chip or transfers data read from the NVM chip and stored in the memory 2 to the host. Optionally, the DMA module 1 and the DMA module 2 are DMA modules integrated inside the DMA device.

The control part generates a DMA command for each of the DMA modules 1 and 2 to instruct the DMA modules 1 and 2 to perform DMA transfer. To generate DMA commands, the control unit manages the allocation and release of buffers and memory. As an example, in the IO command provided by the host to the control unit, the address of the data to be transferred by the IO command in the host memory 1 and the length of the data to be transferred are indicated. The control component receives and analyzes the IO command to obtain SGL, and generates a DMA command 1 according to a descriptor in the SGL, and the DMA module 1 initiates DMA transfer based on the DMA command 1, wherein the DMA transfer refers to that the DMA module 1 executes data transfer once based on each DMA command 1. For example, if the NVMe command is a write command, DMA command 1 is used to move data from memory 1 into the DMA device's cache; if the NVMe command is a read command, DMA command 1 is used to move data from the DMA device's cache to memory 1.

Also by way of example, the SGL indicated by the NVMe command may include one or more data block descriptors and/or one or more hole descriptors, and the control component generates one DMA command 1 based on each data block descriptor and one DMA command 1 based on each hole descriptor. That is, in the solution provided in the embodiment of the present application, the control component generates DMA commands 1 executed by the DMA module 1 based on the SGL descriptors, where the number of generated DMA commands 1 is related to the number of SGL descriptors corresponding to the NVMe command, for example, the number of DMA commands 1 is equal to the sum of the data block descriptors and the hole descriptors in the SGL.

In order to improve the DMA transmission efficiency, the control part allocates continuous buffer space for the data to be transmitted by the IO command in the buffer memory of the DMA device, wherein the size of the continuous buffer space allocated for the IO command in the buffer memory of the DMA device is the size of the data to be transmitted indicated by the IO command. The data DMA-transferred by the DMA module 1 and the DMA module 2 both need to occupy the buffer memory of the DMA device, for example, allocating a continuous memory space for the data to be transferred by the IO command includes allocating a buffer memory space of the DMA device for each DMA command 1.

Fig. 5A is a schematic diagram illustrating allocation of a buffer space of a DMA device according to an embodiment of the present application.

By way of example, in fig. 5A, the control component generates DMA command 1 for DMA module 1 based on the SGL descriptor corresponding to the NVMe command, including DMA command A1, DMA command B1, DMA command C1, and DMA command D1. The control unit allocates a buffer space buffer1 for the DMA command A1, a buffer space buffer2 for the DMA command B1, a buffer space buffer3 for the DMA command C1, and a buffer space buffer4 for the DMA command D1 in the cache of the DMA device, wherein the buffer1, the buffer2, the buffer3, and the buffer4 are all a continuous buffer space.

For another example, if the DMA command A1 and the DMA command B1 are DMA commands generated by adjacent or consecutive descriptors in the SGL, the DMA device cache space buffer1 corresponding to the DMA command A1 and the DMA device cache space buffer2 corresponding to the DMA command B1 are adjacent in the DMA device cache, and the cache space of the buffer2 is located behind the cache space of the buffer 1. That is, the buffer spaces allocated to DMA command 1 generated by the adjacent descriptors in SCL are adjacent, and the buffer space corresponding to DMA command 1 generated by the following descriptor is located after the buffer space corresponding to DMA command 1 generated by the preceding descriptor.

Further, as an example, a description will be given by taking a DMA command in which the DMA command A1 and the DMA command B1 are generated as adjacent or consecutive descriptors in the SGL as an example. If the length of the data to be transferred indicated by DMA command A1 is 3KB, the length of the data to be transferred indicated by DMA command B1 is 2KB, i.e., the size of DMA device cache space buffer1 corresponding to DMA command A1 is 3KB, and the size of DMA device cache space buffer2 corresponding to DMA command B1 is 2KB. If the starting address of buffer1 is addr1, then the starting address of buffer2 is addr1+3KB. That is, there is an association between the DMA device cache space addresses allocated to DMA commands generated by two adjacent or consecutive descriptors in the SGL, for example, the DMA command generated by a subsequent descriptor has an allocated DMA device cache space address equal to the sum of the DMA device cache space address allocated to the DMA command generated by a previous descriptor and the DMA device cache space size allocated to the DMA command generated by a previous descriptor.

Since the DMA command 1 for DMA transfer of the DMA module 1 may be generated by the data block descriptor or the hole descriptor, and the data stored in the hole is invalid data corresponding to the NVMe command, it is generally not desirable to store the data in the hole or move the data in the hole to the host in the NVMe command processing process. However, since the addresses of the buffer spaces of the DMA devices allocated by the DMA commands generated by two adjacent or consecutive descriptors in the SGL are associated, in order to write the data indicated by the DMA command 1 generated after the hole descriptor into the correct location, for example, the buffer of the DMA device corresponding to the DMA command 1 corresponding to the hole descriptor is filled with invalid data.

In order to enable the DMA module 1 to perform data transfer between the memory 1 and the buffer of the DMA device based on the DMA command 1. By way of example, DMA command 1 indicates a source address, a destination address, and a length of data to be transferred. For example, for DMA command 1 generated by a data block descriptor. The source address indicated by the DMA command 1 is the address of a memory 1, and the destination address is the address of the buffer memory space of the DMA device corresponding to the DMA command 1; or the source address indicated by the DMA command 1 is the address of the buffer space of the DMA device corresponding to the DMA command 1, and the destination address is the address of the memory 1. For DMA command 1 generated by the hole descriptor. The source address indicated by the DMA command 1 is empty, and the destination address is the address of the DMA equipment cache space corresponding to the DMA command 1; or the source address indicated by the DMA command 1 is the address of the DMA device cache space corresponding to the DMA command 1, and the destination address is null.

As another example, the address at which each DMA command 1 is allocated DMA device buffer space may be indicated by a pointer. For example, if the IO command is a write command, the destination address of the DMA command 1 is indicated based on a write pointer indicating the location of the write data in the cache of the DMA device. As another example, if the IO command is a read command, the source address of DMA command 1 is indicated based on a read pointer indicating the location where data is currently being read from the DMA device's cache.

By way of further example, in response to completion of writing data into the cache of the DMA device, the write pointer is updated based on the length of data to be transferred as indicated by DMA command 1; or in response to completion of the read of the data from the buffer of the DMA device, the read pointer is updated based on the length of data to be transferred as indicated by DMA command 1. For example, the cache space address of the DMA device indicated by the updated write pointer is the cache space address of the DMA device indicated by the write pointer before updating plus the write data length; the address of the buffer space of the DMA device indicated by the updated read-after pointer is the address of the buffer space of the DMA device indicated by the updated read-before pointer plus the length of the read data.

Further, to move data to or from the memory 2, the control section allocates a memory space in the memory 2 for data to be transferred by the IO command, and generates a DMA command group for the DMA module 2, wherein the DMA command group includes one or more DMA commands 2. For example, the total Data size to be transferred of each DMA command group is specified, such as the total Data size to be transferred of each DMA command group is equal to the Data Transmission Unit (DTU) size, where a Data transmission unit refers to the smallest unit of transfer Data, e.g., 4KB. The LBAs of the logical addresses corresponding to the DTUs are aligned by 4KB, for example, the LBA range of a DTU can be 0-3KB, but not 1-4 KB). The DMA module 2 performs DMA transfer according to each DMA command 2, where DMA transfer refers to the DMA module 2 performing one data transfer according to each DMA command 2 to transfer data from the memory 2 to the buffer of the DMA device or to transfer data from the buffer of the DMA device to the memory 2.

As an example, the control unit allocates memory space in the memory 2 for one or more data transfer units DTUs, the amount of allocated memory space depending on how much DTUs the data to be transferred by the IO command occupies. To increase memory utilization, the memory space allocated in memory 2 for IO commands may be discontinuous. For example, the memory space allocated by the control unit in the memory 2 for one or more data transfer units DTU is not continuous.

Fig. 5B is a schematic diagram illustrating allocation of a storage space for a data transmission unit DTU according to an embodiment of the present application.

By way of example, in fig. 5B, the control component allocates three data transmission units, DTU1, DTU2, and DTU3, for the IO command; three storage spaces are allocated in the memory 2 for accommodating the DTUs 1, 2 and 3, namely, the storage space 1, the storage space 2 and the storage space 3, wherein the storage space 1 is used for accommodating the DTUs 1, the storage space 2 is used for accommodating the DTUs 2, and the storage space 3 is used for accommodating the DTUs 3, and the storage space 1, the storage space 2 and the storage space 3 are all 4KB in size. The storage space 1 and the storage space 3 are discontinuous storage spaces, and the storage space 2 is a continuous storage space; the storage space 1 comprises a storage area 11 and a storage area 12, wherein the storage area 11 and the storage area 12 are discontinuous, the size of each storage area is 2KB, and the storage area is discontinuous, that is, data corresponding to the DTU1 is stored in 2 areas in the memory 2; the storage space 3 includes a storage area 31 and a storage area 32, wherein the size of the storage area 31 is 1KB, the size of the storage area 32 is 3KB, and the storage area 31 and the storage area 32 are not contiguous, i.e. data corresponding to the DTU3 is also stored in 2 areas in the memory 2. The control section generates a DMA command group 1 from the DTU1, a DMA command group 2 from the DTU2, and a DMA command group 3 from the DTU 3.

Since the storage space 1 corresponding to the DTU1 includes two storage areas, the control unit generates one DMA command 2 from the storage area 11 and one DMA command 2 from the storage area 12, that is, the DMA command group 1 includes two DMA commands 2, namely a DMA command a11 and a DMA command a12. The DMA module 2 moves the data of 2KB from the cache of the DMA device to the storage area 11 or moves the data of 2KB from the storage area 11 to the cache of the DMA device according to the DMA command A11; and the data of 2KB is transferred from the buffer memory of the DMA device to the storage area 12 or the data of 2KB is transferred from the storage area 12 to the buffer memory of the DMA device according to the DMA command a12. Since the memory space 2 corresponding to the DTU2 is a continuous memory space, the control unit generates one DMA command 2 according to the memory space 2, i.e. the DMA command group 2 includes one DMA command 2, which is a DMA command B. The DMA module 2 moves 4KB of data from the buffer memory of the DMA device to the memory space 2 or 4KB of data from the memory space 2 to the buffer memory of the DMA device according to the DMA command B. Since the storage space 3 corresponding to the DTU3 comprises two storage areas, the control unit generates one DMA command 2 from the storage area 31 and one DMA command 2 from the storage area 32, i.e. the DMA command group 3 comprises two DMA commands 2, namely DMA command C31 and DMA command C32 respectively. The DMA module 2 moves 1KB of data from the cache of the DMA device to the storage area 31 or moves 1KB of data from the storage area 31 to the cache of the DMA device according to the DMA command C31; and moving 3KB of data from the buffer memory of the DMA device to the memory area 32 or moving 3KB of data from the memory area 32 to the buffer memory of the DMA device according to the DMA command C32. That is, in the solution provided in the embodiment of the present application, if one or more buffers that accommodate DTUs and are allocated from the memory 2 are not consecutive, the buffer includes a plurality of storage areas, and the sum of the sizes of the plurality of storage areas is 4KB. The DMA device generates one DMA command 2 per memory area per DTU in response to a cache discontinuity accommodating the DTU. By way of example, the set of DMA commands generated according to each DTU includes one or more DMA commands 2.

By way of further example, each DMA command 2 indicates the location of the data currently being read from the DMA device cache, the size of the data to be transferred, and the location of the memory region in memory 2; the location from which the data is read from the DMA device cache is updated based on the size of the data to be transferred. For example, one DMA command 2 is denoted as CMD2 (s _ buffer _ RP, sub _ buffer, length), where s _ buffer _ RP indicates the location of the data currently read from the DMA device cache, and after the data reading is completed, the location s _ buffer _ RP = s _ buffer _ RP + length of the data read from the DMA device cache is updated according to the following formula, and the length is the size of the data to be currently read; sub _ buffer is the address of the memory space in the current memory 2.

Fig. 6A is a schematic flowchart illustrating a DMA transfer according to an embodiment of the present application.

By way of example, in FIG. 6A, an IO command provided by a host to a storage device, a control component of the storage device, in response to receiving the IO command, performs the following steps to implement a DMA transfer of data indicated by the IO command.

Step 601, the control component allocates continuous buffer space in the buffer of the DMA device for the IO command, acquires the SGL according to the IO command, and generates a DMA command 1 (as shown in fig. 4B) according to each descriptor in the SCL, where the DMA command 1 is used to describe DMA transfer from the memory 1 (as shown in fig. 4B, memory 1) to the buffer space of the DMA device.

In step 602, the DMA module 1 (see fig. 4B) in the control unit initiates a first DMA transfer (e.g., a DMA transfer between the memory 1 and the DMA device cache) based on the DMA command 1.

In step 603, the control component allocates one or more data transfer units DTUs to the IO command, and generates a DMA command group according to each DTU, where the DMA command group includes one or more DMA commands 2 (see fig. 4B), and the DMA command 2 is used to describe DMA transfer from the DMA device buffer to the memory space 2.

In step 604, the DMA module 2 in the control unit initiates a DMA transfer (e.g., a DMA transfer of the DMA device cache to memory space 2) based on DMA command 2.

Fig. 6B shows a schematic diagram of DMA transfer provided by an embodiment of the present application.

The DMA module 1 (see also fig. 4B) moves the data in the memory 1 to the DAM device cache by DMA transfer, and the DMA module 2 moves the data in the DAM device cache to the memory 2 by DMA.

By way of example, the aforementioned DMA command for the DMA device to perform a DMA transfer may be generated from the NVMe command. Specifically, in response to receiving the NVMe command, one or more DMA command pairs are generated, wherein a DMA command pair includes one DMA command 1 and one DMA command 2, i.e., DMA command 1 and DMA command 2 occur in pairs, the number of DMA commands 1 being related to the number of DMA commands 2. In some implementation scenarios, the generation may also generate one or more DMA commands 1 and one or more DMA commands 2 upon receipt of the NVMe command, where DMA command 1 and DMA command 2 may not be paired, the number of DMA commands 1 is independent of the number of DMA commands 2, e.g., the number of DMA commands 1 is related to the data block descriptor and/or the hole descriptor indicated by the NVMe command, and the DMA command 2 data is related to the number of DTUs allocated for the NVMe command and the number of storage areas allocated for each DTU in memory 2.

If the NVMe command is a write command, the DMA module 1 may move the data to be moved indicated by the command from the memory 1 to the DMA device cache in response to executing the DMA command 1, and the DMA module 2 may move the data to be moved indicated by the command from the DMA device cache to the memory 2 in response to executing the DMA command 2. It should be understood that, when the DMA module 1 and the DMA module 2 execute data transfer, the DMA module 2 can execute one data transfer based on the DMA command 2 instead of the DMA module 1 executing one data transfer. For example, for a write command, the DMA module 2 may perform a data transfer based on the DMA command 2 in response to the DMA module 1 transferring data from the memory 1 into the DMA device cache not less than one DTU of data. Or the DMA module 1 transfers all data to be transferred by the NVMe command to the DMA device cache, and the DMA module 2 starts to execute data transfer, and the specific time for the DMA module 2 to execute the DMA command is not limited herein.

As an example, in fig. 6B, the control section generates 4 DMA commands 1 (HL 1, HL2, HL3, and HL 4) and 5 DMA commands 2 (DL 1, DL2, DL3, DL4, and DL 5) based on the NVMe command, where HL1 indicates that the size of data 1 to be transferred is 2kb, hl2 indicates that the size of data 2 to be transferred is 2kb, hl3 indicates that the size of data 3 to be transferred is 4KB, and HL4 indicates that the size of data 4 to be transferred is 4KB. DL1 indicates that the data size to be transmitted is 1KB, DL2 indicates that the data size to be transmitted is 2KB, DL3 indicates that the data size to be transmitted is 1KB, DL4 indicates that the data size to be transmitted is 4KB, and DL5 indicates that the data size to be transmitted is 4KB.

The DMA module 1 performs DMA transfer according to the DMA command 1 (HL 1, HL2, HL3, and HL 4). Each DMA command 1 records, for example, a source address, a destination address, and a data length. In the example of fig. 6B, the source address is the memory 1 address and the destination address is the address cached by the DAM device (also referred to as the cache address). Optionally, DMA command 1 also describes a DMA transfer from the DAM device cache to memory 1. For example, the DMA module 1 moves data 1 from the memory 1 to the DMA device cache based on the HL1 command, and then moves data 2 from the memory 1 to the DMA device cache based on the HL2 command, at this time, the data size stored by the DMA device cache is 4KB, the DMA module 2 can perform DMA transmission, for example, the DMA module 2 performs three times of data movement based on DL1, DL2 and DL3 to move 4KB corresponding to the data 1 and the data 2 from the DMA device cache to the memory 2, and then the data 1 and the data 2 are moved from the memory 1 to the memory 2. The DMA module 1 executes HL3 to move the data 3 from the memory 1 to the DMA device cache, and then the DMA module 2 executes DL4 to move the data 3 from the DMA device cache to the memory 2, thereby realizing the movement of the data 3 from the memory 1 to the memory 2. The DMA module 1 performs HL4 to move the data 4 from the memory 1 to the DMA device cache, and then the DMA module 2 performs DL5 to move the data 4 from the DMA device cache to the memory 2, thereby implementing the movement of the data 4 from the memory 1 to the memory 2. For another example, after the DMA module 1 transfers all the data corresponding to the NVMe command to the DMA device cache based on HL1, HL2, HL3, and HL4, the DMA module 2 executes DL1, DL2, DL3, DL4, and DL5 to transfer all the data from the DMA device cache to the memory 2, and the process of transferring data by the DMA module 1 and the DMA module 2 is not described herein again.

Further, since the DMA command 1 executed by the DMA module 1 can be generated by the hole descriptor, it has been described above that the cache of the DMA device corresponding to the DMA command 1 corresponding to the hole descriptor is filled with invalid data, and the invalid data is generally not desired to store data in the hole or move data in the hole to the host. In the data transfer process, in order to identify whether the transferred data is invalid data or valid data. When the control unit generates the DMA command 2, if the DMA device cache space has invalid data, for the address of the DMA device cache space corresponding to the invalid data, when the DMA command 2 corresponding to the address is generated, the control unit further marks the range of the invalid data stored in the DMA device cache space in the DMA command 2, so that the invalid data can be marked by an identifier so that the DMA module 2 can recognize the existence of the invalid data when the DMA module 2 reads the invalid data from the DMA device cache space based on the DMA command 2.

Also by way of example, the DMA module 2 generates an invalid signal on the bus indicating that the data is invalid when transferring to the invalid data portion in response to the DMA command 2 processing the marked invalid data range. For example, the invalidation signal is a WSTRB signal indicating invalidation of data in compliance with the AXI protocol.

FIG. 6C is a diagram illustrating a DMA command generated according to an IO command according to an embodiment of the present application.

Referring to FIG. 6C, by way of example, IO commands provided by the host to the storage device indicate one or more DMA commands 510 for transferring data to the storage device.

The control component of the storage device, in response to receiving the IO command, allocates contiguous memory space in the DMA device cache (see also fig. 4B) for receiving the complete data to be transferred by the IO command, such that the contiguous memory space allocated in the DMA device cache can accommodate the complete data to be transferred by the IO command. Alternatively, if the DMA device cache temporarily fails to provide contiguous memory space to accommodate the complete data to be transferred for the IO command, the control component suspends processing of the IO command until sufficient contiguous memory space is available from the DMA device cache. The control unit generates 540 one or more DMA commands with addresses in the DMA device cache that are allocated to the memory space of the complete data to be transferred by the IO command. Each DMA command 540 indicates a transfer of data from memory 1 (see also FIG. 4B) to the DMA device cache. For each DMA command 510, a corresponding DMA command 540 is generated by adding to it the address of the DMA device cache as the destination address. Alternatively, DMA command 540, describes 3 consecutive DMA transfers from memory 1 to the DMA device cache of each of the source address and the destination address.

In response to generating DMA command 540, DMA module 1 (see FIG. 4B) initiates a DMA transfer from memory 1 to the DMA device cache. In response to completion of the DMA transfer indicated by DMA command 540, completion of execution of the IO command (write command) corresponding to DMA command 510 may be indicated to the host.

And in response to generating DMA command 540, beginning to generate DMA command 550.DMA command 550 is used to describe a DMA transfer from a DMA device cache to memory 2. The control unit allocates one or more pieces of memory space in the memory 2 to accommodate the complete data to be moved by the DMA command 510 (DMA command 540). By way of example, 6 segments of memory space are allocated from memory 2 to accommodate the complete data to be moved by DMA command 510. For each DMA command 540, its DMA device cache address is taken as the source address of DMA command 550, e.g., for one DMA command 540 (e.g., DMA command 540 numbered 0), DMA device cache 0x2C00, the address of one of the memory segments retrieved from memory 2 (noted S1) (e.g., address 0x0800 of device memory (memory 2)) is taken as the destination address of one DMA command 550 (e.g., DMA command 550 numbered 0). Since the size of the memory space segment S1 of the memory 2 is 0x0800, it is not enough to accommodate all the data indicated by the DMA command 540, in the DMA command 550, the length of the data indicated for transmission is equal to the size of the memory space segment S1, and another DMA command 550 (such as the DMA command 550 with the number 1) is also generated to continue to transmit and cache the data indicated by the DMA command 540, and the remaining data (address 0x3400 and length 0x0400 in the DMA device cache) of the DMA command 540 is moved to another memory space segment (S2) of the memory 2 (for example, address 0x2400 of the device memory (memory 2)) so that the DMA command 550 (the DMA command 550 with the number 1) has a source address (address 0x3400 of the DMA device cache), a destination address (address 0x2400 of the memory 2) and a data length of 0x0400.

In response to generating one or more DMA commands 550, DMA module 2 (see FIG. 4B) initiates a DMA transfer from the DMA device cache to memory 2. And in response to completing the execution of the DMA transfer corresponding to DMA command 550, may free the memory space occupied by DMA command 550 in the DMA device cache.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (10)

1. A method of DMA transfer, comprising:

allocating continuous cache space for an IO command in a cache of DMA equipment, acquiring SGL (secure gate markup language) according to the IO command, and generating a first DMA command according to each descriptor in the SCL, wherein the first DMA command is used for describing DMA transmission from a first memory space to the cache space of the DMA equipment;

initiating a first DMA transfer based on the first DMA command;

one or more Data Transmission Unit (DTU) is distributed for the IO command, a DMA command group is generated according to each DTU, the DMA command group comprises one or more second DMA commands, and the second DMA commands are used for describing DMA transmission from the cache space to a second memory space;

initiating a second DMA transfer based on the second DMA command.

2. The method of claim 1, wherein generating the first DMA command according to each descriptor in the SCL comprises:

generating a first DMA command according to each hole descriptor in the SCL; and

a first DMA command is generated from each data block descriptor in the SCL.

3. The method of claim 1 or 2, wherein allocating a continuous buffer space in a buffer of a DMA device for IO commands comprises:

each first DMA command is allocated contiguous DMA device cache space.

4. The method of claim 3, wherein the buffer spaces allocated to the first DMA command generated by the adjacent descriptor in the SCL are adjacent, and the buffer space corresponding to the first DMA command generated by the following descriptor is located after the buffer space corresponding to the first DMA command generated by the preceding descriptor.

5. The method according to any one of claims 2 to 4,

according to the first DMA command generated by the hole descriptor, invalid data is filled in a cache of the DMA device corresponding to the first DMA command, so that data indicated by the subsequent first DMA command can be written into a correct position.

6. The method of any one of claims 1-5, further comprising: one or more buffers housing DTUs are allocated in the second memory for IO commands.

7. The method of claim 6, wherein if one or more DTU-containing buffers allocated from the second memory are not contiguous, the buffers comprise a plurality of memory regions, and the sum of the plurality of memory regions is 4KB.

8. The method of claim 7, wherein in response to a cache discontinuity accommodating the DTUs, generating a second DMA command per memory region per DTU.

9. The method of any of claims 5-8, wherein responsive to the presence of invalid data from the data to be read in the DMA device cache space based on the second DMA command, the range in the DMA device cache space in which the invalid data is stored is also marked in the second DMA command.

10. A control component, comprising: an SGL unit and a DMA device;

the SGL unit, in response to receiving an IO command, allocates continuous cache space for the IO command in a cache of DMA equipment, acquires the SGL according to the IO command, and generates a first DMA command according to each descriptor in the SCL, wherein the first DMA command is used for describing DMA transmission from a first memory space to the cache space of the DMA equipment; and

one or more Data Transmission Unit (DTU) is distributed for the IO command, a DMA command group is generated according to each DTU, the DMA command group comprises one or more second DMA commands, and the second DMA commands are used for describing DMA transmission from the cache space to a second memory space;

the DMA device initiating a first DMA transfer based on the first DMA command; and initiating a second DMA transfer based on the second DMA command.

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