CN214376421U

CN214376421U - FTL accelerator and control component

Info

Publication number: CN214376421U
Application number: CN202023331657.6U
Authority: CN
Inventors: 王祎磊; 丁胜涛
Original assignee: Chengdu Starblaze Technology Co ltd
Current assignee: Chengdu Starblaze Technology Co ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-10-08
Anticipated expiration: 2030-12-30

Abstract

FTL accelerator and control components are provided. The provided FTL accelerator comprises a read address calculation unit, a read data selection unit, a read address sending unit and a read data receiving unit; the read address calculation unit calculates the address of an entry of a physical FTL table corresponding to an entry of a logical FTL table to be accessed according to the index (L) of the entry of the logical FTL table to be read; the read address calculation unit further indicates to the read data selection unit a portion of the data read out from the memory that belongs to an entry of the physical FTL table to be accessed; the read data selection unit acquires a part belonging to the entry of the physical FTL table to be accessed from the data read out from the memory indicated by the read address calculation unit, and expands the entry of the physical FTL table to be accessed to obtain the entry of the logical FTL table to be accessed.

Description

FTL accelerator and control component

Technical Field

The present application relates to memory technology, and in particular, to FTL accelerators and control components.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high speed Peripheral Component Interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The storage device 102 includes an interface 103, a control section 104, one or more NVM (Non-Volatile Memory) chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 108, the NVM chip 105, and the DRAM 110, and also used for memory management, physical address mapping of host logical addresses to NVM chips, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 140 and may access data of the DRAM 110. FTL tables and/or cached IO command data are stored in DRAM.

Control section 104 includes a flash interface controller (otherwise known as a media interface, a media interface controller, a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to the interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

NVM storage media typically store and read data on a page basis. And data is erased in blocks. A block (also referred to as a physical block) on an NVM storage medium contains a plurality of pages. Pages on the storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. Physical pages may also have other sizes.

In the storage device, mapping information from logical addresses to physical addresses is maintained by using a Flash Translation Layer (FTL). The logical addresses constitute storage space of the storage device as perceived by upper level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented in the prior art using an intermediate address modality. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address. Optionally, a host accessing the storage device provides the FTL.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table (also called an L2P table). Typically, the data entry of the FTL table records the address mapping relationship in units of storage units of a specified size (e.g., 512 bytes, 2KB, 4KB, etc.) in the storage device.

SUMMERY OF THE UTILITY MODEL

As the capacity of memory devices increases, the size of FTL tables increases to record more memory locations, thereby requiring more memory to accommodate the FTL tables. The size of each entry of the FTL table also needs to be increased in order to address the updated memory location. For example, a 32-bit size FTL table entry can address 2^32 data units. If each data unit has a size of 4KB, 2^32 data units correspond to 16TB storage capacity, and correspondingly, the size of the FTL table is 16GB, and at least 16GB of memory space needs to be occupied. And the storage device has a variety of capacities, e.g., the capacity of the storage device provided to the user is, for example, 4TB, the size of the FTL table itself may be 4 GB. However, to provide 4TB storage, if each data unit is 4KB, then the number of data units that the FTL table needs to manage is 2^30, each entry of the corresponding FTL table only needs 30 bits in size, and the size of the FTL table is 30 ^ 2^30 bits (and 3.75GB, less than 4 GB). However, due to the limitations of the addressing modes of the memory chip and the CPU, the CPU addressing channel uses an integer multiple of 32 bits or bytes as the data width of one addressing, and the memory chip also typically uses an integer multiple of bytes as the data width. Thus, if the entry size of the FTL table is, for example, 30 bits, although the overall size of the FTL table is reduced, the entry crossing byte boundaries therein require, for example, 2 or more bus accesses or memory accesses to be loaded to the CPU, thereby significantly increasing the time for loading the FTL table entry and limiting the performance of the memory device.

In order to reduce the amount of memory space occupied by FTL tables and reduce or eliminate the impact of non-byte aligned FTL table entries on accessing FTL table entries by a CPU or other devices within a chip when providing storage devices of multiple capacities, according to embodiments of the present application, a compressed FTL table is provided. The entry size of the compressed FTL table provided may not be an integer multiple of bytes. And the compressed FTL table entries are tightly arranged in memory without leaving unused memory space between entries for byte alignment. And it is also desirable according to embodiments of the present application for a CPU or other device to access FTL tables in its native manner, byte-aligned or aligned by integer multiples of bytes, thereby eliminating the impact on the CPU or other device caused by the use of compressed FTL tables. It is also desirable to have a method for processing FTL tables with a hardware accelerator to share the burden introduced by executing software to access FTL tables for the CPU and to improve FTL table access performance.

According to a first aspect of the present application, there is provided a first FTL accelerator according to the first aspect of the present application, including a read address calculating unit, a read data selecting unit, a read address transmitting unit, and a read data receiving unit; the read address calculation unit calculates addresses of entries of a physical FTL table corresponding to the entries of the logical FTL table to be accessed according to indexes (L) of the entries of the logical FTL table to be read, wherein the size of the entries of the logical FTL table is M bits, the size of the entries of the physical FTL table is N bits, M and N are positive integers, and M > N, and the entries of the logical FTL table correspond to the entries of the physical FTL table one to one; the read address calculation unit is coupled with the read address sending unit, and the read address sending unit accesses the memory by using the address provided by the read address calculation unit; the read data receiving unit receives the data provided by the memory and provides the data to the read data selecting unit; the read address calculation unit further indicates to the read data selection unit a portion of the data read out from the memory that belongs to an entry of the physical FTL table to be accessed; the read data selection unit acquires a part belonging to the entry of the physical FTL table to be accessed from the data read out from the memory indicated by the read address calculation unit, and expands the entry of the physical FTL table to be accessed to obtain the entry of the logical FTL table to be accessed.

A first FTL accelerator according to a first aspect of the present application provides a second FTL accelerator according to the first aspect of the present application, further comprising: a read address cache unit and a read data cache unit; the read address cache unit stores an index (L) of an entry of a logical FTL table to be accessed; the read data cache unit stores the entry of the logic FTL table to be accessed; the read address calculation unit is coupled with the read address cache unit and acquires an index (L) from the read address cache unit; the read data selection unit stores a part of the data read from the memory, which belongs to an entry of a physical FTL table to be accessed, in a read data cache; the entry of the physical FTL table to be accessed stored in the read data cache is expanded to the size of the entry of the logical FTL table to be accessed to obtain the entry of the logical FTL table to be accessed.

According to the first aspect of the present applicationA first or second FTL accelerator of the plane, providing a third FTL accelerator according to the first aspect of the present application, wherein the address of the entry of the physical FTL table corresponding to the entry of the logical FTL table to be accessed, which is calculated by the read address calculation unit according to the index (L), is in the storage space of the physical FTL table in byte address

Starting with the nth mod8 bit of the memory, stores the address of one or more bytes of N-bit data.

According to one of the first to third FTL accelerators of the first aspect of the present application, there is provided the fourth FTL accelerator according to the first aspect of the present application, wherein if N mod8 is 0, the address of the entry of the physical FTL table corresponding to the entry of the logical FTL table to be accessed, which is calculated by the read address calculation unit according to the index (L), is a byte address

Starting with the Nth mod8 bit

An address of a byte; if L × N mod8 is not 0, and (N mod 8) - (8-L × N mod 8)<If it is 0, the read address calculation unit calculates an address of an entry of the physical FTL table corresponding to an entry of the logical FTL table to be accessed, which is calculated according to the index (L), as a byte address

Start at bit N mod8

An address of a byte; if L × N mod8 is not 0, and (N mod 8) - (8-L × N mod 8)>0, the read address calculation unit calculates the address of the entry of the physical FTL table corresponding to the entry of the logic FTL table to be accessed according to the index (L) and is a byte address

Start at bit N mod8

An address of a byte.

According to one of the first to fourth FTL accelerators of the first aspect of the present application, there is provided the fifth FTL accelerator according to the first aspect of the present application, wherein if N mod8 is 0, a portion of the data read out from the memory indicated by the read address calculation unit to the read data selection unit, which belongs to an entry of the physical FTL table to be accessed, includes an address in bytes

Starting with the Nth mod8 bit

Complete data for a byte of address; if L × N mod8 is not 0, the part of the data read from the memory and indicated by the read data selection unit, which belongs to the entry of the physical FTL table to be accessed, includes bits L × N mod8 to the last bit of the byte with the byte address of L × N/8; if (L +1) × N mod8 is not 0, the portion of the data read out from the memory indicated by the read address calculation unit to the read data selection unit, which belongs to the entry of the physical FTL table to be accessed, includes the first (L +1) × N mod8 bits of the byte having the byte address (L +1) × N/8.

According to one of the first to fifth FTL accelerators according to the first aspect of the present application, there is provided a sixth FTL accelerator according to the first aspect of the present application, further comprising: the device comprises a write address calculation unit, a write command processing unit and a write data splicing unit; the write address calculation unit calculates the address of an entry of a physical FTL table corresponding to the entry of the logical FTL table to be updated according to the index (L) of the entry of the logical FTL table to be updated; the data writing splicing unit acquires corresponding N-bit physical FTL table entries from the to-be-updated logic FTL table entries; the write command processing unit is coupled with the write address calculation unit, and writes the entries of the physical FTL table with N bits acquired by the write data splicing unit into the addresses of the entries of the physical FTL table corresponding to the entries of the logical FTL table to be updated, which are provided by the write address calculation unit.

According to a sixth FTL acceleration of the first aspect of the present application, there is provided a seventh FTL accelerator according to the first aspect of the present application, wherein the write address calculation unit further calculates one or two addresses to be read out from the physical FTL table according to an index (L) of an entry of the logical FTL table to be updated, and provides the one or two addresses to be read out from the physical FTL table to the write command processing unit; the write command processing unit reads data from a memory according to the one or two addresses to be read out from the physical FTL table; the write address calculation unit further indicates to the write data selection unit a portion of the data read out from the memory that does not belong to an entry of the physical FTL table to be updated; the write data selecting unit acquires a part which does not belong to the entry of the physical FTL table to be updated from the data read out from the memory according to the instruction of the write address calculating unit, and provides the part which does not belong to the entry of the physical FTL table to be updated and is acquired from the data read out from the memory to the write data splicing unit; the write data splicing unit splices the corresponding N-bit physical FTL table entries acquired from the logical FTL table entries to be updated with the part of the entries which are not included in the physical FTL table to be updated and acquired from the data read out from the memory and provided by the write data selection unit; and the writing command processing unit is used for writing the N-bit entries of the physical FTL table provided by the writing data splicing unit and the part which is acquired from the data read out from the memory and does not belong to the entries of the physical FTL table to be updated into the addresses of the entries of the physical FTL table corresponding to the entries of the logical FTL table to be updated, wherein the addresses are provided by the writing address calculation unit.

According to a sixth or seventh FTL accelerator of the first aspect of the present application, there is provided the eighth FTL accelerator of the first aspect of the present application, wherein if N mod8 is 0, the address of the entry of the physical FTL table calculated by the write address calculation unit from the index (L) is in byte address

Starting with the Nth mod8 bit

An address of a byte; if L × N mod8 is not 0, and (N mod 8) - (8-L × N mod 8)<When the write address calculation unit calculates the address of the entry of the physical FTL table according to the index (L) as a byte address

Start at bit N mod8

An address of a byte; if L × N mod8 is not 0, and (N mod 8) - (8-L × N mod 8)>0, the address of the entry of the physical FTL table calculated by the write address calculation unit according to the index (L) is a byte address

Start at bit N mod8

An address of a byte.

According to a seventh or eighth FTL accelerator of the first aspect of the present application, there is provided a ninth FTL accelerator according to the first aspect of the present application, wherein if L × N mod8 is not 0, a portion of the data read out from the memory indicated by the write address calculation unit to the write data selection unit, which does not belong to an entry of the physical FTL table to be updated, includes first L N mod8 bits of a byte having a byte address of L × N/8; if (L +1) × N mod8 is not 0, the write address calculation unit instructs the write data selection unit to read out the data from the memory, the part not belonging to the entry of the physical FTL table to be updated, including the (L +1) × N mod8 bits to the last bit of the byte having the byte address (L +1) × N/8.

According to one of the sixth to ninth FTL accelerators of the first aspect of the present application, there is provided the tenth FTL accelerator according to the first aspect of the present application, further comprising a write address transmitting unit; the write command processing unit comprises a read address generating unit and a write address generating unit; the read address generating unit reads data from a memory through the read address sending unit by using the one or two addresses to be read from the physical FTL table; the read data receiving unit receives data read from a memory; the write address generating unit sends the address of the entry of the physical FTL table corresponding to the entry of the logical FTL table to be updated, which is provided by the write address calculating unit, through the write address sending unit.

According to one of the first to tenth FTL accelerators of the first aspect of the present application, there is provided an eleventh FTL accelerator according to the first aspect of the present application, further comprising: a master device interface for coupling to a bus; the read address sending unit sends the read address to a bus through a main equipment interface; the read data receiving unit acquires the read data from the bus through the main equipment interface; the write address sending unit sends a write address to a bus through the main equipment interface; the write data transmitting unit transmits data to be written to the bus through the host interface.

According to one of the first to eleventh FTL accelerators according to the first aspect of the present application, there is provided a twelfth FTL accelerator according to the first aspect of the present application, further comprising: a slave device interface for coupling to a bus; the read address cache stores an index (L) of an entry of a logical FTL table to be read, which is acquired through a device interface; the read data cache stores entries of a logical FTL table to be read to be transmitted through the slave device interface; the write address cache stores an index (L) of an entry of the logical FTL table to be written, which is acquired through the device interface; the write data cache stores entries of the logical FTL table to be written, which are obtained through the slave device interface.

According to a second aspect of the present application, there is provided a first control component according to the second aspect of the present application, comprising: the system comprises a first master device, an FTL accelerator, a memory controller and a bus; the FTL accelerator couples to the bus through a host device interface; the memory controller is coupled with the memory through a slave device interface and the bus; the FTL accelerator described above is an FTL accelerator according to one of the first to twelfth aspects of the present application.

According to a second aspect of the present application, there is provided a method of operating a logical FTL accelerator in a wireless communication system, comprising the steps of providing, by a first master device, an index (L) of an entry of a logical FTL table to be read to the FTL accelerator; the FTL accelerator accesses an entry of a physical FTL table in the memory corresponding to an index (L) through a master interface in response to the index (L) provided by the first master.

According to the second control unit of the second aspect of the present application, there is provided the third control unit of the second aspect of the present application, wherein the FTL accelerator obtains an entry corresponding to the index (L) of the physical FTL table obtained by accessing the memory through a host device interface, and generates an entry corresponding to the index (L) of the logical FTL table to provide to the first host device.

According to one of the first to third control means of the second aspect of the present application, there is provided the fourth control means according to the second aspect of the present application, wherein the FTL accelerator is further coupled to the bus through a slave interface; the first master accesses a first address space with an index (L); forwarding, by the bus, an index (L) provided by the first master device to the FTL accelerator through a slave interface according to a first address space; the bus forwards access to a second address space by the first master to the memory controller.

According to one of the first to third control components of the second aspect of the present application, there is provided a fifth control component according to the second aspect of the present application, wherein the first master device is directly coupled to the FTL accelerator; the first master providing an index (L) directly to the FTL accelerator based on the index (L) being in a first address space; the first master device sending an access to a second address space to the bus; the bus forwards access to a second address space to the memory controller according to the second address space.

According to one of the first to fifth control means of the second aspect of the present application, there is provided the sixth control means of the second aspect of the present application, wherein the first master device is a CPU.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 illustrates a block diagram of a prior art storage device;

fig. 2A illustrates a schematic diagram of a logical FTL table and a physical FTL table according to an embodiment of the present application;

FIG. 2B shows a schematic diagram of a compressed FTL table in memory according to an embodiment of the present application;

FIG. 3 illustrates a block diagram of a control component including an FTL accelerator in accordance with an embodiment of the present application;

FIG. 4 illustrates a block diagram of an FTL accelerator in accordance with an embodiment of the present application;

FIG. 5A illustrates a flow diagram of an FTL accelerator processing a read request to a logical FTL table according to an embodiment of the present application;

FIG. 5B illustrates a flow diagram of an FTL accelerator processing a write request to a logical FTL table in accordance with an embodiment of the present application;

fig. 6A and 6B are schematic diagrams illustrating reading out corresponding entries of logical FTLs from a physical FTL table;

fig. 6C and 6D are schematic diagrams illustrating writing of corresponding entries of a logical FTL table to a physical FTL table; and

fig. 7 illustrates a block diagram of a control component including an FTL accelerator according to yet another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 2A is a schematic diagram illustrating a logical FTL table and a physical FTL table according to an embodiment of the present application.

According to embodiments of the present application, a logical FTL table and a physical FTL table are provided. The logical FTL table is the FTL table perceived by the device accessing the FTL table. The device accessing the FTL table is another bus device such as a CPU or control unit (see also fig. 1, control unit 104). The physical FTL table is an FTL table stored in a memory (e.g., the DRAM 104 of fig. 1).

By way of example, the logical FTL table and the physical FTL table each include a plurality of entries, and the entries of the FTL table are addressed by logical addresses (denoted as LBAs). The entries of the logical FTL table and the physical FTL table are in one-to-one correspondence, so that the entries have the same number of entries, and the number of the entries of the logical FTL table and the physical FTL table is recorded as MaxLBA, the size of the entry of the logical FTL table is M bits, the size of the entry of the physical FTL table is N bits, where M and N are both positive integers.

Optionally, to facilitate access to the logical FTL table by, for example, a CPU, the size of M is an integer multiple of, for example, 8 or 32, so that entries of the logical FTL table are aligned in bytes or DWORD (double word). Referring to fig. 2A, from the perspective of a CPU accessing a logical FTL table, the logical FTL table includes maxla entries, each entry has a size of M bits (in the example of fig. 2A, M is 64), and the entries of the logical FTL table are sequentially arranged end to end in a storage space, and the storage space of the logical FTL table is indexed by a logical address (LBA) to obtain a corresponding FTL table entry. Recorded in the entries of the FTL table are addresses for NVM chips (called physical addresses, noted PBA). Since the logical FTL table entries are byte or DWORD aligned, the start address of each entry thereof in the memory space is located at the start position of the byte or doubleword, and the end of the entry is located at the end position of the byte or doubleword. In the example of fig. 2A, when the CPU accesses the corresponding entry of the FTL table based on the logical address (LBA) as an index, the address of the corresponding entry of the FTL table is obtained by, for example, LBA × 8 (64 bits correspond to 8 bytes).

While for the physical FTL table, the size of each entry is N bits, N being any positive integer less than M. The value of N is determined based on the number of data units provided by the NVM chip addressed by the FTL table entry. For example, to address 2^30 data units, then N is 30. In general, if an entry of the physical FTL table can address one of 2^ N data units, then N ^ N. By way of example, in fig. 2A, N is 33. In the physical FTL table, each entry is stored end to end in a storage space provided by the memory. So that the start and/or end positions of some entries are not located at byte boundaries.

Fig. 2B shows a schematic diagram of a compressed FTL table in a memory according to an embodiment of the present application.

By way of example, the compressed FTL table starts storing at 0 address of the memory. The bit width of the memory is e.g. 64 bits, i.e. e.g. 64 bits (8 bytes) of data are read out of the memory at a time. The entries of the compressed FTL table are stored end-to-end in the memory, and there is no unused memory space between adjacent entries, so that the start address and/or the end address of an entry is not located at the byte boundary of the memory space.

In fig. 2B, the label in the form of PBA (i) represents one of the entries of the compressed FTL table (whose value is the i-th physical address (PBA) of the FTL table, i being an integer, for example). Referring to fig. 2B, 33 bits from the 0 byte address of the memory store a compressed FTL table entry having a value of PBA (0), 34 bits to 64 bits from the 0 byte address of the memory store the first 31 bits of the compressed FTL table entry PBA (1), and the remaining 2 bits of the compressed FTL table entry PBA (1) are stored at the position of the 8 byte address of the memory. Next, the compressed FTL table entry PBA (2) is stored at 3 bits to 35 bits from the beginning of the memory 8 byte address, the first 29 bits of the compressed FTL table entry PBA (3) are stored at 36 bits to 64 bits from the beginning of the memory 8 byte address, the remaining 4 bits of the compressed FTL table entry PBA (4) are stored at the beginning of the memory 12 byte address, the compressed FTL table entry PBA (5) is stored at 5 bits to 37 bits from the beginning of the memory 12 byte address, and next is the compressed FTL table entry PBA (6).

Thus, one or more entries of the physical FTL table are not aligned in the memory by byte boundary or by read data bit width of the memory. The physical FTL table thus occupies a smaller memory space in the memory than the CPU-perceived logical FTL table size.

According to the embodiment of the application, the CPU accesses the logical FTL table by taking the logical address LBA as an index, the FTL accelerator calculates the address of the corresponding entry in the physical FTL table in the memory according to the logical address LBA, and acquires the entry of the FTL table to be accessed through one or more memory accesses so as to respond to the CPU accessing the logical FTL table.

According to an embodiment of the present application, an entry of a logical FTL table indexed by an LBA calculates a storage location of a corresponding entry in a physical FTL table with respect to a start address of the physical FTL table: if LBA × Nmod 8 is 0(mod represents modulo operation), then the corresponding entry in the physical FTL table is stored in the N-bit storage space starting at the location of byte address LBA × N/8, the N-bit storage space occupying N/8 or N/8+1 bytes; if LBA N mod8 is not 0, then the corresponding entry in the physical FTL table is stored in an N-bit storage space starting with LBA N Nmod 8 bits after the location of byte address LBA/8, which occupies N/8+1 or N/8+2 bytes. For example, if LBA × Nmod 8 is not 0, and (N mod 8) - (8-LBA × N mod 8) <equalto 0, the number of bytes occupied by the corresponding N-bit storage space is N/8 (rounded down) + 1; if LBA × Nmod 8 is not 0, and (N mod 8) - (8-LBA × N mod 8) >0, the number of bytes occupied by the corresponding N-bit storage space is N/8 (rounded down) + 2.

Fig. 3 illustrates a block diagram of a control component including an FTL accelerator according to an embodiment of the present application.

The control components include, for example, a CPU, a media interface controller (NF I), an FTL accelerator, and a memory controller. The CPU, media interface controller (NF I), FTL accelerator, and/or memory controller are coupled, for example, by a bus. The control unit is also coupled to an external memory (DRAM of fig. 3), and the memory controller is used to access the external memory. Optionally, each device of the bus is assigned an address space on the bus. So that the bus forwards the access request to the device corresponding to the accessed address. For example, the FTL accelerator is allocated 0-8GB of bus address space, the memory controller is allocated 16-32 GB of bus address space, and the NF I is allocated, for example, 8GB of starting 1MB of address space. From the CPU's perspective, the 0-8GB address space occupied by the FTL accelerator accommodates the logical FTL table. While the physical FTL tables are accommodated in the 16GB-32GB bus address space occupied by the memory controller. Requests for CPU access to 0-8GB of bus address space are forwarded by the bus to the FTL accelerator for processing, while requests for CPU access to 16-32 GB of bus address space are forwarded by the bus to the memory controller for processing.

According to an embodiment of the present application, the FTL accelerator includes a slave interface and a master interface. The FTL accelerators are respectively coupled to the bus by slave and master device interfaces. Such that one or more devices (e.g., CPU, NF I) of the control unit are accessible to the FTL accelerator through the slave interface, with the FTL accelerator being accessed as a bus slave, and the FTL accelerator being accessible to one or more devices (e.g., memory controller) of the control unit through the master interface as a master.

As an example, the CPU looks like the logical FTL table is located in a specified memory space, for example, 8GB memory space starting from 0 byte, and each entry size of the logical FTL table is M ═ 64 bits (8 bytes). Each entry size of the physical FTL table is 33 bits.

Thus, the CPU issues an access request (indicated by (1) in fig. 3) to the entry (index is LBA) of the logical FTL table to the bus, and the accessed address is LBA × 8 and 8 bytes in length. The bus sends the access request from the CPU to the FTL accelerator for processing according to the address range of 0-8GB indicated by the access request. The bus provides the access request to the FTL accelerator through its slave interface (indicated by (2) in fig. 3). The FTL accelerator determines the storage location of the corresponding 33-bit entry in the physical FTL table according to the received address (LBA × 8) indicated in the access, and issues 1 or more memory access requests to the memory controller through the bus through its master interface to fetch the 33-bit entry of the physical FTL table from the DRAM (indicated by (3) in fig. 3). The FTL accelerator sends an access request to the bus through its master interface, and the bus sends the access request to the memory controller process according to the address range accessed by the bus request being, for example, 16GB to 32GB (also indicated by (3) in fig. 3). So that the starting address of the memory controller's address space range on the bus is 16GB, the 33-bit entry determined by the FTL accelerator is stored in the physical FTL table with an offset value, e.g., 16GB, of the memory controller's address space range on the bus. The memory controller accesses the DRAM in response to a request for an access from the FTL accelerator, and provides a processing result of the access request to the FTL accelerator through a host interface of the FTL accelerator. The FTL accelerator completes its access to the entries of the logical FTL table (indicated by (4) in fig. 3) from its slave interface to the CPU according to the processing result provided by the memory controller. For example, if the CPU is to read a logical FTL table entry, the FTL accelerator provides a 64-bit entry to the CPU according to the size of the logical FTL table entry in response to its access request. It will be appreciated that the entry size of the physical FTL table recorded in the DRAM is, for example, 33 bits, and the FTL accelerator fills the 33-bit entry fetched from the DRAM with data and provides the CPU with 64-bit entries.

While accesses to the DRAM are byte aligned, the FTL accelerator accesses a plurality of bytes of the DRAM for accessing entries of the physical FTL table, and some bits of the bytes do not belong to the entries of the physical FTL table to be accessed. The FTL accelerator also avoids corruption of bits that do not belong to entries of the physical FTL table to be accessed.

Fig. 4 illustrates a block diagram of an FTL accelerator according to an embodiment of the present application.

The FTL accelerator comprises a write address cache, a write data cache, a read address cache, a read data cache, a write address calculation unit, a write data splicing unit, a read address calculation unit, a read data selection unit, a write command processing unit, a write data splicing unit, a read address sending unit, a write address sending unit, a read data receiving unit and a write data sending unit. And the FTL accelerator further comprises a slave interface and a master interface. The slave interface and the master interface are each coupled to a bus.

The write address cache, the write data cache, the write address calculation unit, the write data splicing unit, the write command processing unit, the write data selection unit, the write address sending unit and the write data sending unit of the FTL accelerator are used for processing the update request of the logic FTL table. The read address cache, the read data cache, the read address calculation unit, the read data selection unit, the read address sending unit and the read data receiving unit of the FTL accelerator are used for processing read requests of the logic FTL table. Wherein the read address sending unit and the read data receiving unit are both used in processing update requests and read requests to the logical FTL table.

The write address cache, write data cache, read address cache, and read data cache are each coupled to a slave interface to receive and cache logical FTL table update requests/read requests sent to the FTL accelerator by other bus masters, such as a CPU. For a logical FTL table update request, an address to be accessed by the update request is recorded in the write address cache, and the cached address is, for example, an address (e.g., logical address LBA) for accessing an entry of the logical FTL table. The FTL accelerator is configured with a starting address of a physical FTL table in a memory, a bus address of the memory, an entry size of the physical FTL table (N bits, see also fig. 2A) and an entry size of a logical FTL table (M bits, see also fig. 2A). The write data cache records the entry of the logical FTL table indicated by the update request. The logical FTL table entry writing a data cache record is, for example, M bits in size.

As an example, the FTL table update request indicates that the logical address LBA is the same as an entry E of the logical FTL table, and the first M bits of the entry E are the same as the width of the corresponding entry of the physical FTL table, and need to be written into the physical FTL table, while other bits of the entry E are discarded.

And the write address calculation unit is used for calculating the address of the entry corresponding to the logical address LBA in the memory of the physical FTL table to be updated according to the logical address LBA acquired from the write address cache, the configured physical FTL table entry size N and the address of the physical FTL table in the memory.

If LBA × Nmod 8 is 0 and N mod8 is 0, the corresponding entry in the physical FTL table is stored in the N-bit storage space starting from the position of byte address LBA × N/8, and the write address calculation unit calculates that consecutive entries starting from byte address LBA × N/8 are obtained

Byte address of a byte. All bits of these bytes will be updated, wherein

Indicating rounding up. If LBA × Nmod 8 is 0 and N mod8 is not 0, then the byte address is (LBA +1) × N/8 bytes, only the first (LBA +1) × N mod8 bits are to be updated.

If LBA N mod8 is not 0, then the corresponding entry in the physical FTL table is stored in N-bit storage space starting with LBA N Nmod 8 bits after byte address LBA N/8 (rounded down), which occupies N/8 (rounded down) +1 or N/8 (rounded down) +2 bytes. The write address calculation unit calculates the byte addresses of consecutive N/8 (rounded down) +1 or N/8 (rounded down) +2 bytes from the byte address LBA N/8. All or some of the bits of these bytes will be updated. And the write address calculation unit also determines the number of bytes (N/8 (rounded down) +1 or N/8 (rounded down) + 2) in the memory that stores the entry of the physical FTL table to be updated.

The write data splicing unit splices N bits used for the entry of the physical FTL table in the entry of the M-bit logic FTL table in the write cache with partial bits read out from the physical FTL table and storing the byte of the entry of the physical FTL table to be updated so as to obtain the complete content of each byte of the entry of the FTL table to be updated. For example, if LBA × Nmod 8 is 0, the data length after data concatenation by the write data concatenation unit is LBA × N/8 bytes, the first N bits of these data are from N bits of the cache for the entry of the physical FTL table, the optional remaining bits are from a part of bits of the byte read from the physical FTL table and storing the entry of the physical FTL table to be updated, the byte address of this part of bits in the physical FTL table is (LBA +1) × N/8 (rounded down), and the part of bits is located at the last 8- (LBA +1) × N mod8 bits of this byte. If LBA N mod8 is not 0, then the data size after data concatenation by the write data concatenation unit is N/8 (rounded down) +1 or N/8 (rounded down) +2 bytes, with the first LBA N mod8 bits from the first LBA N mod8 bits of the byte in memory addressed to LBA N/8, the next N bits from the N bits of the cache for the physical FTL table entry, and optionally the remaining bits. If (LBA × N + N) mod8 is not 0, the remaining bits come from the last partial bits (the last 8- (LBA × N + N) mod8 bits) of the byte to be updated in the memory (the byte address is (LBA × N + N)/8, rounded down), and if (LBA × N + N) mod8 is 0, the remaining bits do not exist.

It is understood that, for various storage manners of the physical FTL table, and/or an interface width of a memory storing the physical FTL table (e.g., access by byte or access by double word), the write address calculation unit calculates an address of a corresponding entry of the physical FTL table in the memory according to an index of the entry of the logical FTL table (logical address LBA). And the write address calculation unit further calculates and indicates to the write data concatenation unit the position of the bits to be concatenated.

And the write command processing unit reads partial data of the physical FTL table from the memory according to 0, 1 or 2 byte addresses which are provided by the write address calculation unit and store the data to be spliced. If LBA × N mod8 is 0 and if (LBA +1) × N mod8 is 0, then there is no need to read part of the data of the physical FTL table from the memory. If LBA N mod8 is 0, the byte address storing the data to be spliced is (LBA N + N)/8 (rounded down), where the bits used for splicing are its last 8- (LBA N + N) mod8 bits (i.e., 8-Nmod 8 bits). If LBA N mod8 is not 0 and (LBA N + N) mod8 is 0, then the byte address where the data to be spliced is stored is LBA N/8 (rounded down), where the bit for splicing is its first LBA N mod8 bits. If LBA × Nmod 8 is not 0, and LBA × N + N mod8 is also not 0, the byte addresses storing the data to be spliced are (LBA × N)/8 (rounded down) and (LBA × N + N)/8 (rounded down) (total 2 bytes), where the bits for splicing of the first 1 bytes are the previous (LBA × N) mod8 bits, and the bits for splicing of the last 1 byte are the last 8- (LBA × N + N) mod8 bits. Due to the limitation of the memory interface, the write command processing unit reads out the complete byte where the data to be spliced is located from the memory. Alternatively, the write address calculation unit indicates a byte address of 1 or 2 bytes storing the data to be spliced to the write command processing unit.

The write command processing unit includes a read address generating unit and a write address generating unit. The read address generating unit is used for generating a byte address of 1 or 2 bytes storing data to be spliced so as to read the 1 or 2 bytes from the memory. The read address generating unit supplies the read address to the read address transmitting unit. The read address sending unit sends a read address to the bus through the main device interface according to the bus protocol. For example, the bus is an AXI bus, the read address transmitting unit issues a read address on a read address channel of the AXI bus, and the slave device on the bus as a receiving side is, for example, a memory controller (see also fig. 3).

After the bits to be spliced are obtained from the memory and spliced with the entries (N bits) of the physical FTL table provided by the write data cache, the write address generation unit generates a write address to write the spliced data into the memory.

For bits to be spliced read out of the memory, the memory controller supplies bytes read out of the memory accommodating the bits to be spliced to a read data receiving unit (e.g., a read data channel through an AXI bus) through the bus. The write data selecting unit selects the bits to be spliced from the bytes containing the bits to be spliced provided by the read data receiving unit and provides the selected bits to the write data splicing unit. Optionally, the write address calculation unit provides the location of the data to be stitched to the write data selection unit.

The write data splicing unit obtains an entry (N bits) of the physical FTL table to be updated (the index of which is the logical address LBA) and optionally bits to be spliced from the write data cache, forms complete N/8 (round-down), N/8 (round-down) +1 or N/8 (round-down) +2 bytes, and provides the complete N/8 (round-down) +1 bytes to the write data sending unit. Accordingly, the write address generating unit of the write command processing unit generates addresses for these bytes, and supplies them to the write address transmitting unit. According to the bus protocol, the write address transmission unit transmits a write address to the memory controller (see also fig. 3) through the bus, and the write data transmission unit transmits the bytes of data to the memory controller through the bus. For example, the bus is an AXI bus, the write address transmitting unit transmits the write address through a write address channel, and the write data transmitting unit transmits the bytes through a write data channel. Thus, the entries (N bits) containing the physical FTL table to be updated are written to memory with the full N/8 (rounded down), N/8 (rounded down) +1, or N/8 (rounded down) +2 bytes of the bits to be spliced.

So that it appears to the CPU updating the logical FTL table entry that it writes an M-bit entry to the logical FTL table entry indexed by the logical address LBA. And, the CPU can read the M-bit entry from the logical FTL table at the logical address LBA. FTL acceleration units according to embodiments of the present application also handle requests by the CPU to read entries from the logical FTL table.

Continuing with fig. 4, by way of example, a logical FTL table read request from the CPU indicates a logical address LBA, the FTL accelerator is configured with an entry size of the logical FTL table of M bits and an entry size of the physical FTL table of N bits. For FTL table read requests, the address to be accessed by the logical FTL table read request is recorded in the read address cache, and the cached address is, for example, an address (e.g., logical address LBA) for reading an entry of the logical FTL table.

And the read address calculation unit is used for calculating the address of the entry corresponding to the logical address LBA in the memory of the physical FTL table to be read according to the logical address LBA acquired from the read address cache, the configured physical FTL table entry size N and the address of the physical FTL table in the memory. The read address calculation unit calculates an address in the entry memory corresponding to the physical FTL table from the logical address LBA in a similar manner to the write address calculation unit.

For example, if LBA × Nmod 8 is 0, the corresponding entry in the physical FTL table is stored in the N-bit storage space starting from the position of byte address LBA × N/8, and the read address calculation unit calculates that consecutive entries are obtained starting from byte address LBA × N/8

Byte address of a byte. All bits of these bytes will be read.

If LBA N mod8 is not 0, then the corresponding entry in the physical FTL table is stored in an N-bit storage space starting with LBA N Nmod 8 bits after the location of byte address LBA N/8 (rounded down), which occupies N/8 (rounded down) +1 or N/8 (rounded down) +2 bytes. The read address calculation unit calculates the byte addresses of the consecutive N/8 (rounded down) +1 or N/8 (rounded down) +2 bytes from the byte address LBA N/8. All or some of the bits of these bytes will be read. And the read address calculation unit also determines the number of bytes (N/8 (rounded down), N/8 (rounded down) +1, or N/8 (rounded down) + 2) in the memory that stores the entry of the physical FTL table to be read.

The byte address generated by the read address calculation unit is supplied to the read address transmission unit. The read address transmitting unit transmits a read address to, for example, a memory controller through a bus through a host interface of the FTL accelerator. And the memory controller provides corresponding data to the read data receiving unit of the FTL accelerator through the bus in response to the read address.

The read data selecting unit selects N bits corresponding to the physical FTL table entry to be read from N/8 (rounded down), N/8 (rounded down) +1 or N/8 (rounded down) +2 bytes of data read from the memory provided by the read data receiving unit, and records the N bits in the read data cache. Alternatively, the read address calculation unit indicates to the read data selection unit which bits of the read byte data belong to the entries of the physical FTL table indexed by the logical address LBA.

The read data select unit or read data cache also expands the read N-bit entries of the physical FTL table to M bits, for example, fills in a specified number of bits (e.g., M-N bits) of data (e.g., all 0 s or all 1 s or random data) before or after the read N-bit data to obtain M bits of logical FTL table entries. The logical FTL table entry of the M bits of the read data cache is provided to the CPU as a response to the logical FTL table read request through the slave interface of the FTL accelerator.

Optionally, according to the FTL accelerator of the embodiment of the present application, for an update request received from, for example, a CPU to a logical FTL table entry, in addition to writing an entry to be updated to a physical FTL table to update a corresponding entry therein, a response to a processing result of the update result is provided to the CPU through a slave device interface to meet requirements of, for example, a bus protocol.

Fig. 5A illustrates a flow diagram of FTL accelerator processing a read request to a logical FTL table according to an embodiment of the present application.

A master device, such as a CPU, issues a read request for an entry of a logical FTL table, and the bus forwards the read request to the FTL accelerator as a slave (see also fig. 4). In response to a get FTL table read request (510), the read request indicates the logical address LBA to be accessed as an index to the logical FTL table, and the logical address LBA is recorded in the read address cache. The read address calculation unit calculates an address and a length of a corresponding entry of the physical FTL table according to an index (e.g., a logical address LBA) to the logical FTL table indicated by the read request (515).

For example, if LBA × N mod8 is 0, then the corresponding entry in the physical FTL table is stored in N/8 (round up) bytes beginning at byte address LBA × N/8 (round down), and if N mod8 is not 0, then the last byte storing N/8 (round up) bytes of the entry also includes partial bits of other entries; if LBA × Nmod 8 is not 0 and (N mod 8) - (8-LBA × N mod 8) < ═ 0, then the corresponding entry in the physical FTL table is stored in N/8 (rounded down) +1 bytes starting at byte address LBA × N/8 (rounded down); if LBA × Nmod 8 is not 0 and (N mod 8) - (8-LBA × N mod 8) >0, the corresponding entry in the physical FTL table is stored in N/8 (rounded down) +2 bytes from byte address LBA × N/8 (rounded down).

Optionally, the read address calculation unit further adjusts the calculated address and/or length of the corresponding entry of the physical FTL table according to the bus address of the memory and the starting address of the physical FTL table in the memory.

Based on the address and length obtained by the read address calculation unit, the FTL accelerator accesses the memory through the bus by the slave interface to read out data from the memory (520). The read data selection unit of the FTL accelerator selects an N-bit-sized entry indexed by the logical address LBA in the physical FTL table from the read data (525). An entry of the physical FTL table of N bit size is expanded to an entry size (M bits) of the logical FTL table required for the read request (530), and the data of M bits is stored in the read data cache. And responding to an access request to the logical FTL table entry through the slave device interface with the expanded M-bit data.

Fig. 5B illustrates a flow diagram of FTL accelerator processing a write request to a logical FTL table according to an embodiment of the present application.

A master device, such as a CPU, issues a write request to an entry of the logical FTL table to update the entry of the logical FTL table. In response to the get FTL table write request (550), the write request indicates the logical address LBA to be accessed as an index of the logical FTL table and an entry (M bits) of the logical FTL table to be written. The logical address LBA is recorded in the write address cache. An entry for the logical FTL table of M bits is recorded in the write data cache. The write address calculation unit calculates the address and length of the corresponding entry of the physical FTL table according to the index (e.g., logical address LBA) to the logical FTL table indicated by the write request (555). N bits of the M-bit logical FTL table entries correspond to physical FTL table entries to be updated.

If the entries of the physical FTL table to be updated are not aligned according to the byte boundary (i.e. LBA × N mod8 is not 0, and/or (LBA +1) × Nmod 8 is not 0), 1 byte or 2 bytes of data are read from the memory, and part of bits of the read data are concatenated with N bits of data to be written. The data splicing is completed by performing steps 560 through 570. If the entries of the physical FTL table to be updated are aligned by byte boundary (i.e. LBA N mod8 is 0 and (LBA +1) xnmod8 is 0), then steps 560 to 570 need not be executed.

The write address calculation unit also indicates that 0, 1, or 2 of the calculated write addresses need to be read out. The read address generating unit of the write command processing unit reads out data from the memory through the host interface according to the write address to be read (560). The write data selection unit selects valid data (bits to be spliced) from the read data (565). For example, if LBA × N mod8 is 0 and N mod8 is not 0, the byte address of the read 1-byte data is (LBA +1) × N/8, and 8- (LBA +1) × N mod8 bits at the end thereof are data to be concatenated; if LBA × N mod8 is not 0, the first LBA × N mod8 bits of 1 byte data read from byte address LBA × N/8 are data to be spliced, and/or the 8- (LBA +1) × N mod8 bits of the end of 1 byte data read from byte address (LBA +1) × N/8 are data to be spliced.

If steps 560 to 570 are performed, the write data concatenation unit concatenates the bits to be concatenated provided by the write data selection unit with the N-bit data of the entry of the physical FTL table to be updated in the write data cache (570), so as to obtain N/8 (round-down) +1 or N/8 (round-down) + 2-byte data. If steps 560 through 570 need not be performed, the write data concatenation unit obtains the N bits of data (N/8 (rounded down) bytes in size) to be written to the entry of the physical FTL table directly from the write data cache. And writing the data of N/8 (rounding down), N/8 (rounding down) +1 byte or N/8 (rounding down) +2 bytes provided by the write data splicing unit into the memory (580) through the host interface.

Fig. 6A and 6B are schematic diagrams illustrating reading out corresponding entries of logical FTLs from a physical FTL table.

In the examples of fig. 6A to 6D, the entry size of the logical FTL table is 64 bits, and the entry size of the physical FTL table is 33 bits.

Referring to fig. 6A, the entry of the logical FTL table indexed by logical address 0 is to be read out. Fig. 6A shows the first 16 bytes (denoted as byte 0 to byte 15) of the space where the physical FTL table is stored. The entry of the physical FTL table indexed by logical address 0 is denoted as PBA (0), which is located in 33 bits from byte 0, occupying the complete 1 st bit of byte 0 to byte 3 and byte 4. According to an embodiment of the present application, in order to read out entry PBA (0), it is necessary to read out complete bytes 0 to 4, 5 bytes in total, from the memory, and select all data of bytes 0 to 3 and the 1 st bit of byte 4 to obtain PBA (0). And filling PBA (0) of 33 bits with, for example, 31 bits 0 to obtain a logical FTL table entry (denoted as LBA (0)) to be read.

Referring to fig. 6B, the entry of the logical FTL table indexed by logical address 1 is to be read out. The entry of the physical FTL table indexed by logical address 1 is denoted as PBA (1), which is located in 33 bits from the 2 nd bit of byte 4, occupies the 2 nd to 8 th bits of byte 4, the complete bytes 5 to 7, and the first 2 bits of byte 7. According to an embodiment of the application, in order to read out entry PBA (1), it is necessary to read out complete byte 4 to

byte

8, 5 bytes in total, from the memory, and select bits 2 to 8 of byte 4, all data of byte 5 to byte 7, and the first 2 bits of byte 8 to obtain PBA (1). And filling PBA (1) of 33 bits with, for example, 31 bits of 0 to obtain a logical FTL table entry (denoted as LBA (1)) to be read.

Fig. 6C and 6D are schematic diagrams illustrating writing of corresponding entries of a logical FTL table to a physical FTL table.

Referring to fig. 6C, the entry of the logical FTL table indexed by logical address 0 (denoted as LBA (0)) is to be updated. A designated N bits are selected from entry LBA (0), which is PBA (0). The entry of the physical FTL table indexed by logical address 0 is denoted as PBA (0), which is located in 33 bits from byte 0 in the physical FTL table, occupying the complete 1 st bit of byte 0 to byte 3 and byte 4.

According to an embodiment of the application, byte 4 needs to be read out of memory in order to write the entry PBA (0). After PBA (0) is updated, bit 1 of byte 4 is the last bit of PBA (0) that is updated, and bits 2 to 8 of byte 4 belong to PBA (1) and should not be updated. Thus, N bits of LBA (0) are concatenated with 2 nd to 8 th bits of byte 4 read out as the contents of byte 0 to byte 4, and the contents are written into byte 0 to byte 4 of the physical FTL table to complete the update of LBA (0) and PBA (0).

Referring to fig. 6D, the entry of the logical FTL table indexed by logical address 1 (denoted as LBA (1)) is to be updated. A designated N bits, PBA (1), are selected from entry LBA (1). The entry of the physical FTL table indexed by logical address 1 is denoted as PBA (1), which is located in 33 bits from the 2 nd bit of byte 4 in the physical FTL table, occupying the 2 nd to 8 th bits of byte 4, the complete bytes 5 to 7 and the first 2 bits of byte 7.

According to an embodiment of the application,

bytes

4 and 8 need to be read out of memory in order to write the entry PBA (1). After PBA (1) is updated, bit 1 of byte 4 is the last bit of PBA (0) (which should not be updated), and bits 2 through 8 of byte 4 are the first 7 bits of PBA (1). After PBA (1) is updated, the first 2 bits of byte 8 are the last 2 bits of PBA (1). While the 3 rd to 8 th bits of byte 8 belong to PBA (2) and should not be updated.

Thus, N bits of LBA (1) are concatenated with the first 1 bits of byte 4 read out and the last 6 bits of byte 8 read out as the contents of byte 4 to byte 8, and the contents are written into byte 4 to byte 8 of the physical FTL table to complete the update of LBA (1) and PBA (1).

The control components include, for example, a CPU, a media interface controller (NFI), an FTL accelerator, and a memory controller. The CPU, media interface controller (NFI), FTL accelerator, and/or memory controller are coupled, for example, by a bus. The CPU is also directly coupled to the FTL accelerator. The CPU determines whether to send an access request to the FTL accelerator or the bus according to the address space to be accessed. For example, the FTL accelerator is allocated 0-8GB of address space, while devices coupled to the bus are allocated 8-32 GB of address space, while the NFI is allocated, for example, 8GB of starting 1MB of address space, and the memory controller is allocated 16-32 GB of address space. From the CPU's perspective, the 0-8GB address space occupied by the FTL accelerator accommodates the logical FTL table. While the physical FTL tables are accommodated in the 16GB-32GB address space occupied by the memory controller. Requests for CPU access to 0-8GB address space are sent directly to the FTL accelerator for processing, while requests for CPU access to 16-32 GB address space are forwarded by the bus to the memory controller for processing.

According to an embodiment of the present application, the FTL accelerator includes a host device interface. The FTL accelerator is coupled to the bus through a host interface. So that the CPU controlling the component has direct access to the FTL accelerator. And the FTL accelerator may access one or more devices (e.g., memory controllers) of the control component as a master through the master interface.

Thus, the CPU accesses an entry (index is LBA) of the logical FTL table by issuing an access request to the FTL accelerator, where the accessed address is LBA × 8 and the length is 8 bytes. The FTL accelerator determines the storage location of the entry of the corresponding physical FTL table in the physical FTL table according to the address (LBA × 8) indicated in the received access, and issues 1 or more memory access requests to the memory controller through the bus through its master interface to access the entry of the physical FTL table in the DRAM.

Although the present application has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the application, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the application.

Many modifications and other embodiments of the application set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the application is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. An FTL accelerator is characterized by comprising a read address calculation unit, a read data selection unit, a read address sending unit and a read data receiving unit;

the read address calculation unit calculates the address of an entry of a physical FTL table corresponding to an entry of a logical FTL table to be accessed according to the index (L) of the entry of the logical FTL table to be read;

the read address calculation unit further indicates to the read data selection unit a portion of the data read out from the memory that belongs to an entry of the physical FTL table to be accessed;

the read data selection unit acquires a part belonging to the entry of the physical FTL table to be accessed from the data read out from the memory indicated by the read address calculation unit, and expands the entry of the physical FTL table to be accessed to obtain the entry of the logical FTL table to be accessed.

2. An FTL accelerator according to claim 1, further comprising: a read address cache unit and a read data cache unit;

the read address cache unit stores an index (L) of an entry of a logical FTL table to be accessed;

the read data cache unit stores the entry of the logic FTL table to be accessed;

the read address calculation unit is coupled with the read address cache unit and acquires an index (L) from the read address cache unit;

the read data selection unit stores a part of the data read from the memory, which belongs to an entry of a physical FTL table to be accessed, in a read data cache;

the entry of the physical FTL table to be accessed stored in the read data cache is expanded to the size of the entry of the logical FTL table to be accessed to obtain the entry of the logical FTL table to be accessed.

3. An FTL accelerator according to claim 1 or 2, wherein

The address of the entry of the physical FTL table corresponding to the entry of the logic FTL table to be accessed, which is calculated by the read address calculation unit according to the index (L), is in the storage space of the physical FTL table and is in a byte address L

4. An FTL accelerator according to claim 1, further comprising: the device comprises a write address calculation unit, a write command processing unit and a write data splicing unit;

the write address calculation unit calculates the address of an entry of a physical FTL table corresponding to the entry of the logical FTL table to be updated according to the index (L) of the entry of the logical FTL table to be updated;

the data writing splicing unit acquires corresponding N-bit physical FTL table entries from the to-be-updated logic FTL table entries;

the write command processing unit is coupled with the write address calculation unit, and writes the entries of the physical FTL table with N bits acquired by the write data splicing unit into the addresses of the entries of the physical FTL table corresponding to the entries of the logical FTL table to be updated, which are provided by the write address calculation unit.

5. An FTL accelerator according to claim 4,

the write address calculation unit further calculates one or two addresses to be read from the physical FTL table according to an index (L) of an entry of the logical FTL table to be updated, and supplies the one or two addresses to be read from the physical FTL table to the write command processing unit;

the write command processing unit reads data from a memory according to the one or two addresses to be read out from the physical FTL table;

the write address calculation unit further indicates to the write data selection unit a portion of the data read out from the memory that does not belong to an entry of the physical FTL table to be updated;

the write data selecting unit acquires a part which does not belong to the entry of the physical FTL table to be updated from the data read out from the memory according to the instruction of the write address calculating unit, and provides the part which does not belong to the entry of the physical FTL table to be updated and is acquired from the data read out from the memory to the write data splicing unit;

the write data splicing unit splices the corresponding N-bit physical FTL table entries acquired from the logical FTL table entries to be updated with the part of the entries which are not included in the physical FTL table to be updated and acquired from the data read out from the memory and provided by the write data selection unit;

and the writing command processing unit is used for writing the N-bit entries of the physical FTL table provided by the writing data splicing unit and the part which is acquired from the data read out from the memory and does not belong to the entries of the physical FTL table to be updated into the addresses of the entries of the physical FTL table corresponding to the entries of the logical FTL table to be updated, wherein the addresses are provided by the writing address calculation unit.

6. An FTL accelerator according to claim 4 or 5, further comprising a write address transmitting unit;

the write command processing unit comprises a read address generating unit and a write address generating unit;

the read address generating unit reads data from a memory through the read address sending unit by using the one or two addresses to be read from the physical FTL table;

the read data receiving unit receives data read from a memory;

the write address generating unit sends the address of the entry of the physical FTL table corresponding to the entry of the logical FTL table to be updated, which is provided by the write address calculating unit, through the write address sending unit.

7. An FTL accelerator according to claim 1, further comprising:

a master device interface for coupling to a bus;

the read address sending unit sends the read address to a bus through a main equipment interface;

the read data receiving unit acquires the read data from the bus through the main equipment interface;

the write address sending unit sends a write address to a bus through the main equipment interface;

the write data transmitting unit transmits data to be written to the bus through the host interface.

8. An FTL accelerator according to claim 7, further comprising:

a slave device interface for coupling to a bus;

the read address cache stores an index (L) of an entry of a logical FTL table to be read, which is acquired through a device interface;

the read data cache stores entries of a logical FTL table to be read to be transmitted through the slave device interface;

the write address cache stores an index (L) of an entry of the logical FTL table to be written, which is acquired through the device interface;

the write data cache stores entries of the logical FTL table to be written, which are obtained through the slave device interface.

9. A control component, comprising: the system comprises a first master device, an FTL accelerator, a memory controller and a bus;

the FTL accelerator couples to the bus through a host device interface;

the memory controller is coupled with the memory through a slave device interface and the bus;

the FTL accelerator as described above is an FTL accelerator according to one of claims 1-8.

10. The control component of claim 9, wherein

The first master device providing to the FTL accelerator an index (L) of an entry of a logical FTL table to be read;

the FTL accelerator accesses an entry of a physical FTL table in the memory corresponding to an index (L) through a master interface in response to the index (L) provided by the first master.