JP6689325B2 - Memory device control method - Google Patents

Description

  The present embodiment relates to a method of controlling a memory device.

  The solid state drive (SSD) includes, for example, a non-volatile memory such as a NAND flash memory. The NAND flash memory includes a plurality of blocks (physical blocks). The plurality of blocks include a plurality of memory cells arranged at the intersections of the word lines and the bit lines.

JP, 2012-141944, A

  The present embodiment provides a method of controlling a memory device that extends the life of a non-volatile memory.

This embodiment, Ri by the processor, the first memory device including a memory, the second memory and writing of data with respect to, for storing a portion of the valid data stored in the memory device including a plurality of areas And a method of controlling leads .

According to the method of the present embodiment, the processor receives, from the memory device, first information indicating valid data in the garbage collection target area selected from the plurality of areas by the memory device , and the processor receives the first information . Writing the data excluding the deletion target data indicated by the deletion instruction generated by the processor from the valid data indicated by the information No. 1 to the second memory, and causing the processor to write the valid data indicated by the first information Of the second information indicating the data to be deleted of the first memory and the processor causes the data indicated by the second information to be deleted by the garbage collection for the garbage collection target area of the first memory . Transmitting the information to the memory device.

The block diagram which shows an example of a structure of the information processing system which concerns on 1st Embodiment. The flowchart which shows an example of a process of the information processing system which concerns on 1st Embodiment. The block diagram which shows an example of a structure of the information processing system which concerns on 2nd Embodiment. The flowchart which shows an example of the 1st cache control which concerns on 2nd Embodiment. The flowchart which shows an example of the 2nd cache control which concerns on 2nd Embodiment. 9 is a flowchart showing an example of third cache control according to the second embodiment. 9 is a flowchart showing an example of fourth cache control according to the second embodiment. The block diagram which shows an example of a detailed structure of the information processing system which concerns on 3rd Embodiment. The perspective view which shows an example of the storage system which concerns on 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the substantially same or substantially the same function and constituent element will be denoted by the same reference numeral and will be described as necessary.

  In each of the following embodiments, in the nonvolatile memory and the nonvolatile cache memory, data is collectively erased for each erase unit area. The erase unit area includes a plurality of write unit areas and a plurality of read unit areas.

  In the present embodiment, a case where a NAND flash memory is used as the nonvolatile memory and the nonvolatile cache memory will be described. However, the non-volatile memory and the non-volatile cache memory may be other types of memory that are not the NAND flash memory as long as they satisfy the relationship of the erase unit area, the write unit area, and the read unit area.

  When the non-volatile memory and the non-volatile cache memory are NAND flash memories, the erase unit area corresponds to a block. The writing unit area and the reading unit area correspond to a page.

  In the present embodiment, for example, the erasing unit area may be managed in another unit in which data can be collectively erased, such as two or more blocks.

  In this embodiment, access means both writing data to a storage device and reading data from the storage device.

[First Embodiment]
The present embodiment describes transmission and reception of data and information between an information processing device and a memory device.

  In the present embodiment, a case where a logical address (for example, Logical Block Addressing) is used as the data identification information will be described as an example, but the data may be identified by other information.

  FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to this embodiment.

  The information processing system 35 includes the information processing device 17 and the SSD 5, which is an example of a memory device. The information processing device 17 may be a host device compatible with SSD5.

  The SSD 5 may be built in the information processing device 17, or the information processing device 17 and the SSD 5 may be connected to each other via a network so that data can be transmitted and received. Instead of the SSD 5, another non-volatile storage device such as a hard disk drive (HDD) may be used as the memory device.

  The information processing device 17 includes a cache control unit 9, a memory 3 that stores management information 61 to 64, and a nonvolatile cache memory 4. However, some or all of the cache control unit 9, the management information 61 to 64, the memory 3, and the nonvolatile cache memory 4 may be provided outside the information processing device 17.

  The memory 3 stores various control information such as management information (list) 61 to 64 and address conversion information 7. The memory 3 may be a volatile memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), or may be a non-volatile memory. The memory 3 may be included in the non-volatile cache memory 4.

  The management information 61 to 64 is metadata relating to the data written in the block groups BG1 to BG4 described in the second embodiment described later, respectively. For example, the management information 61 to 64 includes information indicating the usage status of each data by the processor 2. For example, the management information 61 to 64 includes identification information of each data, deletion information indicating whether the data is a deletion target, valid / invalid information indicating whether the data is valid data, and an erasing condition for erasing a block. It includes cache judgment information for judging whether or not the condition is satisfied.

  Here, the delete information is, for example, information indicating that a delete command for data has occurred, and as a more specific example, a delete command for data from an application program executed by the processor 2 or an operating system (OS). Information indicating that has been accepted. In the present embodiment, the deletion information includes, for example, information in which the identification information of each block and the logical address indicating the deletion target data written in each block are associated with each other.

  The valid / invalid information is, for example, information indicating that the latest data is valid data and non-latest data is invalid data when the same data is written in a plurality of positions. In other words, for example, the valid data is the updated data when the data written in the nonvolatile cache memory 4 is updated. For example, the invalid data is data before updating when updating occurs. In the present embodiment, the valid / invalid information includes, for example, information in which identification information of each block is associated with a logical address indicating valid data or invalid data written in each block.

  The cache determination information is, for example, information including at least one of write information and read information for each data, or at least one of write information and read information for each block.

  The write information includes, for example, at least one of a write time, a write count, a write frequency, and a write order.

  The read information includes, for example, at least one of a read time, a read count, a read frequency, and a read order.

  The address conversion information 7 associates, for example, a logical address of data with a physical address (for example, Physical Block Addressing) of the nonvolatile cache memory 4 corresponding to the logical address. The address conversion information 7 is managed in a table format, for example.

  The cache control unit 9 executes cache control for the nonvolatile cache memory 4 that can be accessed faster than the SSD 5. For example, the cache control unit 9 manages data and a logical address and a physical address indicating the data by a write-through method or a write-back method.

  The write-through method is a method of storing data in the nonvolatile cache memory 4 and also storing data in the SSD 5.

  In the write-back method, the data stored in the nonvolatile cache memory 4 is not stored in the SSD 5 each time, but the data is temporarily stored in the nonvolatile cache memory 4 and the data evicted from the nonvolatile cache memory 4 is This is a method of storing in SSD5.

  In this embodiment, the cache control unit 9 includes a transmission unit 18, a reception unit 19, a writing unit 20, and a transmission unit 21. Some or all of the cache memory 9 may be implemented by software or hardware.

  The transmitter 18 sends the write data for the SSD 5 and the address of the write data to the SSD 5. In the present embodiment, the address sent from the transmission unit 18 to the SSD 5 is, for example, a logical address.

  The receiving unit 19 receives, from the SSD 5, block information including a logical address indicating valid data written in the garbage collection target block.

  In the present embodiment, the block information may include information in which the identification information of each block in the SSD 5 and the identification information of the data written in each block are associated with each other.

  Based on the block information received from the SSD 5 and the management information 61 to 64, the writing unit 20 writes a part or all of the valid data indicated by the logical address included in the block information in the nonvolatile memory 24 of the SSD 5. Not write to other memory (transcribe). The other memory may be, for example, the nonvolatile cache memory 4 or the like.

  For example, the writing unit 20 excludes the logical address indicating the deletion target (deletion candidate) data when the deletion instruction is received, from the logical address indicating the valid data included in the block information. As a result, it becomes possible to select the valid data written in the garbage collection target block and not the deletion target. The writing unit 20 writes the selected data in another memory.

  The transmission unit 21 generates deletion information including a logical address indicating the deletion target data and sends the deletion information to the SSD 5. For example, the deletion information may include, among the logical addresses indicating the valid data included in the block information, the logical address indicating the deletion target data that has not been written in another memory by the writing unit 20. In addition, instead of the deletion information, the maintenance information including the logical address to be maintained may be sent from the transmission unit 21 to the SSD 5.

  The SSD 5 includes a processor 22, a memory 23, and a non-volatile memory 24.

  The memory 23 stores various control information such as address conversion information 32, valid / invalid information 33, and delete information 34. The memory 23 may be a volatile memory such as a DRAM or SRAM, or a non-volatile memory. The memory 23 may be included in the non-volatile memory 24.

  The processor 22 executes the program stored in the memory in the processor 22, the program stored in the memory 23, or the program stored in the non-volatile memory 24, thereby the address conversion unit 25 and the writing unit. 26, a valid / invalid generation unit 27, a selection unit 28, a transmission unit 29, a reception unit 30, and a garbage collection unit 31.

  In the present embodiment, a program for causing the processor 22 to function as the address conversion unit 25, the writing unit 26, the valid / invalid generation unit 27, the selection unit 28, the transmission unit 29, the reception unit 30, and the garbage collection unit 31 is, for example, It may be OS, middleware, or firmware. In the present embodiment, some or all of the address conversion unit 25, the writing unit 26, the valid / invalid generation unit 27, the selection unit 28, the transmission unit 29, the reception unit 30, and the garbage collection unit 31 are implemented by hardware. May be done.

  When receiving the write data and the logical address of the write data from the cache control unit 9, the address conversion unit 25 indicates the logical address of the write data and the physical address indicating the position of the nonvolatile memory 24 in which the write data is stored. Information relating to the address is generated, and this information is registered in the address conversion information 32.

  In this embodiment, the address conversion unit 25 is realized by the processor 22. However, the address conversion unit 25 may be configured differently from the processor 22.

  Further, the address conversion unit 25 performs the address conversion based on, for example, the table-type address conversion information 32, but instead of this, the address conversion may be performed by a key-value type search. For example, by using a logical address as a key and a physical address as a value, address conversion by a key-value type search can be realized.

  The writing unit 26 writes the write data at the position indicated by the physical address obtained by the address conversion unit 25.

  The valid / invalid generation unit 27 generates valid / invalid information 33 indicating whether each data written in the nonvolatile memory 24 is valid data or invalid data based on the address conversion information 32, for example. Then, the valid / invalid generation unit 27 stores the valid / invalid information 33 in the memory 23.

  The selection unit 28 selects a garbage collection target block.

  For example, the selection unit 28 may select, among the blocks of the non-volatile memory 24, the block with the oldest writing time as the block for garbage collection.

  For example, the selection unit 28 may randomly select a garbage collection target block from the blocks of the nonvolatile memory 24.

  For example, the selection unit 28 selects a block having the largest number of invalid data or a block having a larger number of invalid data than a predetermined value as the garbage collection target block based on the valid / invalid information 33. Good.

  For example, the selection unit 28 determines, based on the valid / invalid information 33 and the deletion information 34, a block in which the number of invalid data and deletion target data is the largest, or the number of invalid data and deletion target data is more than a predetermined value. A large number of blocks may be selected as a target block for garbage collection.

  The transmitting unit 29 generates block information in which a logical address indicating invalid data that is invalidated by the valid / invalid information 33 is deleted from a logical address indicating data written in a garbage collection target block. In other words, the block information includes the information in which the identification information of the garbage collection target block and the logical address indicating the valid data written in the block are associated with each other. Then, the transmitter 29 sends the block information to the cache memory controller 9.

  The receiving unit 30 receives the deletion information from the cache memory control unit 9, and stores the deletion information 34 in the non-volatile memory 24.

  The garbage collection unit 31 excludes invalid data and deletion target data from the data written in the garbage collection target block based on the valid / invalid information 33 and the deletion information 34 stored in the non-volatile memory 24. Then, garbage collection is executed only for data that is valid and is not deleted.

  FIG. 2 is a flowchart showing an example of processing of the information processing apparatus according to this embodiment.

  In step S201, the transmitter 18 sends the write data and the logical address to the SSD 5.

  In step S202, the address conversion unit 25 receives the write data and the logical address, and registers, in the address conversion information 32, information that associates the logical address of the write data with the physical address.

  In step S <b> 203, the writing unit 26 writes the write data at the position indicated by the physical address of the non-volatile memory 24.

  In step S <b> 204, the valid / invalid generation unit 27 generates valid / invalid information 33 indicating whether each data written in the nonvolatile memory 24 is valid data or invalid data, and stores the valid / invalid information 33 in the memory 23. Store.

  In step S205, the selection unit 28 selects a garbage collection target block.

  In step S206, the transmission unit 29 generates block information in which a logical address indicating invalid data invalidated by the valid / invalid information 33 is deleted from the logical address indicating data written in the garbage collection target block. Then, the block information is transmitted to the cache control unit 9.

  In step S207, the receiving unit 19 receives the block information from the SSD 5.

  In step S208, the writing unit 20 writes a part or all of the data indicated by the logical address included in the block information into the nonvolatile memory of the SSD 5 based on the block information received from the SSD 5 and the management information 61 to 64. Write to other memory than 24.

  For example, the writing unit 20 excludes, from the logical addresses included in the block information, the logical address indicating the deletion target data for which the deletion instruction has been received, and stores the data indicated by the maintenance target logical address in another memory. Write.

  In step S209, the transmission unit 21 sends the deletion information including the logical address to be deleted to the SSD 5.

  In step S 210, the receiving unit 30 receives the deletion information from the cache control unit 9 and stores the deletion information 34 in the memory 23.

  In step S211, the garbage collection unit 31 excludes the invalid data and the deletion target data from the data written in the garbage collection target block based on the valid / invalid information 33 and the deletion information 34, and the data is valid. Perform garbage collection only on the data that is not deleted.

  In the present embodiment described above, the cache control unit 9 can acquire the information of the data written in the block of the nonvolatile memory 24 from the SSD 5. As a result, the cache control unit 9 can recognize the data write state in the block of the nonvolatile memory 24. For example, in this embodiment, it is possible to recognize whether the data written in the block of the nonvolatile memory 24 is valid data, invalid data, or deletion target data.

  In the present embodiment, the SSD 5 includes valid / invalid information 33 for identifying whether the data is valid data or invalid data, and deletion information 34 for identifying whether the data is a deletion target. As a result, when garbage collection is executed in the SSD 5, it is possible to determine whether or not to erase the data written in the garbage collection target block, and it is possible to prevent writing of unnecessary data. The life of the non-volatile memory 24 can be extended.

  In the present embodiment, the cache control unit 9 prevents the deletion target data from being transferred from the non-volatile memory 24 to another memory among the valid data indicated by the logical address included in the block information received from the SSD 5. You can In addition, in the present embodiment, the SSD 5 can delete from the SSD 5 data that has not been transferred from the cache control unit 9 to another memory (for example, data that is invalid data, valid data, but is also deletion target data). it can.

  In the present embodiment described above, the block information regarding the block to be erased is sent from the SSD 5 to the information processing device 17. However, this block information may include, for example, information in which each block of the nonvolatile memory 24 is associated with identification information of data written in each block. By receiving this relation information from the SSD 5, the information processing device 17 can recognize the storage relation between the block and the data in the SSD 5.

[Second Embodiment]
In this embodiment, a cache memory device including the nonvolatile cache memory 4 will be described.

  FIG. 3 is a block diagram showing an example of the configuration of the information processing system 35 according to this embodiment.

  The information processing device 17 includes a processor 2, a memory 3, and a nonvolatile cache memory 4.

  The nonvolatile cache memory 4 includes block groups BG1 to BG4. The nonvolatile cache memory 4 can be accessed faster than the SSD 5.

  The block group (first group) BG1 includes blocks (first erase area) B1,1 to B1, K. The block group BG1 stores data accessed by the processor 2 (data used by the processor 2).

  In the present embodiment, when the block group BG1 satisfies the erase condition (first erase condition), the blocks B1,1 in the block group BG1 are based on the first-in first-out (FIFO) method. The blocks to be erased (discarded or ejected) (first erased area) are selected from B1 to K1.

  For example, when the data amount of each block B1,1 to B1, K of the block group BG1 exceeds a predetermined value, the erase condition is satisfied. Further, for example, the erasing condition may be satisfied when the number of pages written in each block B1,1 to B1, K of the block group BG1 exceeds a predetermined number.

  The data written in the block to be erased selected from the blocks B1,1 to B1, K by the FIFO is the first low usage state (for example, the first number of times set or less than the first frequency). In case of being accessed), it is written in the block group BG2. On the other hand, the data written in the block to be erased selected from the blocks B1,1 to B1, K has the first high usage state (for example, the first number of times or the first frequency or more). In case of being accessed), it is written in the block group BG3. Then, the data written in the erase target block selected from the blocks B1,1 to B1, K is erased (discarded or ejected) in block units.

  The block group (second group) BG2 includes blocks (second erase area) B2,1 to B2, L. The block group BG2 stores the data in the first low usage state among the data written in the erase target block selected from the block group BG1.

  In the present embodiment, when the block group BG2 satisfies the erase condition (third erase condition), the blocks to be erased (third erase) from the blocks B2,1 to B2, L in the block group BG2 based on the FIFO. Target area) is selected.

  The data written in the block to be erased selected from the blocks B2,1 to B2, L by the FIFO is the third low usage state (for example, the third number of times or less than the set third frequency). If it is being accessed), it will be deleted. On the other hand, the data written in the block to be erased selected from the blocks B2,1 to B2, L has the third high usage state (for example, the third number of times or the third frequency or more). In case of being accessed), it is written in the block group BG3. Then, the data written in the erase target block selected from the blocks B2,1 to B2, L is erased in block units.

  The block group (third group) BG3 includes blocks (third erase area) B3,1 to B3, M. The block group BG3 stores the data in the first high usage state among the data written in the erase target block selected from the block group BG1. Further, the block group BG3 stores the data in the third high usage state among the data written in the erase target block selected from the block group BG2.

  In the present embodiment, when the block group BG3 satisfies the erasing condition (second erasing condition), the blocks to be erased (second erasing) from the blocks B3,1 to B3, M in the block group BG3 based on the FIFO. Target area) is selected.

  The data written in the block to be erased selected by the FIFO from the blocks B3,1 to B3, M has a second low usage state (for example, the second number of times or less than the second frequency which is set). If it is being accessed), it is written to the block group BG4. On the other hand, the data written in the erasing target block selected from the blocks B3,1 to B3, M has the second high usage state (for example, the second number of times or the second frequency or more). If it is being accessed), it is rewritten to another block in the block group BG3. Then, the data written in the erase target block selected from the blocks B3,1 to B3, M is erased in block units.

  The block group (fourth group) BG4 includes blocks (fourth erase area) B4,1 to B4, N. The block group BG4 stores the data in the second low usage state out of the data written in the erase target block selected from the block group BG3.

  In the present embodiment, when the block group BG4 satisfies the erase condition (fourth erase condition), the blocks to be erased (fourth erase) from the blocks B4,1 to B4, N in the block group BG4 based on the FIFO. Target area) is selected.

  The data written in the erase target block selected by the FIFO from the blocks B4,1 to B4, N is erased.

  In the present embodiment, the FIFO is used as a method of selecting a block to be erased from each block group BG1 to BG4. By selecting the block to be erased based on the FIFO, the blocks having the oldest writing time and writing order are erased from each block group BG1 to BG4. However, the erase target block may be selected at random, may be selected based on LRU (Least Recently Used), or may be selected based on LFU (Least Frequently Used). For example, a block having the largest number of invalid data or a block having a larger number of invalid data than a predetermined value may be selected as the erase target block based on the management information 61 to 64. For example, the management information 61 to 64 includes data identification information, information indicating whether the data is to be deleted, and data usage status information. Based on the management information 61 to 64, a block having the largest number of invalid data and deletion target data or a block having a larger number of invalid data and deletion target data than a predetermined value is selected as an erasing target block. Good.

  In the present embodiment, the cache control unit 9 writes identification information of cached data (for example, a logical address provided by the host) and the data based on the management information 61 to 64 and the address conversion information 7. It is possible to recognize the current position and the usage status of the data. For example, the cache control unit 9 can select the data cached in each of the block groups BG1 to BG4 and the block erased by the FIFO based on the management information 61 to 64 and the address conversion information 7. .

  The processor 2 executes a program stored in the memory in the processor 2, a program stored in the memory 3, a program stored in the non-volatile cache memory 4, or a program stored in the SSD 5. This functions as the address conversion unit 8 and the cache control unit 9.

  In the present embodiment, the program for causing the processor 2 to function as the address conversion unit 8 and the cache control unit 9 may be, for example, an OS, middleware, or firmware. In the present embodiment, part or all of the address conversion unit 8 or part or all of the cache control unit 9 may be implemented by hardware.

  The address conversion unit 8 generates information that associates the logical address of the write data with the physical address indicating the position of the nonvolatile cache memory 4 in which the write data is stored, and registers this information in the address conversion information 7. To do.

  Further, when receiving the logical address of the read data from the processor 2, the address translation unit 8 translates the logical address into a physical address based on the address translation information 7.

  The cache control unit 9 includes a generation unit 10, control units 11 to 14, and changing units 15 and 16.

  The generation unit 10 generates management information 61 to 64 corresponding to the block groups BG1 to BG4 of the nonvolatile cache memory 4, and writes the management information 61 to 64 in the memory 3.

  The control units 11 to 14 control writing of data and erasing of blocks in the block groups BG1 to BG4, respectively.

  The control unit 11 includes a writing unit 111, a determination unit 112, a selection unit 113, a determination unit 114, and an erasing unit 115.

  The writing unit (first writing unit) 111 writes the data accessed by the processor 2 to the block group BG1.

  The determination unit (first determination unit) 112 determines whether the block group BG1 satisfies the erase condition (first erase condition).

  The selection unit (first selection unit) 113 selects an erase target block (first erase target area) from the block group BG1 when the block group BG1 satisfies the erase condition.

  The determination unit (second determination unit) 114 determines, based on the management information 61, whether each data written in the erase target block is the first high usage state, the first low usage state, or the deletion target. .

  The erasing unit (first erasing unit) 115 writes each data written in the erasing target block in the block group BG2 or the block group BG3, or when the data is a deletion target and may be discarded. , Erase the block to be erased.

  The control unit 12 includes a writing unit 121, a determination unit 122, a selection unit 123, a determination unit 124, and an erasing unit 125.

  When the determination unit 114 determines that the data written in the erase target block of the block group BG1 is in the first low usage state and is not the deletion target, the writing unit (second writing unit) 121 concerned data Is written to the block group BG2.

  The determination unit (fifth determination unit) 122 determines whether or not the block group BG2 satisfies the erase condition (third erase condition).

  The selection unit (third selection unit) 123 selects an erase target block (third erase target area) from the block group BG2 when the block group BG2 satisfies the erase condition.

  The determination unit 124 determines, based on the management information 62, whether each piece of data written in the erase target block is the third high usage state, the third low usage state, or the deletion target.

  The erasing unit (second erasing unit) 125 writes to the erasing target block when the third high usage state data written in the erasing target block and not the erasing target data is written to the block group BG3. Delete the stored data.

  The control unit 13 includes a writing unit 131, a determination unit 132, a selection unit 133, a determination unit 134, a writing unit 135, an erasing unit 136, and a writing unit 137.

  When the determination unit 114 determines that the data written in the erase target block of the block group BG1 is in the first high usage state and is not the deletion target, the writing unit (third writing unit) 131 concerned data Is written to the block group BG3.

  The writing unit (sixth writing unit) 137 writes the data written in the block group BG2 to the block group BG3 when the data is in the third high usage state and is not the deletion target. For example, the writing unit 137 may write the access target data of the block group BG2 to the block group BG3 when the data written in the block group BG2 is the access target of the processor 2.

  The determination unit (third determination unit) 132 determines whether or not the block group BG3 satisfies the erase condition (second erase condition).

  The selection unit (second selection unit) 133 selects an erase target block (second erase target area) from the block group BG3 when the block group BG3 satisfies the erase condition.

  The determination unit (fourth determination unit) 134 determines, based on the management information 63, whether each data written in the erase target block is the second high usage state, the second low usage state, or the deletion target. .

  When the writing unit (fifth writing unit) 135 determines that the data written in the erase target block of the block group BG3 is in the second high usage state and is not the deletion target, it writes the data to the block group. Rewrite to another writable block of BG3.

  The erasing unit (third erasing unit) 136 is discarded because each data written in the erasing target block is written in the block group BG4, rewritten in the block group BG3, or is a deletion target. If so, the erase target block is erased.

  The control unit 14 includes a writing unit 141, a determination unit 142, a selection unit 143, and an erasing unit 144.

  When the determination unit 134 determines that the data written in the erase target block of the block group BG3 is in the second low usage state and is not the deletion target, the write unit (fourth write unit) 141 concerned data Is written to the block group BG4.

  The determination unit (sixth determination unit) 142 determines whether the block group BG4 satisfies the erase condition (fourth erase condition).

  The selecting unit (fourth selecting unit) 143 selects an erase target block (fourth erase target area) from the block group BG4 when the block group BG4 satisfies the erase condition.

  The erasing unit (fourth erasing unit) 144 erases the data written in the erase target block of the block group BG4.

  The changing unit (first changing unit) 15 increases the number of blocks included in the block group BG1 when the data written in the block group BG2 is in the third high usage state, Reduce the number of blocks contained in group BG3. For example, the changing unit 15 increases the number of blocks included in the block group BG1 when the data written in the block group BG2 is to be accessed by the processor 2 and is included in the block group BG3. Reduce the number of blocks

  The changing unit (second changing unit) 16 increases the number of blocks included in the block group BG3 when the data written in the block group BG4 becomes the fourth high usage state, The number of blocks included in the group BG1 is reduced. For example, the changing unit 16 increases the number of blocks included in the block group BG3 and increases the number of blocks included in the block group BG1 when the data written in the block group BG4 is to be accessed by the processor 2. Reduce the number of.

  FIG. 4 is a flowchart showing an example of the first cache control according to this embodiment. FIG. 4 exemplifies a process in which data is written in the block group BG1 and then data is written in the block group BG2 or the block group BG3, and the erase target block of the block group BG1 is erased.

  In step S401, the writing unit 111 writes the data accessed by the processor 2 in the block group BG1.

  In step S402, the determination unit 112 determines whether the block group BG1 satisfies the erase condition.

  If the block group BG1 does not satisfy the erase condition, the process proceeds to step S406.

  If the block group BG1 satisfies the erasing condition, the selecting unit 113 selects an erasing target block from the block group BG1 in step S403.

  In step S404, the determination unit 114 determines, based on the management information 61, whether each data written in the erase target block is in the first high usage state, the first low usage state, or the deletion target.

  When the data is in the first low usage state and is not the deletion target, the writing unit 121 writes the data in the block group BG2 in step S501.

  When the data is in the first high usage state and is not the deletion target, in step S601, the writing unit 131 writes the data in the block group BG3.

  In step S405, the erasing unit 115 determines whether the data written in the block to be erased is written in the block group BG2 or the block group BG3, or if the data may be discarded because it is a deletion target. Erase the block.

  In step S406, the cache control unit 9 determines whether to end the process.

  If the cache control unit 9 does not finish the process, the process proceeds to step S401.

  The process ends when the cache control unit 9 ends the process.

  FIG. 5 is a flowchart showing an example of the second cache control according to this embodiment. FIG. 5 exemplifies a process in which data is written in the block group BG2 and the erase target block in the block group BG2 is erased.

  In step S501, when the writing unit 121 determines that the data written in the erase target block of the block group BG1 in step S404 is in the first low usage state and is not the deletion target, the data is blocked. Write to group BG2.

  In step S502, the determination unit 122 determines whether the block group BG2 satisfies the erase condition.

  If the block group BG2 does not satisfy the erase condition, the process proceeds to step S506.

  When the block group BG2 satisfies the erasing condition, in step S503, the selecting unit 123 selects the erasing target block from the block group BG2.

  In step S504, the determination unit 124 determines, based on the management information 62, whether each data written in the erase target block is the third high usage state, the third low usage state, or the deletion target.

  If the data is the third low usage state or the deletion target, the process proceeds to step S505.

  When the data is in the third high usage state and is not the deletion target, in step S601, the writing unit 137 writes the data in the block group BG3.

  In step S505, the erase unit 125 erases the data written in the erase target block of the block group BG2.

  In step S505, the cache control unit 9 determines whether to end the process.

  If the cache control unit 9 does not finish the process, the process proceeds to step S501.

  The process ends when the cache control unit 9 ends the process.

FIG. 6 is a flowchart showing an example of the third cache control according to this embodiment.
FIG. 6 exemplifies the processing from the writing of data to the block group BG3 to the erasing of the data of the block group BG3.

  In step S601, when the writing unit 131 determines that the data written in the block to be erased of the block group BG1 in step S404 is in the first high usage state and is not the deletion target, it blocks the data. Write to group BG3. Alternatively, if the writing unit 137 determines in step S504 that the data written in the block group BG2 is in the third high-usage state (for example, it is an access target in the processor 2) and is not a deletion target. , The relevant data of the block group BG2 is written to the block group BG3.

  In step S602, the determination unit 132 determines whether the block group BG3 satisfies the erase condition.

  If the block group BG3 does not satisfy the erase condition, the process proceeds to step S607.

  When the block group BG3 satisfies the erasing condition, in step S603, the selecting unit 133 selects a block to be erased from the block group BG3.

  In step S604, the determination unit 134 determines, based on the management information 63, whether each data written in the erase target block is the second high usage state, the second low usage state, or the deletion target.

  When the data is in the second low usage state and is not the deletion target, the writing unit 141 writes the data in the block group BG4 in step S701.

  If the data is in the second high usage state and is not the deletion target, in step S605, the writing unit 135 sets the data written in the erase target block of the block group BG3 to another block of the block group BG3. Rewrite it.

  In step S606, the erasing unit 136 may discard the data written in the block to be erased because it was written in the block group BG4, rewritten in the block group BG3, or because it is a deletion target. In this case, the block to be erased is erased.

  In step S607, the cache control unit 9 determines whether to end the process.

  If the cache control unit 9 does not finish the process, the process proceeds to step S601.

  The process ends when the cache control unit 9 ends the process.

  FIG. 7 is a flowchart showing an example of the fourth cache control according to this embodiment. FIG. 7 exemplifies a process in which data is written in the block group BG4 and data in the block group BG4 is deleted.

  In step S701, when the writing unit 141 determines that the data written in the block to be erased of the block group BG3 in step S604 is in the second low usage state and is not the deletion target, it blocks the data. Write to group BG4.

  In step S702, the determination unit 142 determines whether the block group BG4 satisfies the erase condition.

  If the block group BG4 does not satisfy the erase condition, the process proceeds to step S705.

  If the block group BG4 satisfies the erasing condition, in step S703, the selecting unit 143 selects a block to be erased from the block group BG4.

  In step S704, the erase unit 144 erases the data written in the block to be erased of the block group BG4.

  In step S705, the cache control unit 9 determines whether to end the process.

  If the cache control unit 9 does not finish the process, the process proceeds to step S701.

  The process ends when the cache control unit 9 ends the process.

  In the block group BG1 according to the present embodiment described above, for example, first, data is sequentially written to the blocks B1,1 and then data is sequentially written to the blocks B1,2. Data is similarly written to the blocks B1,3 to B1, K. When the blocks B1,1 to B1, K included in the block group BG1 exceed a predetermined amount of data, the FIFO erases the block B1,1 which has been written first, so that the erased block B1,1 becomes On the other hand, the data is sequentially written again. Next, when the writing to the block B1,1 is completed, the block B1,2 is erased by the FIFO. Then, the data is sequentially written again to the erased blocks B1,2. Hereinafter, the same control is repeated.

  In the block group BG1, it is determined based on the management information 61 whether or not the access to the data written in the erase target block in the block group BG1 is, for example, the first number of times or less than the first frequency. When the access to the data written in the erase target block in the block group BG1 is the first number or less than the first frequency, the block group BG2 is selected as the write destination of the data.

  On the other hand, when the data written in the block to be erased in the block group BG1 is accessed the first number of times or more than the first frequency, the block group BG3 is selected as the write destination of the data.

  When the data written in the block to be erased in the block group BG1 is the deletion target, the data is discarded.

  In the block group BG2 according to the present embodiment, first, the data of the first low usage state from the block group BG1 is sequentially written to the block B2,1 and then to the block B2,2. The blocks are written sequentially, and thereafter, the blocks B2,3 to B2, L are similarly written. When the blocks B2,1 to B2, L included in the block group BG2 exceed a predetermined data amount, the FIFO erases the block B2,1 which is the first to be written to the erased block B2,1. On the other hand, the data is sequentially written again. Next, when writing to the block B2,1 is completed, the block B2,2 is erased by the FIFO. Then, data is sequentially written again to the erased block B2,2. Hereinafter, the same control is repeated.

  In the block group BG2, it is determined based on the management information 62 whether or not the access to the data written in the erase target block in the block group BG2 is, for example, the third number of times or less than the third frequency. When the access to the data written in the erase target block in the block group BG2 is the third number of times or less than the third frequency, the data is erased.

  On the other hand, when the data written in the block to be erased in the block group BG2 is accessed a third number of times or more than the third frequency, the block group BG3 is selected as the write destination of the data.

  If the data written in the block to be erased in the block group BG2 is to be deleted, the data is discarded.

  In the block group BG3 according to the present embodiment, first, data in the first high usage state from the block group BG2, data in the third high usage state from the block group BG2, or rewriting from the block group BG3. Data is written to block B3,1 sequentially, then to block B3,2, and then to blocks B3,3 to B3, M. When the blocks B3,1 to B3, M included in the block group BG3 exceed a predetermined amount of data, the FIFO erases the block B3,1 which has been written first, and the erased block B3,1 is erased. On the other hand, the data is sequentially written again. Next, when the writing to the block B3,1 is completed, the block B3,2 is erased by the FIFO. Then, the data is sequentially written again to the erased block B3,2. Hereinafter, the same control is repeated.

  In the block group BG3, it is determined based on the management information 63 whether or not the access to the data written in the erase target block in the block group BG3 is, for example, the second number or less than the second frequency. When the access to the data written in the block to be erased in the block group BG3 is the second number or less than the second frequency, the block group BG4 is selected as the write destination of the data.

  On the other hand, when the access to the data written in the block to be erased in the block group BG3 is the second number or the second frequency or more, the data is rewritten in the block group BG3.

  If the data written in the block to be erased in the block group BG3 is the deletion target, the data is discarded.

  In the block group BG4 according to the present embodiment, first, the second low usage state data from the block group BG3 is sequentially written into the block B4,1 and then sequentially in the block B4,2. To the blocks B4,3 to B4, N in the same manner. When the blocks B4,1 to B4, N included in the block group BG4 exceed a predetermined data amount, the FIFO erases the block B4,1 which has been written first, and the erased block B4,1 is erased. On the other hand, the data is sequentially written again. Next, when the writing to the block B4,1 is completed, the block B4,2 is erased by the FIFO. Then, data is sequentially written again to the erased block B4,2. Hereinafter, the same control is repeated.

  In the present embodiment, the control unit 14 may determine whether the data written in the erase target block of the block group BG4 is in the fifth high usage state. When it is determined that the data written in the erase target block of the block group BG4 is the fifth high usage state, the control unit 13 writes the block group BG3 in order to maintain the data in the nonvolatile cache memory 4. It is also possible to write to a possible destination block. Further, in this case, the processor 2 may reduce the size of the block group BG1.

  In this embodiment, data is managed based on the four block groups BG1 to BG4.

  For example, the first data accessed once by the processor 2 (data accessed once) is managed by the block group BG1.

  For example, when the second data of the block group BG1 is accessed by the processor 2 more than once and is evicted from the block group BG1 based on the FIFO, the second data is moved from the block group BG1 to the block group BG3.

  In this embodiment, the size of the block group BG1 is larger than the size of the block group BG3.

  For example, if the third data of the block group BG1 is evicted from the block group BG1 based on the FIFO without being accessed by the processor 2, the third data is moved from the block group BG1 to the block group BG2.

  For example, if the fourth data of the block group BG3 is evicted from the block group BG3 based on the FIFO without being accessed by the processor 2, the fourth data is moved from the block group BG3 to the block group BG4.

  For example, in the block groups BG2 and BG4, metadata may be cached instead of caching the data. The metadata includes information related to the data. In other words, the metadata is additional data with which the data itself has a high degree of abstraction.

  In the present embodiment, for example, when the fifth data is stored in the block group BG1, the sixth data in the block group BG2 may be evicted based on the FIFO.

  For example, if the seventh data of the block group BG1 is accessed and is evicted from the block group BG1 based on the FIFO, the seventh data may be moved from the block group BG1 to the block group BG3, and the block group BG3. 8th data may be moved from the block group BG3 to the block group BG4 based on the FIFO, and the ninth data of the block group BG4 may be evicted from the block group BG4 based on the FIFO.

  For example, when the tenth data of the block group BG2 is accessed, the size of the block group BG1 is increased. When the size of the block group BG1 is increased, the 11th data of the block group BG3 is moved to the block group BG4 based on the FIFO.

  For example, when the twelfth data of the block group BG4 is accessed and is evicted from the block group BG4 based on the FIFO, the twelfth data is moved to the block group BG3 and the size of the block group BG1 is reduced.

  In the present embodiment described above, the maintenance judgment is performed to determine whether or not to maintain the data on a block-by-block basis, the data of the block to be retained is written to the destination block, and the write operation is performed, and the data is written to the nonvolatile cache memory 4. Existing data is erased in block units.

  In the present embodiment, the effective cache capacity can be increased, the hit rate of the nonvolatile cache memory 4 can be increased, and the speed of the information processing device 17 can be increased.

  In the present embodiment, it is possible to suppress performance degradation without performing garbage collection on the nonvolatile cache memory 4. Then, the number of times of writing to the non-volatile cache memory 4 can be reduced and the life of the non-volatile cache memory 4 can be extended as much as the garbage collection need not be executed. Further, since it is not necessary to execute garbage collection, it is not necessary to secure a spare area in the non-volatile cache memory 4, the amount of data that can be used as a cache memory can be increased, and usage efficiency can be improved. it can.

  For example, when non-volatile memory is used as cache memory, but when data is discarded regardless of block boundaries, garbage collection that moves valid data of a non-volatile memory block to another block occurs frequently. There is. On the other hand, in the present embodiment, it is not necessary to execute garbage collection in the non-volatile cache memory 4. Therefore, as described above, in the present embodiment, the nonvolatile cache memory 4 can have a long life.

[Third Embodiment]
In this embodiment, a detailed configuration of the information processing system 35 including the information processing device 17 and the SSD 5 described in the first and second embodiments will be described.

  FIG. 8 is a block diagram showing an example of a detailed configuration of the information processing system 35 according to this embodiment.

  The information processing system 35 includes the information processing device 17 and a memory system 37.

  The SSD 5 according to the first and second embodiments corresponds to the memory system 37.

  The processor 22 of the SSD 5 corresponds to the CPU 43B.

  The address conversion information 32 corresponds to a LUT (Look Up Table) 45.

  The memory 23 corresponds to the DRAM 47.

  The information processing device 17 functions as a host device.

  The controller 36 of the memory system 37 includes a front end 4F and a back end 4B.

  The front end (host communication unit) 4F includes a host interface 41, a host interface controller 42, an encryption / decryption unit (Advanced Encryption Standard (AES)) 44, and a CPU 43F.

  The host interface 41 communicates requests (write command, read command, erase command, etc.), LBA, data, etc. with the information processing device 17.

  The host interface controller (control unit) 42 controls the communication of the host interface 41 based on the control of the CPU 43F.

  The encryption / decryption unit 44 encrypts the write data (plain text) transmitted from the host interface controller 42 in the data write operation. The encryption / decryption unit 44 decrypts the encrypted read data transmitted from the read buffer RB of the back end 4B in the data read operation. The write data and the read data can be transmitted without the intervention of the encryption / decryption unit 44, if necessary.

  The CPU 43F controls the components 41, 42, 44 of the front end 4F, and controls the overall operation of the front end 4F.

  The back end (memory communication unit) 4B includes a write buffer WB, a read buffer RB, a LUT 45, a DDRC 46, a DRAM 47, a DMAC 48, an ECC 49, a randomizer RZ, a NANDC 50, and a CPU 43B.

  The write buffer (write data transfer unit) WB temporarily stores the write data transmitted from the information processing device 17. Specifically, the write buffer WB temporarily stores the write data until the write data has a predetermined data size suitable for the nonvolatile memory 24.

  The read buffer (read data transfer unit) RB temporarily stores the read data read from the non-volatile memory 24. Specifically, in the read buffer RB, the read data is rearranged so as to be in an order suitable for the information processing device 17 (order of the logical address LBA designated by the information processing device 17).

  The LUT 45 is data for converting a logical address LBA into a physical address PBA.

  The DDRC 46 controls DDR (Double Data Rate) in the DRAM 47.

  The DRAM 47 is, for example, a volatile memory that stores the LUT 45.

  A DMAC (Direct Memory Access Controller) 48 transfers write data, read data and the like via an internal bus IB. Although one DMAC 48 is shown in FIG. 8, the controller 36 may include two or more DMACs 48. The DMAC 48 is set at various positions within the controller 36 as needed.

  The ECC (Error Correcting Unit) 49 adds an ECC (Error Correcting Code) to the write data transmitted from the write buffer WB. The ECC 49 corrects the read data read from the non-volatile memory 24, if necessary, by using the added ECC when transmitting to the read buffer RB.

  The randomizer RZ (or scrambler) distributes the write data so that the write data is not biased toward a specific page or word line direction of the nonvolatile memory 24 during the data write operation. By thus distributing the write data, the number of times of writing can be equalized, and the cell life of the memory cells MC of the nonvolatile memory 24 can be extended. Therefore, the reliability of the nonvolatile memory 24 can be improved. Further, during the data read operation, the read data read from the non-volatile memory 24 passes through the randomizer RZ.

  A NANDC (NAND Controller) 50 uses a plurality of channels (here, four channels CH0 to CH3) to access the nonvolatile memory 24 in parallel in order to satisfy a request for a predetermined speed.

  The CPU 43B controls the above-described components (45 to 50, RZ) of the back end 4B and controls the overall operation of the back end 4B.

  Note that the configuration of the controller 36 is an example, and the present invention is not limited to this configuration.

  FIG. 9 is a perspective view showing an example of a storage system according to this embodiment.

  The storage system 100 includes a memory system 37 as an SSD.

  The memory system 37 is, for example, a relatively small module, and an example of its external dimensions is about 20 mm × 30 mm. The size and dimensions of the memory system 37 are not limited to this, and can be changed to various sizes as appropriate.

  The memory system 37 can be used by being attached to the information processing device 17 such as a server in a data center or a cloud computing system operated in an enterprise, for example. Therefore, the memory system 37 may be an enterprise SSD (eSSD).

  The memory system 37 includes, for example, a plurality of connectors (for example, slots) 38 that open upward. Each connector 38 is, for example, a SAS (Serial Attached SCSI) connector or the like. According to this SAS connector, the information processing device 17 and each memory system 37 can perform high-speed communication with each other through a 6 Gbps dual port. Note that the connector 38 is not limited to this, and may be, for example, PCIe (PCI Express) or NVMe (NVM Express).

  The plurality of memory systems 37 are attached to the connectors 38 of the information processing device 17, respectively, and are supported side by side with each other in an upright posture in a substantially vertical direction. With such a configuration, the plurality of memory systems 37 can be compactly packaged and mounted, and the size of the memory system 37 can be reduced. Furthermore, each shape of the memory system 37 according to the present embodiment is a 2.5-inch SFF (Small Form Factor). With such a shape, the memory system 37 can have a shape compatible with the enterprise HDD (eHDD) (compatible shape), and can easily achieve system compatibility with the eHDD.

  The memory system 37 is not limited to the enterprise type. For example, the memory system 37 can be applied as a storage medium of a consumer electronic device such as a notebook type portable computer or a tablet type terminal.

  As described above, in the information processing system 35 and the storage system 100 having the configurations described in the present embodiment, it is possible to obtain the same effect as that of the second embodiment in large-capacity storage.

  The configuration of the memory system 37 according to the present embodiment may be applied to the information processing device 17 according to the first embodiment. For example, the processor 2 of the first embodiment may correspond to the CPU 43B. The address conversion information 7 may correspond to the LUT 45. The memory 3 may correspond to the DRAM 47. The non-volatile cache memory 4 may correspond to the non-volatile memory 24.

  Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

  2, 22 ... Processor, 3, 23 ... Memory, 4 ... Nonvolatile cache memory, 5 ... SSD, 61-64 ... Management information, 7, 32 ... Address translation information, 8, 25 ... Address translation unit, 9 ... Cache control Part, 10 ... Generation part, 11-14 ... Control part, 15, 16 ... Change part, 17 ... Information processing device, 18, 21, 29 ... Transmission part, 19, 30 ... Reception part, 20, 26, 111, 121 , 131, 135, 137, 141 ... Writing unit, 24 ... Non-volatile memory, 27 ... Valid / invalid generation unit, 28, 113, 123, 133, 143 ... Selection unit, 31 ... Garbage collection unit, 33 ... Valid / invalid Information, 34 ... Delete information, 35 ... Information processing system, 36 ... Controller, 37 ... Memory system, 38 ... Connector, 4F ... Front end, 4B ... Back end, 41 ... Host Interface, 42 ... Host interface controller, 43B, 43F ... CPU, 44 ... Encryption / decryption unit, 45 ... LUT, 46 ... DDRC, 47 ... DRAM, 48 ... DMAC, 49 ... ECC, 50 ... NANDC, 100 ... Storage System, 112, 114, 122, 124, 132, 134, 142 ... Judgment unit, 115, 125, 136, 144 ... Erase unit, BG1 to BG4 ... Block group, WB ... Write buffer, RB ... Read buffer, RZ ... Randomizer .

Claims (5)

Ri by the processor, the memory device and the memory and a second memory for storing a portion of the valid data stored in the device, controls the write and read data to and including a first memory including a plurality of areas there is provided a method of,
The processor receives, from the memory device, first information indicating valid data in a garbage collection target area selected from the plurality of areas by the memory device;
The processor writes, in the second memory, data excluding the deletion target data indicated by the deletion instruction generated by the processor from the valid data indicated by the first information;
And said processor generates a second information indicating the deleted data in the valid data indicated by the first information,
The processor transmits the second information to the memory device in order to cause the data indicated by the second information to be deleted by garbage collection for the garbage collection target area of the first memory ; ,
A method comprising: The second memory is a cache memory, the method of claim 1. The second memory is a nonvolatile method of claim 1 or claim 2. Wherein the processor, the after the garbage collection object area is selected in the memory device, receiving the first information from the memory device, before the garbage collection is performed in the memory device, the second Sending information to the memory device,
The method according to any one of claims 1 to 3 . The first information includes identification information of the plurality of areas in said first non-volatile memory provided in the memory device, the identification information of the data written in the plurality of areas in said first memory Including information that associates and
The method according to any one of claims 1 to 4 .

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