CN108228470B

CN108228470B - Method and equipment for processing write command for writing data into NVM (non-volatile memory)

Info

Publication number: CN108228470B
Application number: CN201611193448.5A
Authority: CN
Inventors: 孙清涛; 殷雪冰
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2016-12-21
Filing date: 2016-12-21
Publication date: 2021-05-18
Anticipated expiration: 2036-12-21
Also published as: CN109164976B; CN108228470A; CN109164976A

Abstract

The application provides a method of processing a write command to write data to an NVM, wherein a cache unit is provided, the cache unit comprising a first portion and a second portion, the method comprising: receiving a first write command; and sending a first message indicating that the processing of the first write command is completed to the host in response to the data corresponding to the first write command being written into the first part of the cache unit. The technical scheme disclosed by the application can at least reduce the delay caused by the 'lower case' command and improve the processing efficiency.

Description

Method and equipment for processing write command for writing data into NVM (non-volatile memory)

Technical Field

The present application relates to the field of storage, and more particularly, to optimizing the processing of "lower case" commands in a solid state storage device.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The solid-state storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory, XPoint Memory), and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in a variety of ways including software, hardware, firmware, or a combination thereof. The control unit 104 may be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller. Software is executed in the processor or controller to manipulate the hardware of the control unit 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

The software and/or firmware (hereinafter collectively referred to as "firmware") running in the control component 104 may be stored in the NVM chip 105 or another firmware memory. Upon power up of the solid state storage device 102, firmware is loaded from the firmware memory into the DRAM 110 and/or memory internal to the control component 104. Optionally, the firmware is received and loaded through interface 103 or a debug interface.

Control section 104 is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to the interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

The memory Target (Target) is one or more Logic Units (LUNs) of a shared Chip Enable (CE) signal within the NAND flash package. One or more dies (Die) may be included within the NAND flash memory package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other. The meaning for target, logical Unit, LUN, Plane (Plane) is provided in "Open NAND Flash Interface Specification (Revision 3.0)" available from http:// www.micron.com// media/Documents/Products/Other% 20Documents/ONFI3_0gold.

Data is typically stored and read on a storage medium on a page-by-page basis. And data is erased in blocks. A block contains a plurality of pages. Pages on the storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. Physical pages may also have other sizes.

In the solid-state storage device, mapping information from logical addresses to physical addresses is maintained using FTL (Flash Translation Layer). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented in the prior art using an intermediate address modality. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.

Volatile Write Cache (Volatile Write Cache) is defined in the NVMe standard.

When an NVM is programmed, a full page of data needs to be written, and the amount of data to be written by a write command sent by the host is sometimes smaller than the size of the NVM's physical page, a situation also known as "lower-case". In some cases, when a "small write" occurs, a partial page of data needs to be read from the NVM, spliced with the written data, and written to the flash memory (called read-modify-write-back, RMW), which results in higher latency in handling the "small write".

Disclosure of Invention

The present application is directed to processing a "lower case" command for NVM to overcome the disadvantage of the prior art that the "lower case" command causes higher latency.

According to a first aspect of the present invention, there is provided a first method of processing a write command to write data to an NVM according to the first aspect of the present invention, wherein a cache unit is provided, the cache unit comprising a first portion and a second portion, the method comprising: receiving a first write command; and sending a first message indicating that the processing of the first write command is completed to the host in response to the data corresponding to the first write command being written into the first part of the cache unit.

According to a first method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a second method of processing a write command to write data to an NVM, further comprising: and responding to the data corresponding to the first write command being written into the first part of the cache unit, and sending out a second message indicating that the cache unit is in a busy state.

According to the second method of processing a write command to write data to an NVM according to the first aspect of the present invention, there is provided a third method of processing a write command to write data to an NVM, wherein when the cache unit is in a "busy" state, other write commands for the cache unit than the first write command are put into a wait state.

According to a first method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a fourth method of processing a write command to write data to an NVM, further comprising: and detecting whether the first write command hits a cache unit, and if the first write command hits the cache unit, writing data into the hit cache unit.

According to a fourth method of handling write commands for writing data to NVM according to the first aspect of the present invention, there is provided a fifth method of handling write commands for writing data to NVM, wherein the first write command hits the cache location if the range of logical addresses recorded by the cache location contains the logical address of the first write command.

According to the fourth or fifth method for processing a write command for writing data to an NVM according to the first aspect of the present invention, there is provided a sixth method for processing a write command for writing data to an NVM, wherein, in a case where the first write command hits the cache unit, if a logical address range accessed by the first write command does not overlap with a logical address range of data contained in the hit cache unit, data corresponding to the first write command is written to the cache unit.

According to one of the fourth to sixth methods of processing a write command to write data to an NVM according to the first aspect of the present invention, there is provided a seventh method of processing a write command to write data to an NVM, wherein in case that the first write command hits the cache unit, if a logical address range accessed by the first write command overlaps with a logical address range of data contained in the hit cache unit, waiting for the cache unit to be emptied; and writing the data corresponding to the first write command into the emptied cache unit.

According to one of the fourth to seventh methods of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided an eighth method of processing a write command to write data to an NVM, further comprising: and if the first write command misses the cache unit, allocating the cache unit in an idle state to the first write command.

According to a first method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a ninth method of processing a write command to write data to an NVM, further comprising: responding to the data corresponding to the first write command written into the first part of the cache unit, reading the data corresponding to the logical address range of the second part of the cache unit based on the logical address range of the second part of the cache unit, and filling the read data into the second part of the cache unit; and marking the cache unit as being in a busy state.

According to the first or ninth method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a tenth method of processing a write command to write data to an NVM, further comprising: and in response to the data corresponding to the first write command being written into the first part of the cache unit, marking the cache unit as being in an occupied state.

According to a tenth method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided an eleventh method of processing a write command to write data to an NVM, further comprising: reading data corresponding to the logical address range of the second part of the cache unit based on the logical address range of the second part of the cache unit in the occupied state, and filling the read data into the second part of the cache unit; and marking the cache unit as being in a busy state.

According to one of the first to eleventh methods of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a twelfth method of processing a write command to write data to an NVM, further comprising: receiving a second write command; and writing the data corresponding to the second write command into a second part of the cache unit according to the second write command.

According to a twelfth method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a thirteenth method of processing a write command to write data to an NVM, further comprising: if the second write command hits the cache unit, the logical address range accessed by the second write command is not overlapped with the logical address range accessed by the first write command, and the cache unit is in a busy state, the processing of the second write command is suspended until the cache unit is in an idle state, and data corresponding to the second write command is written into a second part of the cache unit in the idle state.

According to a twelfth method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a fourteenth method of processing a write command to write data to an NVM, further comprising: and if the second write command hits the cache unit and the cache unit is in an occupied state, writing data corresponding to the second command into a second part of the cache unit.

According to a twelfth method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a fifteenth method of processing a write command to write data to an NVM, further comprising: in response to the second portion of the cache location being written with data, issuing a fourth message indicating a location of the second portion where the cache location is "occupied".

According to a fifteenth method of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a sixteenth method of processing a write command to write data to an NVM, further comprising: reading data corresponding to the logic address of the second part based on the logic address of the second part in the cache unit, and filling the read data into the second part of the cache unit; if the filled location has data written to it, the read data to be written to the filled location is discarded.

According to one of the ninth to sixteenth methods of processing a write command to write data to an NVM of the first aspect of the present invention, there is provided a seventeenth method of processing a write command to write data to an NVM, further comprising: and sending the data of the cache unit to a nonvolatile memory, and marking the cache unit to be in an idle state.

According to a second aspect of the present invention, there is provided a first method of processing a write command to write data to an NVM according to the second aspect of the present invention, wherein a plurality of buffer units are provided, each buffer unit comprising a first portion and a second portion, and the plurality of buffer units are divided into a first group and a second group, the method comprising: receiving a first write command; in response to the data corresponding to the first write command being written into a first portion of a first cache belonging to a first group, sending a first message to a host indicating that processing of the first write command is complete; and writing at least data of a second cache unit belonging to the second group to the NVM.

According to a first method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a second method of processing a write command to write data to an NVM, further comprising: setting the first cache unit to belong to a second group; and/or setting the second cache unit to belong to the first group.

According to the first or second method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a third method of processing a write command to write data to an NVM, wherein data corresponding to the write command is written only to cache cells belonging to a first group; and writing only data of the buffer cells belonging to the second group to the NVM.

According to one of the first to third methods of processing a write command to write data to an NVM according to the second aspect of the present invention, there is provided a fourth method of processing a write command to write data to an NVM, further comprising: all data belonging to the cache cells of the second group is written to the NVM.

According to one of the first to fourth methods of processing a write command to write data to an NVM according to the second aspect of the present invention, there is provided a fifth method of processing a write command to write data to an NVM, wherein based on a logical address range of a second portion of a second cache unit, data corresponding to the logical address range of the second portion is read, and the read data is filled into the second portion of the second cache unit; and writing the complete data of the second cache unit into the NVM.

According to a fifth method of processing a write command to write data to an NVM according to the second aspect of the present invention, there is provided a sixth method of processing a write command to write data to an NVM, wherein the logical address range of the second portion of the second buffer unit is an address range of the logical address range of the second buffer unit to which data is not written.

According to one of the second to sixth methods of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a seventh method of processing a write command to write data to an NVM, further comprising: receiving a second write command; and if the second write command hits the first cache unit, and the logical address range accessed by the second write command is not overlapped with the logical address range accessed by the first write command, writing the data corresponding to the second command into a second part of the first cache unit.

According to one of the second to sixth methods of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided an eighth method of processing a write command to write data to an NVM, further comprising: receiving a second write command; if the second write command hits the first cache unit, and the logical address range accessed by the second write command overlaps with the logical address range accessed by the first write command, suspending the processing of the second write command until a third cache unit belonging to the first group is allocated to the second write command; and writing data corresponding to the second command into the third cache unit.

According to one of the second to sixth methods of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a ninth method of processing a write command to write data to an NVM, further comprising: receiving a second write command; and if the second write command hits the first cache unit, writing data corresponding to the second command into the first cache unit.

According to one of the seventh to ninth methods of processing a write command to write data to an NVM according to the second aspect of the present invention, there is provided a tenth method of processing a write command to write data to an NVM, wherein the write command hits the cache unit if the logical address range recorded by the cache unit contains the logical address of the write command.

According to a first method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided an eleventh method of processing a write command to write data to an NVM, further comprising: emptying at least the second cache unit.

According to a second method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a twelfth method of processing a write command to write data to an NVM, wherein under specified conditions, a first cache unit is set to belong to a second group; and/or setting the second cache unit to belong to the first group.

According to a twelfth method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a thirteenth method of processing a write command to write data to an NVM, wherein the specified condition is a certain period of time.

According to a twelfth method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a fourteenth method of processing a write command to write data to an NVM, wherein the specified condition is that the second buffer unit is emptied.

According to a twelfth method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a fifteenth method of processing a write command to write data to an NVM, wherein the specified condition is that data stored by the first cache unit reaches a specified threshold.

According to a twelfth method of processing a write command to write data to an NVM of the second aspect of the present invention, there is provided a sixteenth method of processing a write command to write data to an NVM, wherein the specified condition is that the number of memory cells in the first group of cache cells to which data is written reaches a specified threshold.

According to a first method of processing a write command to write data to an NVM according to the second aspect of the present invention, there is provided a seventeenth method of processing a write command to write data to an NVM, wherein the number of buffer cells in the first and second groups is determined according to a ratio of an overall duration of the write operation to an overall duration of the read operation.

According to a third aspect of the present invention, there is provided a processor for processing a write command for writing data to an NVM, comprising: one or more processors; a memory; a program stored in the memory, which when executed by the one or more processors, causes the processors to perform the method as described above.

According to a fourth aspect of the present invention, there is provided an apparatus for processing a write command for writing data to an NVM, wherein a cache unit is provided, the cache unit comprising a first portion and a second portion, the apparatus comprising: means for receiving a first write command; means for sending a first message to the host indicating that processing of the first write command is complete in response to data corresponding to the first write command being written to the first portion of the cache unit.

According to a fifth aspect of the present invention, there is provided an apparatus for processing a write command for writing data to an NVM, wherein a plurality of buffer units are provided, each buffer unit comprising a first portion and a second portion, and the plurality of buffer units are divided into a first combined second group, the buffer units in the first group being first buffer units, the buffer units in the second group being second buffer units, the apparatus comprising: means for receiving a first write command; means for sending a first message to a host indicating that processing of a first write command is complete in response to data corresponding to the first write command being written to a first portion of a first cache; and means for writing at least the data of the second cache unit to the NVM.

According to a sixth aspect of the present invention, there is provided a computer-readable storage medium storing a program which, when executed by an apparatus, causes the apparatus to perform the method described above.

The implementation mode disclosed by the application can at least reduce the delay caused by the 'lower-case' command and improve the processing efficiency.

Drawings

FIG. 1 shows a block diagram of a prior art storage device;

FIG. 2 shows a block diagram of a control component of a storage device according to an embodiment of the application;

FIG. 3 shows a schematic diagram of a front-end cache according to an embodiment of the invention;

FIG. 4 illustrates a flow diagram for processing a write command to write data to an NVM in accordance with an embodiment of the present invention;

FIG. 5 shows a schematic diagram of a front-end cache according to an embodiment of the invention;

FIGS. 6A and 6B illustrate a diagram of when a write command hits in a cache molecule, according to one embodiment of the invention;

FIG. 7 illustrates a schematic diagram of a front-end cache according to another embodiment of the invention;

FIG. 8 is a diagram illustrating a cache unit for emptying a front-end cache according to an embodiment of the invention;

FIGS. 9A-9E illustrate the state of individual buffer units and the change of data in buffer subunits for different write commands;

FIG. 10 illustrates a flowchart of a method of processing a write command to write data to an NVM in accordance with yet another embodiment of the present invention; and

11A-11C illustrate state changes of a cache unit and cache sub-unit when multiple different write commands are received according to the embodiment shown in FIG. 10.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the terms "first," "second," and the like in this disclosure are used merely for convenience in referring to objects, and are not intended to limit the number and/or order.

FIG. 2 shows a block diagram of a control component of a storage device according to an embodiment of the invention. The control unit 104 includes a host interface 210, a front-end processing module 220, a flash management module 230, and a back-end processing module 240.

The host interface 210 is used to exchange commands and data with a host. In one example, the host and the storage device communicate via NVMe/PCIe protocol, and the host interface 210 processes the PCIe protocol data packet, extracts the NVMe protocol command, and returns a processing result of the NVMe protocol command to the host. FTL module 230 converts the logical address of NVMe protocol command into a physical address, and manages the flash memory, providing services such as wear leveling and garbage collection. The back-end processing module 240 accesses the one or more NVM chips according to the physical address. Processing before accessing the FTL is referred to as front-end processing, and processing after accessing the FTL is referred to as back-end processing. The front-end control unit 104 is also coupled to an external memory (e.g., RAM) 260. A portion of the space of the memory 260 is used as a front-end cache (front-end cache 265) that the front-end processing module 220 may access to the memory 260 to use. Optionally, a front-end cache module 225 is provided within the control component 104 for use as a front-end cache.

FIG. 3 shows a schematic diagram of a front-end cache according to an embodiment of the invention. By way of example, the front-end cache may include multiple cache molecules (only one cache molecule 310 is shown in FIG. 3 for simplicity). Each cache unit may include multiple cache subunits (shown in fig. 3 as cache subunits A, B, C and D). By way of example, each buffer subunit is 1KB in size, while each buffer unit is 4KB in size. It is understood that the cache unit and the cache sub-unit may have other sizes. Preferably, the size of the cache subunit is equal to the minimum data unit size of the IO command sent by the host to the solid-state storage device, and the size of the cache subunit is the data unit size corresponding to the physical address of one entry in the FTL table.

The front-end cache also records metadata. The metadata records the state corresponding to the cache unit, the logical address and/or the cache subunit usage of the cache unit. The logical address of the buffer unit records the logical address of the data written in the buffer unit.

And determining whether the IO command hits the cache unit or not by comparing the logical address of the IO command with the logical address of the cache unit recorded in the metadata. For example, if the logical address of the IO command overlaps with the logical address of the cache unit, the IO command hits the cache unit.

The cache unit stores data corresponding to the IO command. For example, for a write command, the buffer unit records data to be written into the NVM chip from the host, and provides an indication of completion of processing of the write command to the host after the data of the write command is written into the buffer unit, so as to reduce the write command processing delay. Optionally, the front-end cache may also be used as a cache to speed read operations.

Alternatively, the cache unit is provided by the memory 260 (see FIG. 2), while the metadata is stored by a memory internal to the control component 104.

To achieve at least one of the objects of the present invention, the present invention may be implemented as follows.

Example 1

A cache sub-unit (e.g., cache sub-units A, B, C and D in fig. 3) of the cache unit may be divided into a first portion and a second portion. The first portion represents the portion of the buffer subunit to which data is written and the second portion represents the portion of the buffer subunit to which data is not written. It should be understood that each of the first portion and the second portion may include a plurality of buffer subunits, and the buffer subunits in the same portion may be adjacent or non-adjacent. In addition, the first part and the second part are not static, the second part of the cache subunit can be written with data subsequently, and the data in the first part of the cache subunit can be cleared subsequently. For example, cache subunits a and C in fig. 3 may belong to the first part, while cache subunits B and D may belong to the second part.

FIG. 4 illustrates a flow diagram for processing a write command to write data to an NVM in accordance with an embodiment of the present invention. The method comprises the following steps: in operation S410, a write command is received; in operation S420, a message indicating that write command processing is completed is transmitted to the host in response to data corresponding to the received write command being written to a portion of the cache unit.

It should be noted that the write command is a command for writing to the NVM, and the buffer unit is transparent to the write command. In an embodiment of the present application, when data is written to the cache unit but not yet written to the NVM, a reply message is sent to the host, causing the host to consider the write command processing to be complete. Thereby reducing write command processing latency.

The state of the cache unit is recorded in the metadata. According to embodiments of the invention, a cache molecule may be in an "idle" or "busy" state. It will be appreciated that other states may also be provided for the cache location.

The state transition of the buffer unit is described in connection with table 1.

TABLE 1

Referring to table 1, for a cache unit in an "idle" state, in response to data of a write command being written to a subunit of the cache unit, the state of the cache unit changes from "idle" to "busy", and an output event as a state transition, an ACK (acknowledge) message is provided to the host to indicate that processing for the write command is complete. And optionally, initiating a "flush" process for the cache molecule. The "flush" process is initiated even if the data of the write command only fills a portion of the buffer sub-unit of the buffer unit.

In the process of "emptying", reading out data corresponding to the logical address of the cache subunit in which data is not written in the cache unit from the NVM of the solid-state storage device, and filling the read-out data into the cache unit. In response to the data read from the flash memory being written into an unused buffer sub-unit of the buffer unit (the buffer unit is filled, and there is no buffer sub-unit to which data is not written), the data of the entire buffer unit is written into the logical address range recorded by the metadata of the buffer unit.

With continued reference to table 1, for a cache location in a "busy" state, the status of the cache location becomes "free" in response to the data read from the NVM being merged with the data in the cache location and the complete data for the cache location being written to the NVM ("clear" process complete). A cache molecule in the "idle" state may be allocated to receive data corresponding to a write command. And for the cache unit in the busy state, if a write command hitting the cache is received, suspending the write command (suspending the processing of the write command) as a response, and the memory unit is still in the busy state.

The following describes a process of processing a write command according to an embodiment of the present invention.

In response to receiving a write command, a buffer unit is allocated for the write command. The newly allocated cache location may be in a "Free" state and the logical address of the write command is recorded in the metadata of the allocated cache location. For a "lower case" command, the range of logical addresses for the write command may be smaller than the range of logical addresses to be recorded in the metadata of the cache location. In this case, the logical address of the write command is intercepted to fit the logical address range of the cache unit, and the intercepted logical address is recorded in the metadata of the cache unit.

And writing the data to be written by the write command into the cache unit. And for the 'small write' command, writing data into the corresponding cache subunit in the cache unit according to the logical address of the write command. For example, a write command indicates to write 1KB of data to an address range starting at 100KB in the logical address space, while the size of the buffer unit is 4 KB. According to the logical address range (1K space of 100KB-101 KB) of the write command, a 4K-sized space (truncated logical address) of logical addresses 100KB-104KB (none) is recorded in the metadata of the buffer unit allocated to the write command. Since the 1K space starting at address 100KB is located in the 1 st 1K space of the 100KB-104KB (exclusive) address range, the 1KB data of the write command is written into the first buffer subunit of the buffer unit (the first part of the buffer unit) accordingly. It is also recorded in the metadata of the cache units that the first cache subunit is used and that the other three cache subunits (the second part of the cache unit) are not used.

Once the data of the 'small-case' command is completely written into the cache unit, a response message indicating that the processing or execution of the 'small-case' command is completed is sent to the host, so that the processing delay of the write command is reduced.

Optionally, in response to the data corresponding to the "lower case" command being written into the buffer unit, the status of the buffer unit is set to "busy". And, still optionally, issuing a message indicating that the cache molecule is in a "busy" state.

In the "emptying" process, for those cache subunits (or logical address spaces) in which data is not written in the cache unit, reading data corresponding to the logical address of the cache subunit in which data is not written in the cache unit from the NVM of the solid-state storage device, and filling the read data into the cache unit. For example, the metadata of the buffer unit records a 4K size range of logical addresses 100KB-104KB (not included), wherein the first buffer subunit (1K range of logical addresses 100KB-101 KB) of the buffer unit is written with data, and the other three buffer subunits (3K space of logical addresses 103KB-104 KB) are not used, the data of the 3K range of logical addresses 103KB-104KB is read, and the read data is filled into the other three buffer subunits. In response to data read out from the flash memory being written to an unused buffer subunit of the buffer unit, data of the entire buffer unit (e.g., 4KB in size) is written to a logical address range (e.g., a 4K-sized range of logical addresses 100KB-104KB (not inclusive)) recorded by metadata of the buffer unit.

When the "flush" process is completed, the data for the entire buffer unit is written to the flash memory, the status of the buffer unit changes from "busy" to "free" and may be assigned again to process write commands.

Those skilled in the art will appreciate that reading or writing data according to logical addresses requires obtaining physical addresses from the FTL module 230 (see fig. 2) and reading or writing data from or to the physical addresses.

Example 2

According to embodiment 2 of the present invention, in response to receiving a "lower case" command, it is detected whether the "lower case" command hits in a cache unit, and data corresponding to the lower case command is written in the hit cache unit. If no cache location is hit, then a cache location is allocated for the "lower case" command.

According to one embodiment of the present invention, whether the "lower case" command hits in the cache unit may be determined by identifying whether the logical address range recorded by the cache unit contains the logical address range of the "lower case" command. If the logical address range of the "small-case" command is contained in the logical address range of a certain cache location, the "small-case" command hits the cache location, otherwise, the "small-case" command is considered to miss the cache location.

When a "lower case" command hits a cache location, there may be two cases. (1) In the cache unit, the logical address range indicated by the "lower case" command is not written with data (see fig. 5); (2) in the cache unit, the logical address range indicated by the "lower case" command has been written with data (see fig. 6A).

FIG. 5 shows a schematic diagram of a front-end cache according to an embodiment of the invention. As shown in fig. 5, the buffer subunits a and C of the buffer unit store data, while the buffer subunits B and D do not store any data. And the small write command hits the buffer location and will write data in the buffer sub-locations B and/or D where no data is to be written. In the example of fig. 5, if the hit cache subunit B and/or D has not been written with data, the corresponding data may be directly written into the hit cache unit. Generally, if the logical address range accessed by the "lower case" command does not overlap with the logical address range of the data contained in the hit cache unit, the corresponding data can be directly written into the hit cache unit.

FIGS. 6A and 6B are schematic diagrams illustrating another state change when a write command hits in a cache location, according to one embodiment of the invention. As shown in FIG. 6A, cache subunits B, C and D of a cache unit have data stored therein, while cache subunit A has no data stored therein, and a "lower case" command hits the cache unit and data is to be written in cache subunits B and/or D. As shown in fig. 6A, the logical address range accessed by the "lower case" command overlaps with the logical address range of the data contained in the hit cache unit, in this case, a "flush" process needs to be initiated to flush the data in the cache unit, so that the cache unit is in an "idle" state. The emptied buffer unit is shown in fig. 6B. And then writing the data corresponding to the 'lower-case' command into the emptied cache unit. It should be understood that when the data in the cache location is flushed, the "lower case" command is suspended until the flush operation is completed.

If the "lower case" command misses any cache location, a new cache location is allocated for the "lower case" command. The allocated new buffer unit may be a buffer unit in an "idle" state or a buffer unit in a "busy" state. If the allocated new buffer unit is a buffer unit in an "idle" state, the data of the "lower case" command is written into the buffer unit in the "idle" state. If the allocated new cache unit can be a cache unit in a busy state, the allocated cache unit is emptied first, and then the data corresponding to the lower-case command is written into the emptied cache unit.

See, by way of example, fig. 7. Fig. 7 shows a schematic diagram of a front-end cache according to still another embodiment of the invention. As shown in FIG. 7, the logical address in the metadata of cache unit 710 indicates a range of 100KB-104KB (none).

A buffer unit 710 (shown in fig. 7) has been allocated for write commands that write 1KB of data to an address range starting at 100KB in logical address space. The cache molecule 710 is in an "occupied" state. Accordingly, the logical address in the metadata of the cache unit 710 indicates a range of 100KB-104KB (none). Next, a write command (noted W2) to write 2KB of data in response to receiving an address range beginning at access to the logical address space 101 KB. Since the logical address range accessed by the write command W2 also belongs to the logical address range recorded in the metadata of the cache unit 710, the cache unit 710 is assigned to the write command W2. Alternatively, if the logical address corresponding to the write command W2 is not recorded in the metadata of any cache unit, a cache unit is allocated to the write command W2.

If cache molecule 710 is in a busy state, write command W2 is added to the wait list or suspended. If at least the 2 nd and 3 rd buffer sub-units (101K and 102K) in the buffer unit 710 are not occupied by data, the data of the write command W2 is written into the 2 nd and 3 rd buffer sub-units (indicated as 101K and 102K in fig. 7) of the buffer unit 710 according to the logical address, and the state of the buffer unit 710 changes from "occupied" to "busy".

It is to be understood that "100K" in FIG. 7 indicates a logical address range of 100K-101K (not included), and similarly "103K" indicates a logical address range of 103K-104K (not included).

Fig. 8 shows a schematic diagram of a cache unit of a flush front-end cache according to an embodiment of the invention. As shown in FIG. 8, the exemplary cache molecule 810 of FIG. 8 includes cache subunits A, B, C, and D, where a "lower case" command has data written in cache subunit C, but not data written in cache subunits A, B and D.

According to the embodiment of the invention, when the cache unit is allocated to the write command, the logical address corresponding to the cache unit is recorded in the metadata of the cache unit according to the logical address of the write command. The range of logical addresses corresponding to the cache units (i.e., the logical addresses indicated by the metadata of the cache units) are all aligned by a specified boundary (e.g., 4KB aligned, with the start address located at an integer multiple of 4KB, e.g., 0, 4KB, 8KB), and the size of the logical address space corresponding to the cache units is, e.g., 4 KB. For example, in fig. 8, a "small write" command in which data is written in buffer subunit C accesses a range of 101KB to 102KB (not inclusive), in response to allocation of buffer unit 810 for the "small write" command, a logical address range (100KB to 104KB (not inclusive)) corresponding to buffer unit 810 is set in buffer unit 810 aligned by a 4KB boundary, and a logical address range corresponding to buffer subunit a is 100KB to 101KB (not inclusive), a logical address range corresponding to buffer subunit B is 101KB to 102KB (not inclusive), a logical address range corresponding to buffer subunit C is 102KB to 103KB (not inclusive), and a logical address range corresponding to buffer subunit D is 103KB to 104KB (not inclusive).

The "small write" command writes data in the buffer subunit C, reads data corresponding to the logical address from the NVM according to the logical addresses of the buffer subunits A, B and D, and fills the read data in the buffer subunits A, B and D. And when both cache sub-units A, B, C and D of cache unit 810 are filled with data, writing the data of cache unit 810 in its entirety to NVM.

Example 3

In embodiment 3 according to the present invention, the states of the buffer unit include an "idle" (Free) state, an "occupied" (Dirty) state, and a "Busy" (Busy) state.

Table 2 is a state transition table of the cache unit of embodiment 3.

TABLE 2

As shown in Table 2, the cache molecule is initially in an "idle" state. After the write command writes data into some of the buffer subunits, an ACK (acknowledgement) message is sent to the host to indicate that the write operation is complete, and the buffer subunits into which the data is written are recorded. And initiating the operation of reading data from the NVM for the cache subunit to which the data is not written according to the address range of the cache subunit to which the data is not written. And the state of the buffer unit is changed to an "occupied" state.

When the cache unit is in an "occupied" state, it means that at least some cache subunits in the cache unit have data stored therein. In this case, if the received write command accesses the cache subunits to which data is written before, the data is written into the cache subunits according to the write command; if the received write command accesses the cache subunits to which data has not been written before, the data is written into the cache subunits according to the write command. When data is written into the cache subunit according to the write command, an ACK message is sent to the host to indicate that the write command processing is completed, and at the moment, the cache unit is in an occupied state.

In another case, when the cache units are in an "occupied" state and some cache subunits have been filled with data from the NVM, in this case, if a write command accesses those cache subunits that have been filled with data from the NVM, the write command is suspended waiting for the cache units to be emptied. At this time, the buffer unit is still in the "occupied" state.

When all data read from the NVM is written to the buffer sub-unit, the data in the buffer unit is written to the NVM in its entirety (also referred to as the buffer unit being "emptied"). The state of the buffer cell changes from the busy state to the busy state. And during the process of writing the data of the cache unit into the NVM in a whole, the state of the cache unit is kept in a busy state.

If a cache location is in a "busy" state, write commands that hit the cache location are suspended until the cache location changes from a "busy" state to an "idle" state.

After the data in the buffer unit is entirely written to the NVM, the buffer unit is emptied, and the status of the buffer unit changes from "busy" to "idle".

By way of example, there are four write commands (denoted as W3, W4, W5, and W6, respectively). The write command W3 writes 1KB of data to logical address 200KB, the write command W4 writes 1KB of data to logical address 300KB, and the write command W5 writes 2KB of data to logical address 201 KB; w6 writes 1KB of data to logical address 203 KB. Fig. 9A to 9E show the states of the respective buffer units and the change of data in the buffer subunits in the case of different write commands.

And there are buffer unit 910 and buffer 920 in "idle" state.

First, as shown in fig. 9A, in response to receiving a write command W3, a buffer unit 910 is allocated for a write command W3. In response, the logical address range 200KB-204KB (none) is marked in the metadata of cache unit 910. Upon the write command W3 accessing the 1 st 1KB space starting at logical address 200KB, the data of the write command W3 is written into the buffer subunit 912. The state of the recording logic unit 910 is changed from "free" to "occupied" in the metadata, and the recording buffer sub-unit (912) is written with data. And reading data from the logical address range (201KB-204KB (none)) corresponding to the cache subunit (914, 916, 918) to which the data is not written.

At this time, the buffer unit 920 is still in an "idle" state.

Next, as shown in FIG. 9B, in response to receiving the write command W4, the logical address it accesses is located in 1KB of space starting at 300 KB. As a result of the lookup, none of the logical address ranges of the cache locations contains the address range accessed by the write command W4, and therefore the "free" state cache location 920 is allocated for the write command W4, and the data of the write command W4 is written to the sub-cache location 922. And marks the logical address range of 300KB-304KB (none) in the metadata of the buffer unit 920, the status is "occupied", and records that the 1 st buffer subunit 922 is written with data. And reading data from the logical address range (301KB-304KB (not contained)) corresponding to the cache subunits (924, 926 and 928) to which data is not written.

Referring to FIG. 9C, in response to receiving write command W5, the logical address it accesses is located in 2KB of space starting at 201 KB. By looking up the logical address of the cache unit, the logical address range of the cache unit 910 is found to cover the logical address range accessed by the write command W5. Since cache unit 910 is in the "busy" state and

cache subunits

914 and 916 have not yet been written with data, the data to be written by write command W5 is written into

cache subunits

914 and 916 of cache unit 910. The state of cache unit 910 is still "occupied" and

tag cache subunits

912, 914, and 916 are written with data.

It should be understood that, when it is described in this application that a certain cache unit is in an "occupied" state, it indicates that at least one cache subunit in the cache unit is occupied, but at this time, other cache subunits not written with data may also exist in the cache unit, and these cache subunits not written with data may still be used to carry data from a write command.

After write command W5 writes data to the cache molecule, a message may be issued to indicate that the cache molecule is in an "occupied" state and/or occupied location, particularly a location newly occupied by write command W5 (e.g., cache subunits 914 and 916). It will be appreciated that the message may not be sent to the host.

Next, referring to FIG. 9D, data is received that is read from the NVM for a logical address range of 201KB-204KB (not included). Since the

sub-buffer units

914 and 916 corresponding to the 2KB space from the logical address range 201KB are written with data from the write command W5, the read data corresponding to this address range will be discarded. And writes data read from logical addresses 203KB-204KB (none) to buffer subunit 918.

In response to all buffer subunits of the buffer unit 910 being filled with data (data from a write command and/or data read from a corresponding logical address range), the logical address range 200KB-204KB (not included) is completely written with the data of the buffer unit 910, and the state of the buffer unit 910 that is in the process of this writing is set to "busy".

Similarly, for the buffer unit 920, in response to receiving data read from the logical address range 301KB-304KB (not inclusive) and writing to a buffer sub-unit in the buffer unit 920 to which data is not written (924/926/928), the logical address 300KB-304KB (not inclusive) is written with the complete data of the buffer unit 920, and the state of the buffer unit 920 in the write process is set to "busy".

Next, with continued reference to FIG. 9D, in response to receiving the write command W6, the query cache unit finds that the logical address range in the metadata of cache unit 910 covers the logical address of the write command W6, but suspends processing of the write command W6 because cache unit 910 is in a "BUSY" state. And optionally, after the status of the buffer unit 910 changes from the busy state to the idle state, the write command W6 is processed again.

Referring to fig. 9E, in response to completion of the process of completely writing the data of the cache unit 910 into the logical address range 200KB to 204KB (not inclusive), the state of the cache unit 910 is changed from "busy" to "free". Similarly, in response to completion of the process of completely writing the data of the buffer unit 920 into the logical address range 300KB to 304KB (not inclusive), the state of the buffer unit 920 changes from "busy" to "free".

Example 4

According to embodiment 4 of the present invention, the plurality of cache units are divided into two groups. Each group includes one or more cache molecules. One set receives only the data of the write command and the other set is used only for handling the flush operation. This will avoid data from the write command colliding with data from the NVM on the buffer unit, advantageously increasing write command processing speed.

FIG. 10 is a flowchart of a method of processing a write command to write data to an NVM according to embodiment 4 of the present invention. As shown in fig. 10, the method includes the operations of: in operation S1010, a write command is received; in operation S1020, in response to data corresponding to the write command being written into the first portion of the first cache unit belonging to the first group, sending a message indicating that the write command processing is completed to the host; and, in operation S1030, writing data of at least a second buffer cell belonging to the second group to the NVM.

A group may have two states: a "working" state and a "switching" state. Table 3 is a state transition table of the cache units in the group in the "working" state. Table 4 is a state transition table of the cache units in the group in the "swap" state.

The buffer cells of the group in the "active" state are only used to carry data of the write command. In other words, the data corresponding to the write command is written only to the buffer cells belonging to the group in the "working" state. While only a flush operation occurs on the cache elements of the group in the "swap" state. In the flushing operation, for the buffer units in the group in the "swap" state, data is read out from the NVM according to the logical address range of the buffer subunit to which data is not written, and the read data is filled into the corresponding buffer subunit. For a buffer unit in a group in the "swap" state, to which all buffer subunits are written with data (whether data of a write command or data read from the NVM), the data of the buffer unit is written to the NVM as a whole.

All the cache units in the group in the "swap" state do not carry write commands, and all the cache units in the group of memory units in the "working" state do not carry a task (flushing task) of writing the data of the cache units into the NVM. Therefore, when the 'small-write' command is processed, the processes of reading data from the NVM and writing spliced data into the NVM are not required to be waited, and the processing of the 'small-write' command is further accelerated.

Referring to table 3, a cache unit in a group that is in the "working" state may be in the "idle" state or the "occupied" state. A cache molecule in an "idle" state may be allocated to respond to a write command. In response to data of a write command being written to the cache subunit, the cache unit changes from an "idle" state to an "occupied" state. In response to data of the write command being written to the cache unit, an Acknowledgement (ACK) message is generated to indicate to the host that write command processing is complete. And also recording the cache subunit to which the data is written in the metadata of the cache unit.

A cache molecule in an "occupied" state may also respond to write commands. If the write command hits a cache location that is in an "occupied" state, an Acknowledgement (ACK) message is generated to indicate to the host that the write command processing is complete in response to the write command data being written to the hit cache location, and the cache location remains in the "occupied" state. And also recording the cache subunit to which the data is written in the metadata of the cache unit.

TABLE 3

Referring to table 4, a cache unit in a group in the "swap" state may be in the "idle" state or the "busy" state.

In response to the cache unit entering the group in the exchange state, the cache unit in the idle state does not need to perform any operation, and the cache unit in the occupation state initiates an emptying operation to write all data in the cache unit to a logical address range indicated by the metadata of the cache unit. Specifically, if all the cache subunits in the cache unit are occupied, the complete data in the cache unit is directly written into the logical address range indicated by the metadata. If part of the cache subunits in the cache unit are unoccupied, reading data from the logic address corresponding to the unoccupied cache subunits to fill the unoccupied cache subunits. And after all the unoccupied cache subunits of the cache unit are filled with data, writing the complete data in the cache unit into the logical address range indicated by the metadata. And the buffer unit changes from the occupied state to the idle state.

Group status	Current state	Inputting events	Outputting events	Next state
					"exchange" state	Free up	(none)	(none)	Free up
"exchange" state	Occupancy	Emptying	(none)	Free up

TABLE 4

In a given case, the cache units in the group in the "active" state are set to be in the group in the "swapped" state, and/or the cache units in the group in the "swapped" state may be set to be in the group in the "active" state. It is to be understood that such state group transitions may be independent, e.g., a particular buffer unit(s) may be transitioned from a group belonging to a "working" state to a group belonging to a "swap" state, in which case it is not necessarily required that the memory units belonging to the group exchanging the "swap" state are also transitioned to the group belonging to the "working" state. The translations of the two groups may also be related, e.g., the cache units in the two groups may be swapped.

Under specified conditions, the state of the group of memory cells transitions between an "active" state and a "swapped" state. For example, the specified condition may be a certain period of time, i.e., when the period of time expires, a transition of state occurs.

As an example, the specified condition may be that the flushing operation of the cache unit belonging to the group in the "swap" state is completed. Once the flush operation for a cache location is complete, the cache location is converted from a group belonging to the swap state to a group belonging to the "working" state. In another example, after the flushing operation of a certain number or proportion of buffer units is completed, the buffer units are converted from a group belonging to the "swap" state to a group belonging to the "work" state. Alternatively, after the flushing operation of all the buffer units belonging to the group in the "swap" state is completed, the buffer units belonging to the group in the "swap" state may be converted into the group belonging to the "work" state.

In another example, the specified condition is that the amount of data stored in the cache unit in the group belonging to the "active" state reaches a specified threshold.

In still another example, the specified condition is that the number of cache units to which data is written among cache units belonging to a group in the "active" state reaches a specified threshold. This example differs from the above example in that the present example considers the number of buffer units to which data is written, whereas the previous example considers the amount of data written in a buffer unit.

The above-mentioned specified threshold value can be set by those skilled in the art according to practical situations, and the specific size of the specified threshold value does not set any limit to the scope of the present application.

Example 4 is described in detail below with reference to fig. 11A to 11C.

11A-11C illustrate the state of individual buffer cells and the variation of data in buffer subunits for different write commands according to another embodiment of the present invention.

By way of example, there are four write commands (denoted as W7, W8, W9, and W10, respectively). The write command W7 writes 4KB of data to logical address 200KB, the write command W8 writes 1KB of data to logical address 303KB, and the write command W9 writes 1KB of data to logical address 201 KB; w10 writes 4KB of data to logical address 60 KB.

First, as shown in fig. 11A, the cache units 1110 and 1120 belong to a first group and are in a "working" state; the cache unit 1130 and the cache unit 1140 belong to the second group and are in a "swap" state.

In response to receiving the write command W7, the metadata of the cache locations in the first group is queried. Since a logical address range covering the logical address range of the write command W7 is not recorded in the metadata of any cache unit in the first group, the write command W7 misses any cache unit, and allocates, for example, the cache unit 1110 to the write command W7.

In response, the logical address range 200KB-204KB (none) is marked in the metadata of the cache unit 1110. Upon the write command W7 accessing the 4KB space starting at logical address 200KB, the data of the write command W7 is written into the 4 buffer subunits of the buffer unit 1110 (1112/1114/1116/1118). The state of the logical unit 1110 changes from "free" to "occupied" and records that 4 buffer subunits (1112/1114/1116/1118) were written with data.

In response to receiving the write command W8, the metadata of the cache locations in the first group is queried. Since no logical address range covering the logical address range of the write command W8 is recorded in the metadata of any cache unit in the first group, the write command W8 misses any cache unit, and allocates, for example, the cache unit 1220 for the write command W8.

In response, the logical address range 300KB-304KB (none) is marked in the metadata of the cache unit 1120. According to the write command W8, the data of the write command W8 is written into the 4 th buffer sub-unit of the buffer unit 1120 in 1KB space starting from the logical address 303KB (1128). The state of the logic unit 1120 changes from "free" to "occupied" and the record buffer subunit (1128) is written with data.

With continued reference to FIG. 11A, the second group in the "swapped" state includes cache unit 1130 and cache unit 1140. The cache unit 1130 is, for example, in an "occupied" state, with all 4 cache subunits (1132/1134/1136/1138) being written with data, and having a logical address range of 100K-104K (none). In response to the second group entering the "swap" state, the data of the cache unit 1130 is completely written into the 4K logical address space starting at logical address 100K.

The buffer unit 1140 is in an "occupied" state, in which only the buffer subunit 1142 is written with data. The logical address range of cache unit 1140 is 20KB-24KB (not included). In response to the second group entering the "swap" state, the data in cache cell 1140 is to be written to NVM. Since only the buffer subunit 1142 is written with data, a read request is issued to the logical address range (21KB to 24KB (not inclusive)) corresponding to the other buffer subunits 1144/1146/1148, and the read data is filled in the corresponding buffer subunit 1144/1146/1148. During this time, buffer unit 1140 remains in the "busy" state.

After all the buffer subunits of the buffer unit 1140 are filled with data, the data of the buffer unit 1140 is completely written into the NVM.

FIG. 11B illustrates the receipt of a write command W9. In response to receiving the write command W9, the metadata of the cache locations in the first group is queried. Since the logical address 200KB (not including) 204KB recorded in the metadata of the cache unit 1110 includes the logical address range accessed by the write command W9, the write command W9 hits the cache unit 1110. The data to be written by the write command W9 is written to the buffer subunit 1114 of the buffer unit 1110 (data of the write command W7 is overwritten). And record in the metadata that the cache subunit 1114 is written with data, the cache unit 1110 is still in an "occupied" state. Alternatively, since the buffer subunit 1114 has already been written with data in response to the write command W9, it may not be necessary to repeatedly record that the buffer subunit 1114 has already been written with data.

In yet another embodiment of the present invention, since there was previously data written by the write command W7 in the buffer subunit 1114, the logical address accessed by the write command W9 overlaps with the logical address range accessed by the write command W7, and in response, a new buffer unit is allocated for the write command W9 from the first group. If no new cache location is available, processing of write command W9 is suspended until a new cache location is allocated for write command W9.

Although it is shown above that data has been written in the cache subunit of the cache unit hit by the write command W9, there may be a case where no data exists in the cache subunit of the cache unit hit by the write command. In other words, if the logical address range accessed by the subsequent write command does not overlap with the logical address range accessed by the previous write command, the data of the subsequent write command can be directly written into the corresponding cache subunit of the hit cache unit.

For the buffer locations 1130 and 1140 belonging to the second group, in response to the data in the buffer locations 1130 and 1140 being written to the NVM or the buffer locations 1130 and 1140 being emptied, the state of the buffer location 1130/1140 is changed from "occupied" to "free", and optionally the information about the buffer sub-locations to which the data is written is cleared.

Referring to fig. 11C, in response to the states of the buffer units in the second group all becoming "idle", the first group is "swapped" with the second group, the first group becomes in the "swapped" state, and the second group becomes in the "active" state. Optionally, the state of the first group is not dependent on the state or state change of the second group, i.e. the states of the first and second groups are independent of each other, which has been described in detail above.

After the swap, the write command is carried by cache molecule 1130/1140 since the second group is in the "active" state. In response to receiving the write command W10 (fig. 11C), the metadata of the cache location in the second group is queried. Since the cache units in the second group are all in an idle state, the metadata of any cache unit in the second group does not record a logical address range covering the logical address range of the write command W10, and thus the write command W10 misses any cache unit and allocates a cache unit 1130 for the write command W10. In response, the logical address range 60KB-64KB (none) is marked in the metadata of cache unit 1130. Upon the write command W10 accessing the 4KB space starting at logical address 60KB, the data of the write command W10 is written into the 4 buffer subunits of the buffer unit 1130 (1132/1134/1136/1138). The state of logical unit 1130 changes from "free" to "occupied" and records that 4 buffer subunits (1132/1134/1136/1138) were written with data.

In response to the first group becoming in the "swap" state, a flush operation is initiated with cache unit 1110 and cache unit 1120, writing data therein to NVM. Since the buffer subunits of the buffer unit 1110 are all written with data, the data of the buffer unit 1110 is entirely written into the 4KB space starting from the logical address 200 KB. Since only cache subunit 1128 of cache unit 1120 is written with data, the data is read from the logical address range (300KB-303KB (not included)) corresponding to the unoccupied cache subunit (1122/1124/1126), and fills the cache subunit that is not written with data (1122/1124/1126). And after all the buffer subunits of the buffer unit 1120 are written with data, the data of the buffer unit 1120 is entirely written into the 4KB space of the logical address range (300KB-304KB (not included)).

In the embodiments of the present application, there may be various ways to determine the number of buffer units in the first group and the second group, for example, the number of buffer units in the first group and the second group may be divided equally, or the number of buffer units in each group may be determined according to a specific ratio.

According to one embodiment, the number of buffer cells in the first and second groups is determined according to a ratio of a processing duration of a write operation to a processing duration of a read operation. For example, if the average processing duration of one write command is T1, the average number of write commands is N1, the average processing duration of one read command is T2, and the average number of read commands is N2, in order to maintain the balance between reading and writing, the average processing duration of one write command is T1 × N1: t2 × N2 determines the ratio of the number of buffer cells in the first group to the second group.

It should be understood that the above-mentioned manner for determining the number of buffer units in the first group and the second group is only exemplary, and those skilled in the art can determine the ratio in any suitable manner, and the practical examples provided in the present disclosure do not set any limit to the scope of the present application.

The methods and apparatus of the present invention may be implemented in hardware, software, firmware, or any combination thereof. The hardware may include digital circuitry, analog circuitry, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), and so forth. The software may be recorded in a computer-readable storage medium, which, when executed by a processor, implements the methods provided by embodiments of the present application.

For example, the invention may be implemented in a controller, which may include: one or more processors; a memory; a program stored in the memory, which when executed by the one or more processors, causes the method provided by embodiments of the present application to be performed therein.

The software of the present invention can also be stored in a computer-readable storage medium, such as a hard disk, an optical disk, etc., which stores a program that, when executed by a device, causes the device to perform the methods provided by the embodiments of the present application.

The foregoing description is merely exemplary rather than exhaustive of the present invention, and those skilled in the art may add, delete, modify, replace, etc. the above methods, apparatuses, devices, modules, etc. without departing from the spirit and scope of the present invention.

Claims

1. A method of processing a write command to write data to an NVM, wherein a cache unit is provided, the cache unit comprising a first portion and a second portion, the method comprising:

receiving a first write command;

responding to the first part of the cache unit written with the data corresponding to the first write command, and sending a first message indicating the completion of the processing of the first write command to the host;

and under the condition that the first write command hits the cache unit, if the logical address range accessed by the first write command is not overlapped with the logical address range of the data contained in the hit cache unit, writing the data corresponding to the first write command into the cache unit.

2. The method of claim 1, further comprising:

detecting whether the first write command hits in a cache unit,

and if the first write command hits the cache unit, writing data into the hit cache unit.

3. Method according to one of claims 1-2, wherein in case of a hit of the first write command to the cache location, if the logical address range accessed by the first write command overlaps with the logical address range of the data contained in the hit cache location, then

Waiting for emptying the cache unit;

and writing the data corresponding to the first write command into the emptied cache unit.

4. A method of processing a write command to write data to an NVM, wherein a plurality of buffer units are provided, each buffer unit comprising a first portion and a second portion, and the plurality of buffer units are divided into a first group and a second group, the method comprising:

in response to data corresponding to the first write command being written into a first portion of a first cache unit belonging to the first group, sending a first message to the host indicating that processing of the first write command is complete; and

writing data of at least a second cache unit belonging to the second group to the NVM;

the method further comprises:

receiving a second write command;

and if the second write command hits the first cache unit, and the logical address range accessed by the second write command is not overlapped with the logical address range accessed by the first write command, writing the data corresponding to the second write command into the second part of the first cache unit.

5. The method of claim 4, wherein

Writing data corresponding to the write command into the cache units belonging to the first group only; and

only data of the buffer cells belonging to the second group is written to the NVM.

6. The method of one of claims 4-5, further comprising:

if the second write command hits the first cache unit, and the logical address range accessed by the second write command overlaps with the logical address range accessed by the first write command, suspending the processing of the second write command until a third cache unit belonging to the first group is allocated to the second write command; and

and writing the data corresponding to the second command into the third cache unit.

7. A processor that processes a write command to write data to an NVM, comprising:

one or more processors;

a memory;

a program stored in the memory, which when executed by the one or more processors, causes the processors to perform the method of any one of claims 1-6.

8. An apparatus for processing a write command to write data to an NVM, wherein a cache unit is provided, the cache unit comprising a first portion and a second portion, the apparatus comprising:

means for receiving a first write command;

means for sending a first message to a host indicating that processing of a first write command is complete in response to data corresponding to the first write command being written to a first portion of a cache unit; and under the condition that the first write command hits the cache unit, if the logical address range accessed by the first write command is not overlapped with the logical address range of the data contained in the hit cache unit, writing the data corresponding to the first write command into the cache unit.