CN110928482A

CN110928482A - Partial page stripes and memory devices using the same and methods thereof

Info

Publication number: CN110928482A
Application number: CN201811095376.XA
Authority: CN
Inventors: 路向峰; 孙清涛; 袁戎; 刘玉进
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2018-09-19
Filing date: 2018-09-19
Publication date: 2020-03-27

Abstract

Partial page stripes and memory devices using partial page stripes and methods thereof are provided. A method for a storage device is provided, comprising: obtaining a first portion of user data to be written to a first page stripe; generating first check data of a first page stripe according to the first part of the user data; writing a first portion of the user data to a first page stripe.

Description

Partial page stripes and memory devices using the same and methods thereof

Technical Field

The present application relates to Storage devices (SSDs), and more particularly, to managing data written to a non-volatile Storage medium of a Storage Device with partial page stripes.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (small computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (universal Serial Bus), PCIE (Peripheral component Interconnect Express), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The storage device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DR AM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRA (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (application specific integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to an interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

The memory Target (Target) is one or more Logic units (Logic units) of a shared Chip Enable (CE) signal within the package of the flash memory pellet 105, each Logic Unit having a Logic Unit Number (LUN). One or more dies (Die) may be included within the NAND flash memory package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other. In "Open NAND Flash InterfaceSpecification (Revision 3.2)" obtained at http:// www.onfi.org// media/ONFI/specs/ONFI-3-2% 20gold. pdf, the meaning for target (target), logical unit, LUN, Plane (Plane) is provided, and the commands to operate the NVM chip are also provided.

Data is typically stored and read on a storage medium on a page-by-page basis. And data is erased in blocks. A block contains a plurality of pages. Pages on the storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. Physical pages may also have other sizes. The physical page may include a plurality of data frames (data frames) therein, the data frames having a specified size, e.g., 4096 or 4416 bytes.

In the storage device, mapping information from logical addresses to physical addresses is maintained by using a Flash Translation Layer (FTL). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented in the prior art using an intermediate address modality. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address. A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices.

Memory device 102 includes a plurality of NVM chips 105 therein. Each NVM chip includes one or more DIEs (DIE) or Logical Units (LUNs). The dies or logic units can respond to read and write operations in parallel. Multiple read, write, or erase operations are performed sequentially on the same die or logic.

FIG. 2 shows a schematic diagram of a chunk and page stripe. A large block includes physical blocks from multiple logical units. Preferably, each logical unit provides one physical block for a large block. By way of example, large blocks are constructed on every 16 Logical Units (LUNs). Each large block includes 16 physical blocks, from each of 16 Logical Units (LUNs). In that

In the example of FIG. 2, chunk 0 includes physical block 0 from each of the 8 Logical Units (LUNs), and chunk 1 includes physical block 1 from each Logical Unit (LUN). There are many other ways to construct the bulk mass.

As an alternative, page stripes are constructed in large blocks, with physical pages of the same physical address within each Logical Unit (LUN) constituting a "page stripe". In FIG. 2, physical pages P0-0, P0-1 … …, and P0-7 of chunk 0 constitute page stripe 0, where physical pages P0-0, P0-1 … …, physical pages P0-6 are used to store user data, and physical pages 0-7 are used to store parity data computed from all user data within the stripe. Similarly, in FIG. 2, physical pages P2-0, P2-1 … …, and P2-7 of chunk 0 constitute page strip 2. Alternatively, the physical page used to store parity data may be located anywhere in the page stripe.

To write data to the page stripe, a control component (104) of the storage device (see FIG. 1) provides a check data calculator. Taking the example of computing parity data using an exclusive-OR operation, for a page stripe including N +1 physical pages, exclusive-OR is computed for user data of the N physical pages (e.g., (P0-0) XOR (P0-1) XOR (P0-2) XOR … XOR (P0- (N-1))), and the computed result is written as a physical page (e.g., P0-N) where the page stripe stores parity data. Optionally, a plurality of check data calculators (e.g., M) are provided in the control unit (104) to write data to M page stripes simultaneously. The check data calculator records the intermediate result of the check data using a buffer (e.g., an XOR buffer).

Disclosure of Invention

The page stripe includes a plurality of physical pages and a large amount of user data. To calculate the check data of a page stripe, all user data of the page stripe is used for calculation, and the cache of the check data calculator is occupied for a long time. Before the user data is written into the NVM storage medium, it is also necessary to protect the security of the user data, so as to avoid data loss caused by unexpected events such as power failure. The large data size of the page stripes increases the overhead for securing user data, and also results in low utilization of the cache of the check data calculator.

According to embodiments of the present application, a page stripe is divided into two or more portions (referred to as partial page stripes) and data is written to an NVM chip using the partial page stripes. Thus the data of the stripe is written to the NVM chip through multiple operations, each time writing data of a partial page stripe. After partial page stripes are written into the NVM chip, the cache of the check data calculator is redistributed, and the utilization rate of the cache of the check data calculator is improved. Alternatively or additionally, to avoid data loss caused by unexpected events such as power failure, for example, a backup power supply is only required to support protection of partial page stripe data, thereby reducing resources for protecting user data security and further reducing cost. Also, the ratio of the check data to the user data of the page stripe is maintained at a low level.

According to a first aspect of the present application, there is provided a method for a storage device according to the first aspect of the present application, comprising: obtaining a first portion of user data to be written to a first page stripe; generating first check data of a first page stripe according to the first part of the user data; writing a first portion of the user data to a first page stripe.

According to a first method for a storage device of the first aspect of the present application, there is provided a second method for a storage device of the first aspect of the present application, further comprising: obtaining a second portion of user data to be written to the first page stripe;

generating second parity data of the first page stripe according to the first parity data and the second part of the user data; and writing a second portion of the user data and the second parity data to a first page stripe.

The first or second method for a storage device according to the first aspect of the present application provides a third method for a storage device according to the first aspect of the present application, wherein the first and second portions of user data constitute all user data of the first page stripe.

According to one of the first to third methods for a storage device of the first aspect of the present application, there is provided the fourth method for a storage device of the first aspect of the present application, wherein the first parity data is moved to an external memory in response to generation of the first parity data.

According to a fourth method for a storage device of the first aspect of the present application, there is provided a fifth method for a storage device of the first aspect of the present application, further comprising: obtaining a first portion of user data to be written to a second page stripe; in response to moving the first parity data of the first page stripe to the external memory, first parity data of a second page stripe is generated from a first portion of user data to be written to the second page stripe.

According to a fourth or fifth method for a storage device of the first aspect of the present application, there is provided a sixth method for a storage device according to the first aspect of the present application, further comprising: first parity data of the first page stripe is retrieved from an external memory to generate second parity data of the first page stripe from the first parity data and the second portion of the user data.

According to a fifth or sixth method for a storage device of the first aspect of the present application, there is provided the seventh method for a storage device of the first aspect of the present application, wherein the first parity data of the first page stripe and the first parity data of the second page stripe are generated using the same hardware resources.

According to one of the fifth to seventh methods for a memory device of the first aspect of the present application, there is provided the eighth method for a memory device of the first aspect of the present application, wherein the first page stripe and the second page stripe are coupled to the same channel.

According to one of the first to eighth methods for a storage device of the first aspect of the present application, there is provided the ninth method for a storage device of the first aspect of the present application, wherein the first portion of the user data to be written to the first page stripe is written to the first W page of the first page stripe; and a second portion of said user data to be written to the first page stripe and second parity data for the first page stripe, written to a second W page of the first page stripe; where the first W page does not include the parity data for the first page stripe.

According to a ninth method for a storage device of the first aspect of the present application, there is provided the tenth method for a storage device of the first aspect of the present application, wherein the second portion of the user data to be written to the first page stripe is acquired in response to completion of the first W page operation of writing the first portion of the user data to the first page stripe.

According to one of the fourth to eighth methods for a storage device of the first aspect of the present application, there is provided the eleventh method for a storage device of the first aspect of the present application, wherein the first portion of user data to be written to the third page stripe is obtained; in response to moving the first parity data of the second page stripe to the external memory, first parity data of a third page stripe is generated from a first portion of user data to be written to the third page stripe.

A method for a storage device according to an eleventh aspect of the present application provides the method for a storage device according to the twelfth aspect of the present application, further comprising: in response to completion of a first W-page operation to write a first portion of user data to be written to a third page stripe, first parity data for the first page stripe is retrieved from external memory to generate second parity data for the first page stripe from the first parity data and a second portion of the user data.

According to the first method for a storage device of the first aspect of the present application, there is provided the thirteenth method for a storage device of the first aspect of the present application, further comprising: obtaining a second portion of user data to be written to the first page stripe; generating second check data of the first page stripe according to the first check data of the first page stripe and the second part of the user data; and writing a second portion of the user data to the first page stripe.

According to a thirteenth method for a storage device of the first aspect of the present application, there is provided the fourteenth method for a storage device of the first aspect of the present application, further comprising: first parity data of the first page stripe is retrieved from an external memory to generate second parity data of the first page stripe from the first parity data and the second portion of the user data.

According to a thirteenth or fourteenth method for a storage device of the first aspect of the present application, there is provided the fifteenth method for a storage device of the first aspect of the present application, further comprising: obtaining a third portion of user data to be written to the first page stripe; generating third check data of the first page stripe according to the second check data of the first page stripe and the third part of the user data; and writing the third portion of the user data and third parity data of the first page stripe to the first page stripe.

According to a fifteenth method for a storage device of the first aspect of the present application, there is provided the sixteenth method for a storage device of the first aspect of the present application, further comprising: second parity data for the first page stripe is retrieved from external memory to generate third parity data for the first page stripe from the second parity data and a third portion of the user data.

According to a second aspect of the present application, there is provided a first memory device according to the second aspect of the present application, comprising a control means and an NVM chip, the control means performing one of the methods for a memory device according to the first aspect of the present application.

Drawings

The application, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a prior art memory device;

FIG. 2 shows a schematic diagram of a chunk and page stripe;

FIG. 3 illustrates a partial page stripe in accordance with an embodiment of the present application;

FIG. 4 illustrates a block diagram of a storage device according to an embodiment of the present application;

FIG. 5A illustrates a timing diagram according to an embodiment of the present application;

FIG. 5B illustrates a schematic diagram of a page stripe according to an embodiment of the present application;

FIG. 6A illustrates a timing diagram according to yet another embodiment of the present application;

FIG. 6B shows a schematic diagram of a page stripe according to yet another embodiment of the present application

FIG. 6C illustrates a timing diagram according to yet another embodiment of the present application;

FIG. 6D illustrates a timing diagram according to still another embodiment of the present application; and

FIG. 7 illustrates a flow diagram according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

FIG. 3 illustrates a partial page stripe in accordance with an embodiment of the present application.

For purposes of clarity, a partial page strip is referred to as a W page.

Referring to fig. 3, a large block is constructed on logic unit 0 through logic unit 7. For example, chunk 0 includes physical block 0 from each of logical unit 0 through logical unit 7. A page stripe is constructed on the large block. For example, page stripe 0 includes physical pages P0-0, P0-1 … …, and P0-7 of chunk 0, where physical pages P0-0, P0-1 … …, P0-6 are used to store user data, and physical pages 0-7 are used to store parity data computed from all user data within stripe 0.

In the example of fig. 3, the page stripe includes 2W pages. It is understood that in embodiments according to the present application, the page strip includes other numbers of W pages. And allocating the cache of the check data calculator for the W pages. In response to writing the W pages of data to the NVM chip, the allocated cache for the W pages may be released.

With continued reference to FIG. 3, page stripe 0 includes W page 0 and W page 1. W page 0 includes physical page P0-0, physical page P0-1, physical page P0-2, and physical page P0-3 of chunk 0, and W page 1 includes physical page P0-4, physical page P0-5, physical page P0-6, and physical page P07 of chunk 0. All recorded by W page 0 are user data of page stripe 0 without parity data, physical pages P0-4, P0-5, and P0-6 of W page 1 record user data of page stripe 0, and physical pages P0-7 record parity data of page stripe 0. Alternatively, the parity data of the page stripe is recorded in other physical pages of the page stripe (not the last physical page), and the parity data may be recorded in either W page 1 or W page 0.

Still alternatively, the plurality of W pages constituting the same page stripe may have different sizes. For example, the page stripe includes 8 physical pages, and W page 0 constituting the page stripe includes 3 physical pages, and W1 constituting the page stripe includes 5 physical pages.

FIG. 4 illustrates a block diagram of a memory device in accordance with an embodiment of the present application.

The control components of the memory device are coupled to the plurality of NVM chips 105 through a plurality of channels (452, 454, 456, 458). Each channel couples multiple NVM chips.

By way of example, NVM chips each provide a logic cell. The physical blocks of logical units from each of the plurality of lanes (452, 454, 456, 458) constitute a large block. The page stripe on the chunk includes W pages 0 and W pages 1. The physical page of Wpage 0 is from an NVM chip coupled to channel 452 and channel 454. The physical page of Wpage 1 is from an NVM chip coupled to channel 456 and channel 458. Still by way of example, W page 1 stores parity data for the stripe of pages in which it resides, while W page 0 stores no parity data.

The control section of the storage apparatus includes an interface 103, a command processing section 420, and a media interface 410.

Command processing component 420 obtains IO commands from interface 103, e.g., provided by a host, provides logical address to physical address mapping, wear leveling, garbage collection, etc., and generates IO operations that are sent to media interface 410. Media interface 410 is coupled to NVM chip 105 through a plurality of channels. The media interface 410 receives the IO operations and issues commands to the NVM chip to read, program, erase, suspend, read feature (feature) and/or set feature according to the IO operations.

The media interface 410 further comprises a check data calculator for calculating check data from the user data of the page stripes. The check data calculator includes, for example, a plurality of XOR caches (422, 424, 426, 428). The XOR buffer is used to store intermediate or final results of the check data computed for the page stripe. The check data calculator is also coupled to the DRAM. The data recorded by the XOR cache may be stored to the DRAM and the data stored by the DRAM may be stored to the XOR cache.

According to an embodiment of the application, the XOR cache is allocated/released by W pages. By way of example, W page 0 and W page 1 together comprise a page stripe, while W page 0 does not include parity data for the page stripe and W page 1 includes parity data for the page stripe. To write data to W page 0, an XOR buffer (e.g., XOR buffer 428) is allocated, a program command is sent to each NVM chip where W page 0 is located, and the results of an exclusive or (XOR) calculation of the data of each physical page of W page 0 are recorded in the XOR buffer. In response to W page 0 being written with data, the data recorded in XOR cache 428 is stored to DRAM. So that XOR cache 428 may be allocated for write operations to other W pages. In response to the data to be written to W page 1, an XOR buffer (e.g., XOR buffer 422) is allocated for W page 1, the data previously generated by XOR buffer 428 for W page 0, recorded in DRAM, is moved to XOR buffer 422, the data of XOR buffer 422 is xored with the respective user data to be written to W page 1, and the final result is written to W page 1 as the check data of W page 1 (also the check data of the page stripe to which W page 1 and W page 0 belong), and XOR buffer 422 is released. At this time, since the page stripes to which W page 0 and W page 1 belong are written to completion, the data of the XOR cache 422 does not need to be saved to the DRAM.

FIG. 5A shows a timing diagram according to an embodiment of the present application. In fig. 5A, the direction to the right represents the direction in which time elapses.

FIG. 5B shows a schematic diagram of a page stripe according to an embodiment of the present application.

Referring to fig. 5B, a large block is constructed on logic unit 0 through logic unit 3. The large block includes page stripe 0, page stripe 1, page stripe 2, and page stripe 3. Physical pages are indicated by reference numerals in the form of Sa-b-c, the letter a indicates the page band to which the physical page belongs, the letter b indicates the W page to which the physical page belongs, and the letter c indicates the serial number of the physical page within the W page. For example, physical pages S0-0-0 indicates physical page number 0 of W page 0 of page stripe 0, and physical pages S3-1-1 indicates physical page number 1 of W page 1 of page stripe 3. By way of example, a page stripe includes 4 physical pages, 2W pages, each of which includes 2 physical pages. The parity data of the page stripe is recorded in, for example, the second W page (W page 1) of the page stripe. Logic 0 and logic 1 are coupled to channel 452 and logic 2 and logic 3 are coupled to channel 454.

Referring back to FIG. 5A, command processing unit 420 (see also FIG. 4) prepares the data to be written to W page 0 of page stripe 0, allocates XOR cache 424 for the data of W page 0, and provides the data to be written to the various physical pages of W page 0 one by one, for example, to XOR cache 424.

Next, an XOR operation is performed on each physical page data of W page 0 to be written to page stripe 0, and the result of the XOR operation is recorded in XOR cache 424. As the computation of the check data is completed with the respective physical page data to be written to W page 0, the data is written to the physical page belonging to W page 0 via channel 452.

As the data of the last physical page of W page 0 is transferred to W page 0, the data in XOR cache 424 (referred to as intermediate check data) is stored to DRAM so that XOR cache 424 may be allocated for write operations for other W pages. The physical pages of W page 0 of page stripe 0 (S0-0-0 and S0-0-1) to which data is written are hatched with vertical lines in FIG. 5B to distinguish from other physical pages.

In response to command processing unit 420 being ready to write data for W page 1 of page stripe 0, an XOR buffer is allocated for the data for W page 1. By way of example, XOR cache 424 is allocated. The intermediate check data previously stored for W page 0 of page stripe 0 is retrieved from DRAM and written to XOR cache 424. The data to be written to each physical page of W page 1 (user data only) is provided to XOR buffer 424 one by one.

Next, an XOR operation is performed on the user data to be written to W Page 1, and the result of the XOR operation is recorded in cache 424. As an example, user data to be written to W Page 1 occupies only physical pages S0-1-0. As the calculation of the check data from the user data is complete, the user data is written to physical page S0-1-0, which belongs to W Page 1, via channel 454. Next, the data in the XOR buffer (referred to as check data) is written to physical page S0-1-1, which belongs to W Page 1, via channel 454.

With the data of the last physical page S0-1-1 of W Page 1 transferred to the NVM chip providing W Page 1, XOR buffer 424 is freed, and XOR buffer 424 may be allocated for write operations to other W pages. To this end, the physical pages of W Page 1 of Page stripe 0 (S0-1-0 and S0-1-1) are also written with data, shaded with vertical lines in FIG. 5B.

FIG. 6A shows a timing diagram according to yet another embodiment of the present application. In fig. 6A, the direction to the right represents the direction in which time elapses. FIG. 6B shows a schematic diagram of a page stripe according to yet another embodiment of the present application.

Referring to fig. 6B, a large block is constructed on logic unit 0 to logic unit 3, and a large block is constructed on logic unit 4 to logic unit 7. Page stripe 0, page stripe 1, page stripe 2, and page stripe 3 are from a large block of logic cells 0 through 3. Page stripe 4 to page stripe 7 come from a large block of logical units 4 to 7. Logic units 0 through 3 are coupled to channel 452 and logic units 4 through 7 are coupled to channel 454.

Physical pages are indicated by reference numerals in the form of Sa-b-c, the letter a indicates the page band to which the physical page belongs, the letter b indicates the W page to which the physical page belongs, and the letter c indicates the serial number of the physical page within the W page. By way of example, a page stripe includes 4 physical pages, 2W pages, each of which includes 2 physical pages. The parity data of the page stripe is recorded, for example, at the 2 nd W page of the page stripe.

W pages are indicated by reference numerals in the form of We-f, where e indicates the page band to which the W page belongs and f indicates the serial number of the W page in the page band.

Referring back to FIG. 6A, command processing unit 420 (see also FIG. 4) prepares the data to be written to W pages 0-0 of page stripe 0, allocates XOR buffers 424 for the data of W pages 0-0, and provides the data to be written to the various physical pages of W pages 0-0 one by one, e.g., to XOR buffers 424.

Next, an XOR operation is performed on the data to be written into W pages 0-0, and the result of the XOR operation is recorded in cache 424. As the calculation of the parity data with the data of each physical page is completed, the data of each physical page is written to the physical page belonging to W pages 0-0 through channel 452 (S0-0-0 and S0-0-1).

As the data of the last physical page of W pages 0-0 is transferred to W pages 0-0, the data in XOR buffer 424 (referred to as intermediate check data) is stored to DRAM and XOR buffer 424 is freed. Physical pages of W pages 0-0 (S0-0-0 and S0-0-1) of page stripe 0 to which data is written are hatched in FIG. 6B to distinguish from other physical pages.

During writing data to the physical pages of Wpages 0-0 (S0-0-0 and S0-0-1), channel 452 is occupied. While W pages 4-0 are coupled to channel 454, data can be written to W pages 4-0 simultaneously during the writing of data to W pages 0-0. Thus, in response to channel 452 being occupied, command processing unit 420 prepares data to be written to W page 4-0 of page stripe 4 of unoccupied channel 454.

In response to command processing unit 420 being ready to write data for W page 4-0, an XOR buffer is allocated for the data for W page 4-0. By way of example, XOR cache 424 is allocated. The data to be written to each of the physical pages of W pages 4-0 is provided to XOR cache 424 one by one. As the computation of the parity data with the data of each physical page is completed, the data of each physical page is written to the physical page belonging to W page 4-0 through channel 454 (S4-0-0 and S4-0-1).

With the data of the last physical page of W page 4-0 transferred to the NVM chip providing W page 4-0, the data in XOR cache 424 (referred to as intermediate check data) is stored to DRAM, and XOR cache 424 is freed. The physical pages of W page 4-0 (S4-0-0 and S4-0-1) of the page stripe 4 to which data is written are hatched with vertical lines in FIG. 6B.

Next, the operation of writing data to the physical page of W pages 0-0 (S0-0-0 and S0-0-1) is about to complete or has been completed. The command processing unit 420 prepares data of another W page (W pages 0-1) to be written to the page stripe 0 to which data has been partially written.

In response to command processing unit 420 being ready to write data for W pages 0-1, XOR buffer 424 is allocated for W pages 0-1. Intermediate check data previously stored for W pages 0-0 are retrieved from DRAM and written to XOR cache 424. Data to be written to each of the physical pages of W pages 0-1 is provided to XOR cache 424 one by one.

Next, an XOR operation is performed on the intermediate parity data and the user data to be written to W pages 0-1, and the result of the XOR operation is recorded in cache 424. As an example, user data to be written to W pages 0-1 only occupies physical pages S0-1-0. As the computation of the parity data from the user data is complete, the user data is written to physical page S0-1-0, which belongs to W page 0-1, via channel 452. Next, the data in the XOR buffer (referred to as check data) is written to physical page S0-1-1, which belongs to W page 0-1, via channel 452.

With the data of the last physical page S0-1-1 of W pages 0-1 transferred to the NVM chip providing W pages 0-1, XOR buffer 424 is freed, and XOR buffer 424 may be allocated for write operations of other W pages. To this end, the physical pages of W pages 0-1 of page stripe 0 (S0-1-0 and S0-1-1) are also written with data, hatched with vertical lines in FIG. 6B.

Next, the operation of writing data to the physical page of W pages 4-0 (S4-0-0 and S4-0-1) is about to complete or has been completed. The command processing unit 420 prepares data to be written to another W page (W page 4-1) of the page stripe 4 to which data has been partially written.

In response to command processing unit 420 being ready to write data for W page 4-1, XOR buffer 424 is allocated for the data for W page 4-1. Intermediate check data previously stored for W pages 4-0 is retrieved from DRAM and written to XOR cache 424. User data to be written to W page 4-1 is provided to XOR cache 424.

Next, an XOR operation is performed on the user data to be written to W page 4-1, and the result of the XOR operation is recorded in cache 424. As an example, user data to be written to W page 4-1 occupies only physical page S4-1-0. As the calculation of the check data from the user data is complete, the user data is written to physical page S4-1-0 belonging to W page 4-1 via channel 454. Next, the check data in the XOR buffer is written to physical page S4-1-1, which belongs to W page 4-1, via channel 454.

With the data of the last physical page S4-1-1 of W page 4-1 transferred to the NVM chip providing W page 4-1, XOR buffer 424 is freed, and XOR buffer 424 may be allocated for write operations of other W pages. To this end, the physical pages (S4-1-0 and S4-1-1) of W page 4-1 of page stripe 4 are also written with data, hatched with vertical lines in FIG. 6B.

FIG. 6C shows a timing diagram according to yet another embodiment of the present application.

Wpages 0-0 and 0-1 of page stripe 0 are provided by logic coupled to channel 452, and Wpages 4-0 and 4-1 of page stripe 4 are provided by logic coupled to channel 454. Parity data is computed for page stripe 0 and page stripe 4 using both XOR cache 424 and XOR cache 426.

Command processing unit 420 (see also FIG. 4) prepares the data to be written to W pages 0-0 of page stripe 0, allocates XOR buffers 424 for the data of W pages 0-0, and provides the data to be written to the various physical pages of W pages 0-0 one by one, for example, to XOR buffers 424. The result of the XOR operation is recorded in cache 424. The data for each physical page is written to the physical pages belonging to W pages 0-0 through channel 452.

During calculation of the intermediate check data by XOR buffer 424 for W pages 0-0, command processing unit 420 prepares the data to be written to W pages 4-0 of page stripe 4, allocates XOR buffer 426 for the data of W pages 4-0, and provides the data to be written to the various physical pages of W pages 4-0 to XOR buffer 426 one by one. The result of the XOR operation is recorded in buffer 426. The data for each physical page is written to the physical pages belonging to W pages 4-0 through channel 454. The write data to W pages 0-0 is processed in parallel with the write data to W pages 4-0.

Command processing unit 420 continues to prepare data to be written to W pages 0-1 of page stripe 0. XOR cache 424 now records intermediate check results generated from W pages 0-0. Since W pages 0-1 belong to the same page stripe as W pages 0-0, XOR buffer 424 is allocated for W pages 0-1, eliminating the process of moving intermediate check results recorded by XOR buffer 424 to DRAM.

User data to be written to W pages 0-1 is provided to XOR cache 424. The result of the XOR operation is recorded in cache 424. As the computation of the check data with the user data of each physical page is complete, the data of each physical page is written to the physical pages belonging to W pages 0-1 via channel 452. The check data recorded by XOR cache 424 is also written to physical pages belonging to W pages 0-1.

The command processing unit 420 continues to prepare data to be written to W page 4-1 of the page stripe 4. The XOR cache 426 now records the intermediate check result generated from W page 4-0. Since W page 4-1 belongs to the same page stripe 4 as W page 4-0, XOR cache 426 is allocated for W page 4-1, eliminating the process of moving intermediate check results recorded by XOR cache 426 to DRAM.

User data to be written to W page 4-1 is provided to XOR cache 426. The result of the XOR operation is recorded in buffer 426. As the computation of the check data with the user data of each physical page is complete, the data of the physical page is written to the physical page belonging to W page 4-1 via channel 454. The check data recorded by XOR buffer 426 is also written to the physical page belonging to W page 4-1. The write operation to W pages 0-1 and the write operation to W pages 4-1 are processed in parallel.

Fig. 6D shows a timing diagram according to still another embodiment of the present application.

Wpages 0-0 and Wpages 0-1 of page stripe 0 are provided by a logic unit coupled to channel 452, and Wpages 4-0 and Wpages 4-1 of page stripe 4 are provided by a logic unit coupled to channel 452. Parity data is computed for page stripe 0 and page stripe 4 using XOR cache 424.

Command processing unit 420 (see also FIG. 4) prepares the data to be written to W pages 0-0 of page stripe 0, allocates XOR buffers 424 for the data of W pages 0-0, and provides the data to be written to the various physical pages of W pages 0-0 one by one, for example, to XOR buffers 424. The result of the XOR operation is recorded in cache 424. As the computation of the check data with the data of each physical page is complete, the data of the physical page is written to the physical pages belonging to W pages 0-0 via channel 452.

During calculation of the intermediate check data by XOR cache 424 for W pages 0-0, command processing unit 420 prepares the data to be written to W pages 4-0 of page stripe 4. Intermediate check results from W pages 0-0 in XOR cache 424 are saved and XOR cache 424 is allocated to W pages 4-0. The data to be written to each of the physical pages of W pages 4-0 is provided to XOR cache 424 one by one. The intermediate check result for W pages 4-0 is recorded in cache 424. As the computation of the check data with the data of each physical page is complete, the data of the physical page is also written to the physical page belonging to W page 4-0 via channel 452. The write operation to W pages 0-0 and the write operation to W pages 4-0 are processed serially to share channel 452 in a time sharing manner.

Command processing unit 420 continues to prepare data to be written to W pages 0-1 of page stripe 0. Intermediate check results from W pages 4-0 in XOR cache 424 are stored and XOR cache 424 is allocated to W pages 0-1. The previously saved intermediate check results generated from W pages 0-0 are transferred to XOR cache 424.

User data to be written to W pages 0-1 is provided to XOR cache 424. The result of the XOR operation is recorded in cache 424. As the computation of the check data with the user data of each physical page is complete, the data of the physical page is written to the physical pages belonging to W pages 0-1 via channel 452. The check data recorded by XOR cache 424 is also written to physical pages belonging to W pages 0-1.

The command processing unit 420 continues to prepare data to be written to W page 4-1 of the page stripe 4. XOR cache 424 is allocated to W page 4-1. The previously saved intermediate check result generated from W pages 4-0 is transferred to XOR cache 424.

User data to be written to W page 4-1 is provided to XOR cache 424. As the computation of the check data with the user data of each physical page is complete, the data of the physical page is written to the physical page belonging to W page 4-1 via channel 452. The check data recorded by XOR cache 424 is also written to the physical page belonging to W page 4-1.

To write data of the first page stripe to the NVM chip, at least a portion of the user data of the first page stripe is written to one or more physical pages comprising the first page stripe (710). During writing of user data to the first page stripe, parity data is calculated from the user data. Since these user data are not all the user data that can be accommodated by the first page stripe, the parity data obtained from these user data are referred to as intermediate parity data.

Optionally, the intermediate check data is saved from the XOR cache to an external memory, such as DRAM. To allocate the XOR cache to other page stripes.

Before completing writing data to the first page stripe, the XOR cache and the channel in which the first page stripe is located may both be used to write data to other page stripes. Allowing the storage device to Open (Open) multiple page stripes "simultaneously" and write data to multiple page stripes in time, while using only a small amount of resources, such as XOR buffers and/or channels. Allowing multiple page stripes to be opened simultaneously allows the storage device to group and write different types of data to different page stripes.

To complete the writing of data to the first page stripe, the previously saved intermediate check results for the first page stripe are moved from the external memory to the XOR cache. And calculates the check data based on the other user data of the first page stripe and the data recorded in the XOR buffer. And writing other user data of the first page stripe to physical pages making up the first page stripe, and writing the generated parity data to the physical pages making up the first page stripe as well (730).

Optionally, user data and parity data of the first page stripe are divided into physical pages that are written to the first page stripe more times, and between each writing of data to the first page stripe, intermediate parity data generated for the first page stripe and/or the channel to which the first page stripe is coupled may be used to write data to other page stripes.

The description of the present application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the application in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art.

Claims

1. A method for a storage device, comprising:

obtaining a first portion of user data to be written to a first page stripe;

generating first check data of a first page stripe according to the first part of the user data;

writing a first portion of the user data to a first page stripe.

2. The method of claim 1, further comprising:

obtaining a second portion of user data to be written to the first page stripe;

generating second parity data of the first page stripe according to the first parity data and the second part of the user data; and

writing a second portion of the user data and the second parity data to a first page stripe.

3. The method of claim 1 or 2, wherein

In response to generating the first parity data, moving the first parity data to an external memory.

4. The method of claim 3, further comprising:

obtaining a first portion of user data to be written to a second page stripe; in response to moving the first parity data of the first page stripe to the external memory, first parity data of a second page stripe is generated from a first portion of user data to be written to the second page stripe.

5. The method of claim 3 or 4, further comprising:

first parity data of the first page stripe is retrieved from an external memory to generate second parity data of the first page stripe from the first parity data and the second portion of the user data.

6. The method according to one of claims 1 to 5, wherein

A first portion of the user data to be written to a first page stripe, written to a first W page of the first page stripe; and

the second portion of the user data to be written to the first page stripe and the second parity data for the first page stripe are written to the second W page of the first page stripe; where the first W page does not include the parity data for the first page stripe.

7. The method of claim 3 or 4, wherein

Obtaining a first portion of user data to be written to a third page stripe; in response to moving the first parity data of the second page stripe to the external memory, first parity data of a third page stripe is generated from a first portion of user data to be written to the third page stripe.

8. The method of claim 7, further comprising:

in response to completion of a first W-page operation to write a first portion of user data to be written to a third page stripe, first parity data for the first page stripe is retrieved from external memory to generate second parity data for the first page stripe from the first parity data and a second portion of the user data.

9. The method of claim 1, further comprising:

obtaining a second portion of user data to be written to the first page stripe;

generating second check data of the first page stripe according to the first check data of the first page stripe and the second part of the user data; and

writing a second portion of the user data to a first page stripe.

10. A memory device comprising control means and an NVM chip, the control means performing the method according to any of claims 1-9.