CN115588670A - Display device - Google Patents

Abstract

A display device, comprising: a substrate; a first active pattern disposed on the substrate; a second active pattern disposed on the first active pattern; a first upper electrode disposed on the second active pattern and having an island (island) shape; and a first signal wiring which is arranged on the first upper electrode, is electrically connected to the first upper electrode, and has a resistance smaller than that of the first upper electrode.

Description

Display device

Technical Field

The present invention relates to a display device. More particularly, the present invention relates to a display device including signal wirings.

Background

Generally, a display device includes a plurality of pixel structures. The pixel structure includes a transistor, at least one storage capacitor, and a light emitting element. The transistor is formed of a plurality of electrodes and a plurality of wirings, and various signals and voltages are supplied to the electrodes and the wirings. The light emitting element may emit light according to the signal and the voltage. On the other hand, as the display device is increased in size, the length of the wiring is increased, and the resistance of the wiring is increased. Which becomes a cause of reducing the transmission speed of the signal and the voltage supplied through the wiring and changing the voltage level to degrade the display quality of the display device.

Disclosure of Invention

The invention provides a display device with improved display quality.

However, the object of the present invention is not limited to the above object, and various extensions can be made within a scope not departing from the concept and field of the present invention.

In order to achieve the foregoing object of the present invention, a display device according to an embodiment of the present invention may include: a substrate; a first active pattern disposed on the substrate; a second active pattern disposed on the first active pattern; a first upper electrode disposed on the second active pattern and having an island (island) shape; and a first signal wiring which is disposed on the first upper electrode, is electrically connected to the first upper electrode, and has a resistance smaller than that of the first upper electrode.

According to an embodiment, the display device may further include: and a first lower electrode disposed between the first active pattern and the second active pattern and having an island shape, wherein the first signal wiring is electrically connected to the first lower electrode.

According to an embodiment, the first signal wiring may be in contact with the first lower electrode and the first upper electrode.

According to an embodiment, the first lower electrode, the first upper electrode, and the second active pattern may overlap each other.

According to an embodiment, the display device may further include: a second upper electrode disposed on the second active pattern and having an island shape; and a second signal wiring disposed on the second upper electrode and electrically connected to the second upper electrode.

According to an embodiment, the display device may further include: and a second lower electrode disposed between the first active pattern and the second active pattern and having an island shape, wherein the second signal wiring is electrically connected to the second lower electrode.

According to an embodiment, the second signal wiring may be in contact with the second lower electrode and the second upper electrode.

According to an embodiment, the second lower electrode, the second upper electrode, and the second active pattern may overlap each other.

According to an embodiment, the display device may further include: a first gate electrode disposed between the first active pattern and the second active pattern and having an island shape; and a third signal wiring disposed on the first gate electrode and electrically connected to the first gate electrode.

According to an embodiment, the third signal wiring may be in contact with the first gate electrode, and the first active pattern, the first gate electrode, and the third signal wiring may overlap each other.

According to an embodiment, the display device may further include: a second gate electrode disposed between the first active pattern and the second active pattern and having an island shape; and a fourth signal wiring disposed on the second gate electrode and electrically connected to the second gate electrode.

According to an embodiment, the fourth signal wiring may be in contact with the second gate electrode, and the first active pattern, the second gate electrode, and the fourth signal wiring may overlap each other.

According to an embodiment, the first signal wiring may be in contact with the first upper electrode.

According to an embodiment, the first upper electrode may be in contact with the first lower electrode.

According to an embodiment, the first signal wiring may be in contact with the first lower electrode.

According to an embodiment, the first lower electrode may be in contact with the first upper electrode.

According to an embodiment, the display device may further include: and a first lower electrode disposed in the same layer as the first active pattern, having an island shape, and electrically connected to the first signal wire.

According to an embodiment, the first signal wiring may be in contact with the first lower electrode and the first upper electrode.

According to an embodiment, the first upper electrode and the first signal wiring may include metal substances different from each other.

According to an embodiment, the first active pattern may include polysilicon, and the second active pattern may include an oxide semiconductor.

(effect of the invention)

A display device according to an embodiment of the present invention includes an upper electrode disposed above an active pattern, a lower electrode disposed below the active pattern, and a signal wiring electrically connected to the upper electrode and the lower electrode. A gate signal is transmitted through the signal wiring having a resistance smaller than that of the upper electrode, a transmission speed of the gate signal can be increased, and a voltage level of the gate signal can be maintained. In addition, the active pattern, the upper electrode, and the lower electrode overlap each other, thereby implementing a transistor as a dual-gate (dual-gate) structure, whereby on-characteristics and/or off-characteristics of the transistor can be improved.

However, the effects of the present invention are not limited to the above-described effects, and various extensions can be made within the scope not departing from the concept and field of the present invention.

Drawings

Fig. 1 is a plan view illustrating a display device according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing an example of a pixel circuit and an organic light emitting diode included in the display device of fig. 1.

Fig. 3 to 9 are layout views illustrating an embodiment of a pixel structure included in the display device of fig. 1.

Fig. 10 is a sectional view taken along line I-I' of fig. 9.

Fig. 11 is a sectional view taken along line II-II' of fig. 9.

Fig. 12 is a sectional view taken along line III-III' of fig. 9.

Fig. 13 is a sectional view taken along line IV-IV' of fig. 9.

Fig. 14 is a sectional view taken along line V-V' of fig. 9.

Fig. 15 is a cross-sectional view illustrating another embodiment of a pixel structure included in the display device of fig. 1.

Fig. 16 is a sectional view showing still another embodiment of a pixel structure included in the display device of fig. 1.

Fig. 17 to 22 are layout views showing still another embodiment of a pixel structure included in the display device of fig. 1.

Fig. 23 is a sectional view taken along line VI-VI' of fig. 22.

Fig. 24 is a sectional view taken along line VII-VII' of fig. 22.

(description of reference numerals)

10: a display device SUB: substrate

1100: first conductive pattern 1200: a second conductive pattern

1300: second active pattern 1400: third conductive pattern

1500: a fourth conductive pattern

Detailed Description

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description thereof will be omitted.

Fig. 1 is a plan view illustrating a display device according to an embodiment of the present invention, and fig. 2 is a circuit diagram illustrating an example of a pixel circuit and an organic light emitting diode included in the display device of fig. 1.

Referring to fig. 1 and 2, the display device 10 may include a display area DA, a non-display area NDA surrounding the display area DA, a bendable bent area BA, and a pad area PA.

For example, a pixel structure PX may be disposed in the display area DA, and a driving unit for driving the pixel structure PX may be disposed in the non-display area NDA. For example, the pad area PA may be provided with a pad portion PD and a data driving portion DDV, and the bending area BA may be bent with reference to a virtual bending axis.

The pixel structure PX, and a data line DL, a gate line GL, a light emission control line EML, and a driving voltage line PL connected to the pixel structure PX may be further disposed in the display region DA.

The data wire DL may be electrically connected to the data driving part DDV and extend in the second direction D2. The DATA wiring DL may receive the supply of the DATA voltage DATA from the DATA driving part DDV to supply the DATA voltage DATA to the pixel circuit PC.

The gate line GL may be connected to the gate driving portion GDV and extend in a first direction D1 intersecting the second direction D2. The gate wiring GL may receive a supply of a gate signal from the gate driving portion GDV to supply the gate signal to the pixel circuit PC.

The light emission control wire EML may be connected to the light emission driving part EDV and extend in the first direction D1. The emission control wiring EML may receive the supply of the emission control signal EM from the emission driving part EDV to supply the emission control signal EM to the pixel circuit PC. For example, the active interval of the emission control signal EM may be an emission interval of the display apparatus 10, and the inactive interval of the emission control signal EM may be a non-emission interval of the display apparatus 10.

The driving voltage wiring PL may be connected to the pad portion PD and extend in the second direction D2. The driving voltage wiring PL may receive the supply of the high power supply voltage ELVDD from the pad part PD to supply the high power supply voltage ELVDD to the pixel circuit PC. On the other hand, the low power supply voltage ELVSS may be commonly supplied to a counter electrode (e.g., a cathode electrode) of the organic light emitting diodes OLED.

The driving part may include the gate driving part GDV, the data driving part DDV, the light emission driving part EDV, and the pad part PD. In addition, the driving part may include a timing control part which may control the gate driving part GDV, the data driving part DDV, the light emission driving part EDV, and the pad part PD.

The gate driving part GDV may receive the supply of the voltage from the pad part PD to generate the gate signal. For example, the gate signals may include a first gate signal GW, a second gate signal GC, a third gate signal GI, and a fourth gate signal GB.

The DATA driving part DDV may generate the DATA voltage DATA corresponding to the light emitting section and the non-light emitting section. The light emission driving part EDV may receive the supply of the voltage from the pad part PD to generate the light emission control signal EM. The pad part PD may be electrically connected to an external device to supply voltages to the gate driving part GDV, the light emission driving part EDV, and the driving voltage wiring PL, respectively.

On the other hand, although fig. 1 shows that the gate driving part GDV and the light emission driving part EDV are respectively disposed on the left and right sides of the display device 10, the present invention is not limited thereto.

In addition, although it is illustrated in fig. 1 that the data driving part DDV is mounted in the non-display region NDA of the display device 10, the present invention is not limited thereto. For example, the data driving unit DDV may be disposed on a separate flexible printed circuit board (flexible printed circuit board), and the pad unit PD may be electrically connected to the flexible printed circuit board.

The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a boost capacitor CBS. The pixel circuit PC may be electrically connected to the organic light emitting diode OLED to supply a driving current to the organic light emitting diode OLED.

The organic light emitting diode OLED may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal), and the first terminal of the organic light emitting diode OLED may be connected to the first transistor T1 through the sixth transistor T6 to receive the supply of the driving current, and the second terminal may receive the supply of the low power supply voltage ELVSS. The organic light emitting diode OLED may generate light of a luminance corresponding to the driving current.

The storage capacitor CST may include a first terminal and a second terminal. It may be that the first terminal of the storage capacitor CST is connected with the first transistor T1, and the second terminal of the storage capacitor CST receives the supply of the high power supply voltage ELVDD. The storage capacitor CST may maintain a voltage level of the gate terminal of the first transistor T1 during an inactive period of the first gate signal GW.

The boost capacitor CBS may include a first terminal and a second terminal. The first terminal of the boost capacitor CBS may be connected to a first terminal of the storage capacitor CST, and the second terminal of the boost capacitor CBS receives the provision of the first gate signal GW. The boost capacitor CBS may increase the voltage of the gate terminal of the first transistor T1 at a point when the supply of the first gate signal GW is interrupted, thereby compensating for the voltage drop of the gate terminal.

The first transistor T1 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor T1 may be connected with a first terminal of the storage capacitor CST. The first terminal of the first transistor T1 may be connected to the second transistor T2 to receive the supply of the DATA voltage DATA. The second terminal of the first transistor T1 may be connected to the organic light emitting diode OLED via the sixth transistor T6 to supply the driving current. The first transistor T1 may generate the driving current based on a voltage difference between the gate terminal and the first terminal. For example, the first transistor T1 may be referred to as a driving transistor.

The second transistor T2 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor T2 may receive the supply of the first gate signal GW through the gate wiring GL.

The second transistor T2 may be turned on or off in response to the first gate signal GW. For example, when the second transistor T2 is a PMOS transistor, the second transistor T2 may be turned off when the first gate signal GW has a positive voltage level and turned on when the first gate signal GW has a negative voltage level. The first terminal of the second transistor T2 may receive the supply of the DATA voltage DATA through the DATA wiring DL. The second terminal of the second transistor T2 may supply the DATA voltage DATA to the first terminal of the first transistor T1 during an interval in which the second transistor T2 is turned on. For example, the second transistor T2 may be referred to as a switching transistor.

The third transistor T3 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the third transistor T3 may receive the supply of the second gate signal GC. The first terminal of the third transistor T3 may be connected to a gate terminal of the first transistor T1. The second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1.

The third transistor T3 may be turned on or off in response to the second gate signal GC. For example, when the third transistor T3 is an NMOS transistor, the third transistor T3 may be turned on when the second gate signal GC has a positive voltage level and turned off when the second gate signal GC has a negative voltage level.

The third transistor T3 may diode-connect the first transistor T1 during an interval in which the third transistor T3 is turned on in response to the second gate signal GC. Since the first transistor T1 is diode-connected, a voltage difference of the degree of the threshold voltage of the first transistor T1 may be generated between the gate terminal of the first transistor T1 and the first terminal of the first transistor T1. Accordingly, in the gate terminal of the first transistor T1, a voltage obtained by adding the voltage difference to the DATA voltage DATA supplied to the first terminal of the first transistor T1 may be supplied to the gate terminal of the first transistor T1 during the period in which the third transistor T3 is turned on. Accordingly, the third transistor T3 may compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be referred to as a compensation transistor.

The fourth transistor T4 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fourth transistor T4 may receive a supply of the third gate signal GI. The first terminal of the fourth transistor T4 may receive a supply of a gate initialization voltage VINT. The second terminal of the fourth transistor T4 may be connected to a gate terminal of the first transistor T1.

The fourth transistor T4 may be turned on or off in response to the third gate signal GI. For example, when the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 may be turned on when the third gate signal GI has a positive voltage level, and turned off when the third gate signal GI has a negative voltage level.

The gate initialization voltage VINT may be provided at the gate terminal of the first transistor T1 during a period in which the fourth transistor T4 is turned on in response to the third gate signal GI. Thereby, the fourth transistor T4 may initialize the gate terminal of the first transistor T1 to the gate initialization voltage VINT. For example, the fourth transistor T4 may be referred to as a gate initialization transistor.

The fifth transistor T5 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor T5 may receive the supply of the emission control signal EM. The first terminal of the fifth transistor T5 may receive the supply of the high power supply voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first terminal of the first transistor T1. If the fifth transistor T5 is turned on in response to the light emission control signal EM, the fifth transistor T5 may supply the high power supply voltage ELVDD to the first transistor T1.

The sixth transistor T6 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor T6 may receive the supply of the emission control signal EM. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1. The second terminal of the sixth transistor T6 may be connected to the first terminal of the organic light emitting diode OLED. If the sixth transistor T6 is turned on in response to the light emission control signal EM, the sixth transistor T6 may provide the driving current generated by the first transistor T1 to the organic light emitting diode OLED.

The seventh transistor T7 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor T7 may receive the supply of the fourth gate signal GB. The first terminal of the seventh transistor T7 may receive the supply of an anode initialization voltage AINT. The second terminal of the seventh transistor T7 may be connected to the first terminal of the organic light emitting diode OLED. If the seventh transistor T7 is turned on in response to the fourth gate signal GB, the seventh transistor T7 may supply the anode initialization voltage AINT to the organic light emitting diode OLED. Thereby, the seventh transistor T7 may initialize the first terminal of the organic light emitting diode OLED to the anode initialization voltage AINT. For example, the seventh transistor T7 may be referred to as an anode initialization transistor.

On the other hand, the connection structure of the pixel circuit PC shown in fig. 2 is exemplary, and various changes may be made. For example, when the pixel circuit PC does not include the third to seventh transistors T3, T4, T5, T6, T7 and the boost capacitor CBS, the connection structure between the constituent elements in the pixel circuit PC may be changed in order to form the connection structure between the constituent elements (i.e., the first transistor T1, the second transistor T2, the storage capacitor CST, and the organic light emitting diode OLED) included in the pixel circuit PC.

Fig. 3 to 9 are layout views illustrating an embodiment of a pixel structure included in the display device of fig. 1.

Referring to fig. 3, the pixel structure PX may include a substrate SUB and a first conductive pattern 1100 disposed on the substrate SUB. The first conductive pattern 1100 may include a first active pattern 1110 and a gate initialization voltage wiring 1120.

The substrate SUB may include a glass substrate, a quartz substrate, a plastic substrate, and the like. In an embodiment, the substrate SUB may include a plastic substrate, and thus the display device 10 may have a flexible characteristic. In this case, the substrate SUB may have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. For example, the organic film layer may be formed using an organic substance such as polyimide, and the barrier layer may be formed using an inorganic substance.

A buffer layer (e.g., BFR of fig. 10) may be disposed on the substrate SUB. The buffer layer may prevent a phenomenon in which metal atoms or impurities are diffused from the substrate SUB to the first conductive pattern 1100. In addition, the buffer layer may uniformly form the first conductive pattern 1100 by adjusting a supply speed of heat during a crystallization process for forming the first conductive pattern 1100.

The first active pattern 1110 may be disposed on the buffer layer. In one embodiment, the first active pattern 1110 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polysilicon, and the like.

In one embodiment, ions may be selectively implanted into the first active pattern 1110. For example, when the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 are PMOS transistors, the first active pattern 1110 may include source and drain regions implanted with cations and a channel region not implanted with the cations.

The gate initialization voltage wiring 1120 may extend toward the first direction D1. In one embodiment, the gate initialization voltage wiring 1120 may supply the gate initialization voltage VINT to the fourth transistor T4. In another embodiment, the gate initialization voltage wiring 1120 may also be disposed in a different layer from the first active pattern 1110.

A first gate insulating layer (e.g., GI1 of fig. 10) may cover the first conductive pattern 1100 and be disposed on the substrate SUB. The first gate insulating layer may include an insulating substance. For example, the first gate insulating layer may include silicon oxide, silicon nitride, titanium oxide, tantalum oxide, or the like.

Referring to fig. 4, a second conductive pattern 1200 may be disposed on the first gate insulating layer. The second conductive pattern 1200 may include a first lower electrode 1210, a first gate electrode 1220, a second lower electrode 1230, a third gate electrode 1240, a light emission control wiring 1250, a second gate electrode 1260, and an anode initialization voltage wiring 1270. The first gate electrode 1220 may include a first portion 1221 and a second portion 1222 connected to the first portion 1221.

The first lower electrode 1210 may extend in the first direction D1 and be arranged in an island (island) shape. For example, the first lower electrode 1210 may function as a lower gate electrode of the fourth transistor T4. For example, the first lower electrode 1210 may be in contact with a first signal wiring (e.g., 1520 of fig. 11) to be described later.

The first gate electrode 1220 may be configured in an island shape. For example, the first portion 1221 may function as the second terminal of the boost capacitor CBS, and the second portion 1222 may constitute the second transistor T2 together with a portion of the first active pattern 1110. For example, the second portion 1222 may be connected to the first portion 1221 to function as the gate terminal of the second transistor T2. For example, the second portion 1222 may be in contact with a third signal wiring (e.g., 1541 of fig. 12) which will be described later.

The second lower electrode 1230 may extend in the first direction D1 and be configured in an island shape. For example, the second lower electrode 1230 may function as a lower gate electrode of the third transistor T3. For example, the second lower electrode 1230 may be in contact with a second signal wiring (e.g., 1550 of fig. 10) to be described later.

The third gate electrode 1240 may be configured in an island shape. For example, the third gate electrode 1240 may constitute the first transistor T1 together with a portion of the first active pattern 1110.

The light emission control wiring 1250 may extend toward the first direction D1. For example, the light emission control wiring 1250 may constitute the fifth and sixth transistors T5 and T6 together with a portion of the first active pattern 1110. For example, the emission control signal EM may be provided to the emission control wiring 1250.

The second gate electrode 1260 may be configured in an island shape. For example, the second gate electrode 1260 may constitute the seventh transistor T7 together with a portion of the first active pattern 1110. For example, the second gate electrode 1260 may be in contact with a fourth signal wiring (e.g., 1542 of fig. 13) to be described later.

The anode initialization voltage wiring 1270 may extend toward the first direction D1. For example, the anode initialization voltage wiring 1270 may be spaced not to overlap with the first active pattern 1110. The anode initialization voltage wiring 1270 may supply the anode initialization voltage AINT to the seventh transistor T7.

For example, the second conductive pattern 1200 may include a metal, an alloy, a conductive metal oxide, a transparent conductive substance, and the like. For example, the second conductive pattern 1200 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and the like. In one embodiment, the second conductive pattern 1200 may include the molybdenum (Mo), an alloy including the molybdenum, or the like in order to ensure process reliability.

A first interlayer insulating layer (e.g., ILD1 of fig. 10) may cover the second conductive pattern 1200 and be disposed on the first gate insulating layer. The first interlayer insulating layer may include an insulating substance.

On the other hand, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be substantially the same as the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 described with reference to fig. 2. The gate terminal, the first terminal, and the second terminal described with reference to fig. 2 may substantially correspond to a conductive pattern to be described later. However, such a correspondence relationship, which is obvious to a person having ordinary skill in the art to which the present invention pertains, is not described in detail.

Referring to fig. 5 and 6, a second active pattern 1300 may be disposed on the first interlayer insulating layer. In an embodiment, the second active pattern 1300 may include an oxide semiconductor.

For example, the second active pattern 1300 may include a channel region, a source region, and a drain region for constituting the third and fourth transistors T3 and T4. Specifically, the second active pattern 1300 may include a channel region b, a source region a, and a drain region c for constituting the fourth transistor T4. The channel region b may overlap with the first lower electrode 1210. In addition, the second active pattern 1300 may include a channel region e, a source region f, and a drain region d for constituting the third transistor T3. The channel region e may overlap with the second lower electrode 1230.

In addition, in an embodiment, the second active pattern 1300 may further include a third portion g that may function as the first terminal of the boost capacitor CBS. The third portion g may overlap with the first portion 1221. In addition, the second active pattern 1300 may include a fourth portion h that may function as the second terminal of the storage capacitor CST. The fourth portion h may overlap with the third gate electrode 1240. The fourth portion h may be in contact with a high power voltage pattern (e.g., 1570 of fig. 14) to be described later. Thus, the boost capacitor CBS and the storage capacitor CST may be formed without further including a separate metal layer.

A second gate insulating layer (e.g., GI2 of fig. 10) may cover the second active pattern 1300 and be disposed on the first interlayer insulating layer. The second gate insulating layer may include an insulating substance.

Referring to fig. 7, a third conductive pattern 1400 may be disposed on the second gate insulating layer. The third conductive pattern 1400 may include a first upper electrode 1410 and a second upper electrode 1420.

The first upper electrode 1410 may extend toward the first direction D1 and be configured in an island shape. For example, the first upper electrode 1410 may function as an upper gate electrode of the fourth transistor T4. In other words, the fourth transistor T4 may have a dual-gate structure. For example, the first upper electrode 1410 may be in contact with a first signal wiring (e.g., 1520 of fig. 11) which will be described later.

The second upper electrode 1420 may extend toward the first direction D1 and be configured in an island shape. For example, the second upper electrode 1420 may function as an upper gate electrode of the third transistor T3. In other words, the third transistor T3 may have a double gate structure. For example, the second upper electrode 1420 may be in contact with a second signal wiring (e.g., 1550 of fig. 10) to be described later.

The third and fourth transistors T3 and T4 have a dual-gate structure, respectively, so that on-characteristics and/or off-characteristics of the third and fourth transistors T3 and T4 can be improved.

For example, the third conductive pattern 1400 may include a metal, an alloy, a conductive metal oxide, a transparent conductive substance, and the like. For example, the third conductive pattern 1400 may include the same substance as the second conductive pattern 1200. In one embodiment, the second and third conductive patterns 1200 and 1400 may include the molybdenum (Mo), an alloy including the molybdenum, and the like in order to ensure process reliability.

A second interlayer insulating layer (e.g., ILD2 of fig. 10) may cover the third conductive pattern 1400 and be disposed on the second gate insulating layer. The second interlayer insulating layer may include an insulating substance.

Referring to fig. 8 and 9, the fourth conductive pattern 1500 may include a gate initialization voltage connection wiring 1510, a first signal wiring 1520, a first pad 1530, a third signal wiring 1541, a second signal wiring 1550, a compensation connection pattern 1560, a high power supply voltage pattern 1570, a second pad 1580, a fourth signal wiring 1542, and an anode initialization voltage connection wiring 1590.

The gate initialization voltage connection wiring 1510 may electrically connect the gate initialization voltage wiring 1120 and the second active pattern 1300. The gate initialization voltage VINT may be transferred to the first active pattern 1110 through the gate initialization voltage connection wiring 1510.

The first signal wiring 1520 may extend to the first direction D1. For example, the third gate signal GI may be provided to the first signal wiring 1520. In one embodiment, the first signal wiring 1520 may be in contact with the first lower electrode 1210 and the first upper electrode 1410. Thus, the third gate signal GI provided at the first signal wiring 1520 may be transmitted to the first lower electrode 1210 and the first upper electrode 1410.

The first pad 1530 may transmit the DATA voltage DATA to the first active pattern 1110. For example, the first pad 1530 may be disposed between the first active pattern 1110 and the data wire, and may be in contact with the first active pattern 1110 and the data wire.

The third signal wiring 1541 may extend in the first direction D1. For example, the first gate signal GW may be provided to the third signal wiring 1541. In an embodiment, the third signal wiring 1541 may be in contact with the second portion 1222 of the first gate electrode 1220. Thus, the first gate signal GW provided at the third signal wiring 1541 may be transmitted to the second portion 1222.

The second signal wiring 1550 may extend to the first direction D1. For example, the second gate signal GC may be provided to the second signal wiring 1550. In one embodiment, the second signal wire 1550 may be in contact with the second lower electrode 1230 and the second upper electrode 1420. Thereby, the second gate signal GC may be transmitted to the second lower electrode 1230 and the second upper electrode 1420.

The compensation connection pattern 1560 may electrically connect the second active pattern 1300 and the first active pattern 1110. For example, the second terminal of the third transistor T3 (e.g., a drain terminal of a third transistor) may be connected with the second terminal of the first transistor T1 (e.g., a drain terminal of a first transistor) through the compensation connection pattern 1560.

The high power supply voltage pattern 1570 may transmit the high power supply voltage ELVDD to the second active pattern 1300 and the first active pattern 1110. For example, the high power voltage pattern 1570 may contact the second active pattern 1300 in a portion i overlapping the second active pattern 1300. In addition, the high power voltage pattern 1570 may contact the first active pattern 1110 in another partial region j overlapping the first active pattern 1110.

The second pad 1580 may supply the driving current and the anode initialization voltage AINT to a first electrode (e.g., 1710 of fig. 10) of an organic light emitting diode, which will be described later. For example, the second pad 1580 may be disposed between the first active pattern 1110 and the first electrode, and may contact the first active pattern 1110.

The fourth signal wiring 1542 may extend in the first direction D1. For example, the fourth gate signal GB may be supplied to the fourth signal wiring 1542. In one embodiment, the fourth signal wiring 1542 may be in contact with the second gate electrode 1260. Thereby, the fourth gate signal GB provided at the fourth signal wiring 1542 may be transmitted to the second gate electrode 1260.

The anode initialization voltage connection wiring 1590 may electrically connect the anode initialization voltage wiring 1270 and the first active pattern 1110. The anode initialization voltage AINT may be transferred to the first active pattern 1110 through the anode initialization voltage connection wiring 1590.

For example, the fourth conductive pattern 1500 may include a metal, an alloy, a conductive metal oxide, a transparent conductive substance, and the like. For example, the fourth conductive pattern 1500 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and the like. In an embodiment, to reduce the resistance of the fourth conductive pattern 1500, the fourth conductive pattern 1500 may include the aluminum (Al). For example, the fourth conductive pattern 1500 may have a Ti/Al/Ti structure in which titanium (Ti) and aluminum (Al) are alternately arranged.

A first VIA insulating layer (e.g., VIA1 of fig. 10) may cover the fourth conductive pattern 1500 and be disposed on the second interlayer insulating layer. The first via insulating layer may include an organic insulating substance. For example, the first via insulating layer may include a photoresist, an acrylic resin, a polyimide resin, an acrylic resin, or the like.

On the other hand, although not shown, a data wiring (e.g., 1610 of fig. 12) and/or a driving voltage wiring (e.g., 1620 of fig. 10) may be disposed on the first via insulating layer. For example, the data wire may correspond to the data wire DL described with reference to fig. 1, and the driving voltage wire may correspond to the driving voltage wire PL described with reference to fig. 1.

In addition, a second VIA insulating layer (e.g., VIA2 of fig. 10) may cover the data wire and the driving voltage wire and be disposed on the first VIA insulating layer, and an organic light emitting element (e.g., 1700 of fig. 10) may be disposed on the second VIA insulating layer.

Fig. 10 is a sectional view taken along line I-I' of fig. 9.

Referring to fig. 2, 9 and 10, the pixel structure PX may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the second lower electrode 1230, the first interlayer insulating layer ILD1, the second active pattern 1300, the second gate insulating layer GI2, the second upper electrode 1420, the second interlayer insulating layer ILD2, the second signal wire 1550, the first VIA insulating layer VIA1, the driving voltage wire 1620, the second VIA insulating layer VIA2, the first electrode 1710, the light emitting layer 1720 and the second electrode 1730 are sequentially disposed.

As described above, the second signal wiring 1550 may be in contact with the second lower electrode 1230 and the second upper electrode 1420. Thereby, the second gate signal GC provided at the second signal wiring 1550 may be transmitted to the second lower electrode 1230 and the second upper electrode 1420.

In one embodiment, the second lower electrode 1230 and the second upper electrode 1420 may include the molybdenum (Mo), an alloy including the molybdenum, or the like, and the second signal wiring 1550 may have a Ti/Al/Ti structure including the aluminum (Al). Thus, the resistance of the second signal wiring 1550 may be less than the resistance of the second lower electrode 1230 or the resistance of the second upper electrode 1420. By implementing the wiring that transmits the second gate signal GC as the second signal wiring 1550, the transmission speed of the second gate signal GC can be increased, and the voltage level of the second gate signal GC can be maintained.

In one embodiment, the channel region e, the second lower electrode 1230, and the second upper electrode 1420 of the second active pattern 1300 may overlap each other. Thus, the second active pattern 1300, the second lower electrode 1230, and the second upper electrode 1420 may constitute the third transistor T3 having a dual gate structure. By implementing the third transistor T3 as a dual gate structure, the on-characteristics and/or off-characteristics of the third transistor T3 may be improved.

Fig. 11 is a sectional view taken along line II-II' of fig. 9.

Referring to fig. 2, 9 and 11, the pixel structure PX may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the first lower electrode 1210, the first interlayer insulating layer ILD1, the second active pattern 1300, the second gate insulating layer GI2, the first upper electrode 1410, the second interlayer insulating layer ILD2, the first signal wiring 1520, the first VIA insulating layer VIA1, the driving voltage wiring 1620, the second VIA insulating layer VIA2, the first electrode 1710, the light emitting layer 1720 and the second electrode 1730 are sequentially disposed.

As described above, the first signal wiring 1520 may be in contact with the first lower electrode 1210 and the first upper electrode 1410. Thus, the third gate signal GI provided at the first signal wiring 1520 may be transmitted to the first lower electrode 1210 and the first upper electrode 1410.

In one embodiment, the first lower electrode 1210 and the first upper electrode 1410 may include the molybdenum (Mo), an alloy including the molybdenum (Mo), and the like, and the first signal wiring 1520 may have a Ti/Al/Ti structure including the aluminum (Al). Thus, the resistance of the first signal wiring 1520 may be smaller than the resistance of the first lower electrode 1210 or the resistance of the first upper electrode 1410. By implementing the wiring for transmitting the third gate signal GI as the first signal wiring 1520, the transmission speed of the third gate signal GI may be increased, and the voltage level of the third gate signal GI may be maintained.

In an embodiment, the channel region b, the first lower electrode 1210, and the first upper electrode 1410 of the second active pattern 1300 may overlap each other. Thus, the second active pattern 1300, the first lower electrode 1210, and the first upper electrode 1410 may constitute the fourth transistor T4 having a dual gate structure. By implementing the fourth transistor T4 as a dual gate structure, the on-characteristics and/or off-characteristics of the fourth transistor T4 may be improved.

Fig. 12 is a sectional view taken along line III-III' of fig. 9.

Referring to fig. 2, 9, and 12, the pixel structure PX may have a structure in which the substrate SUB, the buffer layer BFR, the first active pattern 1110, the first gate insulating layer GI1, the second portion 1222 of the first gate electrode, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, the second interlayer insulating layer ILD2, the third signal wire 1541, the first VIA insulating layer VIA1, the data wire 1610, the second VIA insulating layer VIA2, the first electrode 1710, the light-emitting layer 1720, and the second electrode 1730 are sequentially disposed.

As described above, the third signal wiring 1541 may be in contact with the second portion 1222. Thus, the first gate signal GW provided at the third signal wiring 1541 may be transmitted to the second portion 1222.

In one embodiment, the second portion 1222 may include the molybdenum (Mo), an alloy including the molybdenum, or the like, and the third signal wiring 1541 may have a Ti/Al/Ti structure including the aluminum (Al). Thus, the resistance of the third signal wiring 1541 can be smaller than the resistance of the second portion 1222. By implementing the wiring that transmits the first gate signal GW as the third signal wiring 1541, the transmission speed of the first gate signal GW may be increased, and the voltage level of the first gate signal GW may be maintained.

In an embodiment, the first active pattern 1110 and the second portion 1222 may overlap each other. Thus, the first active pattern 1110 and the second portion 1222 may constitute the second transistor T2.

Fig. 13 is a sectional view taken along line IV-IV' of fig. 9.

Referring to fig. 2, 9 and 13, the pixel structure PX may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the second gate electrode 1260, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, the second interlayer insulating layer ILD2, the fourth signal wire 1542, the first VIA insulating layer VIA1, the second VIA insulating layer VIA2, the first electrode 1710, the light-emitting layer 1720 and the second electrode 1730 are sequentially disposed.

As described above, the fourth signal wiring 1542 may be in contact with the second gate electrode 1260. Thereby, the fourth gate signal GB provided at the fourth signal wiring 1542 may be transmitted to the second gate electrode 1260.

In one embodiment, the second gate electrode 1260 may include the molybdenum (Mo), an alloy including the molybdenum, or the like, and the fourth signal wiring 1542 may have a Ti/Al/Ti structure including the aluminum (Al). Thus, the resistance of the fourth signal wiring 1542 may be smaller than the resistance of the second gate electrode 1260. By implementing the wiring that transmits the fourth gate signal GB as the fourth signal wiring 1542, the transmission speed of the fourth gate signal GB can be increased, and the voltage level of the fourth gate signal GB can be maintained.

In one embodiment, the first active pattern 1110 and the second gate electrode 1260 may overlap each other. Thus, the first active pattern 1110 and the second gate electrode 1260 may constitute the seventh transistor T7.

Fig. 14 is a sectional view taken along line V-V' of fig. 9.

Referring to fig. 2, 9 and 14, the pixel structure PX may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the third gate electrode 1240, the first interlayer insulating layer ILD1, the second active pattern 1300, the second gate insulating layer GI2, the second interlayer insulating layer ILD2, the high power voltage pattern 1570, the first VIA insulating layer VIA1, the driving voltage wiring 1620, the second VIA insulating layer VIA2, the first electrode 1710, the light emitting layer 1720 and the second electrode 1730 are sequentially disposed.

As described above, the second active pattern 1300 may contact the high power voltage pattern 1570 in the fourth portion h, and the high power voltage pattern 1570 may contact the driving voltage wiring 1620. The second active pattern 1300 may be electrically connected with the driving voltage wiring 1620 to receive the supply of the high power supply voltage ELVDD.

In an embodiment, the fourth portion h of the second active pattern 1300 and the third gate electrode 1240 may overlap each other. Thus, the second active pattern 1300 and the third gate electrode 1240 may constitute the storage capacitor CST. The display device 10 may also form the storage capacitor CST without further including a separate metal layer.

Fig. 15 is a sectional view showing another embodiment of a pixel structure included in the display device of fig. 1, and fig. 16 is a sectional view showing still another embodiment of a pixel structure included in the display device of fig. 1.

Referring to fig. 15, the pixel structure PX-2 may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the second lower electrode 1230-2, the first interlayer insulating layer ILD1, the second active pattern 1300, the second gate insulating layer GI2, the second upper electrode 1420-2, the second interlayer insulating layer ILD2, the second signal wire 1550-2, the first VIA insulating layer VIA1, the driving voltage wire 1620, the second VIA insulating layer VIA2, the first electrode 1710, the light emitting layer 1720, and the second electrode 1730 are sequentially disposed. However, the pixel structure PX-2 is substantially the same as the pixel structure PX described with reference to fig. 10 except for the contact relationship of the second lower electrode 1230-2, the second upper electrode 1420-2, and the second signal wire 1550-2, and thus, the contact relationship of the second lower electrode 1230-2, the second upper electrode 1420-2, and the second signal wire 1550-2 will be described in detail below.

The second signal wiring 1550-2 may contact the second upper electrode 1420-2, and the second upper electrode 1420-2 may contact the second lower electrode 1230-2. Thereby, the second gate signal GC provided at the second signal wiring 1550-2 may be transmitted to the second lower electrode 1230-2 and the second upper electrode 1420-2.

Referring to fig. 16, the pixel structure PX-3 may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the second lower electrode 1230-3, the first interlayer insulating layer ILD1, the second active pattern 1300, the second gate insulating layer GI2, the second upper electrode 1420-3, the second interlayer insulating layer ILD2, the second signal wire 1550-3, the first VIA insulating layer VIA1, the driving voltage wire 1620, the second VIA insulating layer VIA2, the first electrode 1710, the light-emitting layer 1720, and the second electrode 1730 are sequentially disposed. However, the pixel structure PX-3 is substantially the same as the pixel structure PX described with reference to fig. 10 except for the contact relationship of the second lower electrode 1230-3, the second upper electrode 1420-3, and the second signal wire 1550-3, and thus, the contact relationship of the second lower electrode 1230-3, the second upper electrode 1420-3, and the second signal wire 1550-3 will be described in detail below.

The second signal wiring 1550-3 may be in contact with the second lower electrode 1230-3, and the second upper electrode 1420-3 may be in contact with the second lower electrode 1230-3. Thereby, the second gate signal GC provided at the second signal wiring 1550-3 may be transmitted to the second lower electrode 1230-3 and the second upper electrode 1420-3.

Fig. 17 to 22 are layout views showing still another embodiment of a pixel structure included in the display device of fig. 1.

Referring to fig. 17, a pixel structure PX-4 may include a substrate SUB and a first conductive pattern 2100 disposed on the substrate SUB. The first conductive pattern 2100 may include a first active pattern 2110, a gate initialization voltage wiring 2120, a first lower electrode 2130, and a second lower electrode 2140.

The substrate SUB may include a glass substrate, a quartz substrate, a plastic substrate, and the like. In an embodiment, the substrate SUB may include a plastic substrate, and thus, the display device 10 may have a flexible characteristic. In this case, the substrate SUB may have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. For example, the organic film layer may be formed using an organic substance such as polyimide, and the barrier layer may be formed using an inorganic substance.

A buffer layer (e.g., BFR of fig. 23) may be disposed on the substrate SUB. The buffer layer may prevent a phenomenon in which metal atoms or impurities are diffused from the substrate SUB to the first conductive pattern 2100. In addition, the buffer layer may uniformly form the first conductive pattern 2100 by adjusting a supply speed of heat during a crystallization process for forming the first conductive pattern 2100.

The first active pattern 2110 may be disposed on the buffer layer. In an embodiment, the first active pattern 2110 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polysilicon, and the like.

In one embodiment, ions may be selectively implanted into the first active pattern 2110. For example, when the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 are the PMOS transistors, the first active pattern 2110 may include source and drain regions into which the cations are injected and a channel region into which the cations are not injected.

The gate initialization voltage wire 2120 may extend toward the first direction D1. In one embodiment, the gate initialization voltage wiring 2120 may supply the gate initialization voltage VINT to the fourth transistor T4. In another embodiment, the gate initialization voltage wiring 2120 may also be disposed on the first active pattern 2110.

The first lower electrode 2130 may extend in the first direction D1 and be arranged in an island (island) shape. For example, the first lower electrode 2130 may function as a lower gate electrode of the fourth transistor T4. For example, the first lower electrode 2130 may be in contact with a first signal wire (e.g., 2520 of fig. 24) to be described later.

The second lower electrode 2140 may extend in the first direction D1 and be arranged in an island shape. For example, the second lower electrode 2140 may function as a lower gate electrode of the third transistor T3. For example, the second lower electrode 2140 may be in contact with a second signal wiring (e.g., 2550 of fig. 23) which will be described later.

A first gate insulating layer (e.g., GI1 of fig. 23) may cover the first conductive pattern 2100 and be disposed on the substrate SUB. The first gate insulating layer may include an insulating substance. For example, the first gate insulating layer may include silicon oxide, silicon nitride, titanium oxide, tantalum oxide, or the like.

Referring to fig. 18, a second conductive pattern 2200 may be disposed on the first gate insulating layer. The second conductive pattern 2200 may include a first gate electrode 2220, a third gate electrode 2240, a light emission control wiring 2250, a second gate electrode 2260, and an anode initialization voltage wiring 2270. The first gate electrode 2220 may include a first portion 2221 and a second portion 2222 connected to the first portion 2221.

The first gate electrode 2220 may be configured in an island shape. For example, the first portion 2221 may function as the second terminal of the boost capacitor CBS, and the second portion 2222 may constitute the second transistor T2 together with a portion of the first active pattern 2110. For example, the second portion 2222 may be connected to the first portion 2221 to function as the gate terminal of the second transistor T2.

The third gate electrode 2240 may be configured in an island shape. For example, the third gate electrode 2240 may constitute the first transistor T1 together with a portion of the first active pattern 2110.

The light emission control wiring 2250 may extend to the first direction D1. For example, the light emitting control wire 2250 may constitute the fifth and sixth transistors T5 and T6 together with a portion of the first active pattern 2110. For example, the light emission control signal EM may be provided to the light emission control wiring 2250.

The second gate electrode 2260 may be configured in an island shape. For example, the second gate electrode 2260 may constitute the seventh transistor T7 together with a portion of the first active pattern 2110.

The anode initialization voltage wiring 2270 may extend toward the first direction D1. For example, the anode initialization voltage wiring 2270 may be spaced not to overlap with the first active pattern 2110. The anode initialization voltage wiring 2270 may supply the anode initialization voltage AINT to the seventh transistor T7.

For example, the second conductive pattern 2200 may include a metal, an alloy, a conductive metal oxide, a transparent conductive substance, and the like. For example, the second conductive pattern 2200 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and the like. In an embodiment, the second conductive pattern 2200 may include the molybdenum (Mo), an alloy including the molybdenum, or the like in order to ensure process reliability.

A first interlayer insulating layer (e.g., ILD1 of fig. 23) may cover the second conductive pattern 2200 and be disposed on the first gate insulating layer. The first interlayer insulating layer may include an insulating substance.

Referring to fig. 19, a second active pattern 2300 may be disposed on the first interlayer insulating layer. In an embodiment, the second active pattern 2300 may include an oxide semiconductor. For example, the second active pattern 2300 may be substantially the same as the second active pattern 1300 described with reference to fig. 5.

A second gate insulating layer (e.g., GI2 of fig. 23) may cover the second active pattern 2300 and be disposed on the first interlayer insulating layer. The second gate insulating layer may include an insulating substance.

Referring to fig. 20, a third conductive pattern 2400 may be disposed on the second gate insulating layer. The third conductive pattern 2400 may include a first upper electrode 2410 and a second upper electrode 2420.

The first upper electrode 2410 may extend in the first direction D1 and be configured in an island shape. For example, the first upper electrode 2410 may function as an upper gate electrode of the fourth transistor T4. In other words, the fourth transistor T4 may have a double gate structure. For example, the first upper electrode 2410 may be in contact with a first signal wiring (e.g., 2520 of fig. 24) to be described later.

The second upper electrode 2420 may extend to the first direction D1 and be configured in an island shape. For example, the second upper electrode 2420 may function as an upper gate electrode of the third transistor T3. In other words, the third transistor T3 may have a double gate structure. For example, the second upper electrode 2420 can be in contact with a second signal wiring (e.g., 2550 of fig. 23) to be described later.

The third and fourth transistors T3 and T4 have a dual-gate structure, respectively, so that on-characteristics and/or off-characteristics of the third and fourth transistors T3 and T4 can be improved.

For example, the third conductive pattern 2400 may include a metal, an alloy, a conductive metal oxide, a transparent conductive substance, and the like. For example, the third conductive pattern 2400 may include the same substance as the second conductive pattern 2200. In one embodiment, the second and third conductive patterns 2200 and 2400 may include the molybdenum (Mo), an alloy including the molybdenum, and the like in order to ensure process reliability.

A second interlayer insulating layer (e.g., ILD2 of fig. 23) may cover the third conductive pattern 2400 and be disposed on the second gate insulating layer. The second interlayer insulating layer may include an insulating substance.

Referring to fig. 21 and 22, the fourth conductive pattern 2500 may include a gate initialization voltage connection wiring 2510, a first signal wiring 2520, a first pad 2530, a third signal wiring 2541, a second signal wiring 2550, a compensation connection pattern 2560, a high power supply voltage pattern 2570, a second pad 2580, a fourth signal wiring 2542, and an anode initialization voltage connection wiring 2590.

The gate initialization voltage connection wire 2510 may electrically connect the gate initialization voltage wire 2120 and the second active pattern 2300. The gate initialization voltage VINT may be transmitted to the first active pattern 2110 through the gate initialization voltage connection wiring 2510.

The first signal wiring 2520 may extend in the first direction D1. For example, the third gate signal GI may be supplied to the first signal wiring 2520. In one embodiment, the first signal wiring 2520 may be in contact with the first lower electrode 2130 and the first upper electrode 2410. Thus, the third gate signal GI supplied to the first signal wiring 2520 can be transmitted to the first lower electrode 2130 and the first upper electrode 2410.

The first pad 2530 may transmit the DATA voltage DATA to the first active pattern 2110. For example, the first pad 2530 may be disposed between the first active pattern 2110 and a data wire, and may be in contact with the first active pattern 2110 and the data wire.

The third signal wiring 2541 may extend to the first direction D1. For example, the first gate signal GW may be provided to the third signal wiring 2541. In an embodiment, the third signal wiring 2541 may contact the second portion 2222 of the first gate electrode 2220. Thereby, the first gate signal GW provided in the third signal wiring 2541 can be transferred to the second portion 2222.

The second signal wiring 2550 may extend to the first direction D1. For example, the second gate signal GC may be supplied to the second signal wiring 2550. In one embodiment, the second signal wiring 2550 may be in contact with the second lower electrode 2140 and the second upper electrode 2420. Thus, the second gate signal GC may be transmitted to the second lower electrode 2140 and the second upper electrode 2420.

The compensation connection pattern 2560 may electrically connect the second active pattern 2300 and the first active pattern 2110. For example, the second terminal of the third transistor T3 (e.g., a drain terminal of a third transistor) may be connected to the second terminal of the first transistor T1 (e.g., a drain terminal of a first transistor) through the compensation connection pattern 2560.

The high power voltage pattern 2570 may transmit the high power voltage ELVDD to the second active pattern 2300 and the first active pattern 2110.

The second pad 2580 may supply the driving current and the anode initialization voltage AINT to a first electrode (e.g., 2710 of fig. 23) of an organic light emitting diode, which will be described later. For example, the second pad 2580 may be disposed between the first active pattern 2110 and the first electrode, and may be in contact with the first active pattern 2110.

The fourth signal wiring 2542 may extend to the first direction D1. For example, the fourth gate signal GB may be supplied to the fourth signal wiring 2542. In one embodiment, the fourth signal wiring 2542 may be in contact with the second gate electrode 2260. Thereby, the fourth gate signal GB provided on the fourth signal wiring 2542 may be transmitted to the second gate electrode 2260.

The anode initialization voltage connection wire 2590 may electrically connect the anode initialization voltage wire 2270 and the first active pattern 2110. The anode initialization voltage AINT may be transferred to the first active pattern 2110 through the anode initialization voltage connection wiring 2590.

For example, the fourth conductive pattern 2500 may include a metal, an alloy, a conductive metal oxide, a transparent conductive substance, and the like. For example, the fourth conductive pattern 2500 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and the like. In an embodiment, in order to reduce the resistance of the fourth conductive pattern 2500, the fourth conductive pattern 2500 may include the aluminum (Al), for example, may have a Ti/Al/Ti structure in which titanium (Ti) and aluminum (Al) are alternately arranged.

A first VIA insulating layer (e.g., VIA1 of fig. 23) may cover the fourth conductive pattern 2500 and be disposed on the second interlayer insulating layer. The first via insulating layer may include an organic insulating substance. For example, the first via insulating layer may include a photoresist, an acrylic resin, a polyimide resin, an acrylic resin, or the like.

On the other hand, although not shown, a data wiring and/or a driving voltage wiring (for example, 2620 of fig. 23) may be disposed on the first via insulating layer. For example, the data wire may correspond to the data wire DL described with reference to fig. 1, and the driving voltage wire may correspond to the driving voltage wire PL described with reference to fig. 1.

In addition, a second VIA insulating layer (e.g., VIA2 of fig. 23) may cover the data wire and the driving voltage wire and be disposed on the first VIA insulating layer, and an organic light emitting element (e.g., 2700 of fig. 23) may be disposed on the second VIA insulating layer.

Fig. 23 is a sectional view taken along line VI-VI' of fig. 22.

Referring to fig. 2, 22 and 23, the pixel structure PX-4 may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the second lower electrode 2140, the first interlayer insulating layer ILD1, the second active pattern 2300, the second gate insulating layer GI2, the second upper electrode 2420, the second interlayer insulating layer ILD2, the second signal wiring 2550, the first VIA insulating layer VIA1, the driving voltage wiring 2620, the second VIA insulating layer VIA2, the first electrode 2710, the light emitting layer 2720 and the second electrode 2730 are sequentially disposed.

As described above, the second signal wiring 2550 may be in contact with the second lower electrode 2140 and the second upper electrode 2420. Thereby, the second gate signal GC supplied to the second signal wiring 2550 can be transmitted to the second lower electrode 2140 and the second upper electrode 2420.

In an embodiment, the second upper electrode 2420 may include the molybdenum (Mo), an alloy including the molybdenum, or the like, and the second signal wire 2550 may have a Ti/Al/Ti structure including the aluminum (Al). Thus, the resistance of the second signal wiring 2550 can be smaller than the resistance of the second upper electrode 2420. By implementing the wiring that transmits the second gate signal GC as the second signal wiring 2550, the transmission speed of the second gate signal GC can be increased, and the voltage level of the second gate signal GC can be maintained.

In one embodiment, the second active pattern 2300, the second lower electrode 2140, and the second upper electrode 2420 may overlap each other. Accordingly, the second active pattern 2300, the second lower electrode 2140, and the second upper electrode 2420 may constitute the third transistor T3 having a dual gate structure. By implementing the third transistor T3 as a dual gate structure, the on-characteristics and/or off-characteristics of the third transistor T3 may be improved.

Fig. 24 is a sectional view taken along line VII-VII' of fig. 22.

Referring to fig. 2, 22 and 24, the pixel structure PX-4 may have a structure in which the substrate SUB, the buffer layer BFR, the first gate insulating layer GI1, the first lower electrode 2130, the first interlayer insulating layer ILD1, the second active pattern 2300, the second gate insulating layer GI2, the first upper electrode 2410, the second interlayer insulating layer ILD2, the first signal wiring 2520, the first VIA insulating layer VIA1, the driving voltage wiring 2620, the second VIA insulating layer VIA2, the first electrode 2710, the light-emitting layer 2720 and the second electrode 2730 are sequentially disposed.

As described above, the first signal wiring 2520 may be in contact with the first lower electrode 2130 and the first upper electrode 2410. Thus, the third gate signal GI supplied to the first signal wiring 2520 can be transmitted to the first lower electrode 2130 and the first upper electrode 2410.

In one embodiment, the first upper electrode 2410 may include the molybdenum (Mo), an alloy including the molybdenum, or the like, and the first signal wiring 2520 may have a Ti/Al/Ti structure including the aluminum (Al). Thus, the resistance of the first signal wiring 2520 may be smaller than that of the first upper electrode 2410. By implementing the wiring for transmitting the third gate signal GI as the first signal wiring 2520, the transmission speed of the third gate signal GI can be increased, and the voltage level of the third gate signal GI can be maintained.

In one embodiment, the second active pattern 2300, the first lower electrode 2130, and the first upper electrode 2410 may overlap each other. Accordingly, the second active pattern 2300, the first lower electrode 2130, and the first upper electrode 2410 may constitute the fourth transistor T4 having a dual gate structure. By implementing the fourth transistor T4 as a dual gate structure, the on-characteristics and/or off-characteristics of the fourth transistor T4 may be improved.

Although the foregoing has been described with reference to exemplary embodiments of the present invention, it will be understood by those having ordinary skill in the art that various changes and modifications may be made therein without departing from the spirit and scope of the present invention as set forth in the following claims.

(availability in industry)

The present invention can be applied to a display device and an electronic apparatus including the same. For example, the present invention may be applicable to high resolution smart phones, cell phones, smart tablets, smart watches, tablet computers, navigation systems for vehicles, televisions, computer displays, notebook computers, and the like.

Claims (10)

1. A display device, comprising:

a substrate;

a first active pattern disposed on the substrate;

a second active pattern disposed on the first active pattern;

a first upper electrode disposed on the second active pattern and having an island shape; and

and a first signal wiring disposed on the first upper electrode, electrically connected to the first upper electrode, and having a resistance smaller than that of the first upper electrode.

2. The display device according to claim 1,

the display device further includes:

a first lower electrode disposed between the first active pattern and the second active pattern and having an island shape,

the first signal wiring is electrically connected to the first lower electrode.

3. The display device according to claim 2,

the first signal wiring is in contact with the first lower electrode and the first upper electrode.

4. The display device according to claim 2,

the first signal wiring is in contact with the first upper electrode.

5. The display device according to claim 4,

the first upper electrode is in contact with the first lower electrode.

6. The display device according to claim 2,

the first signal wiring is in contact with the first lower electrode.

7. The display device according to claim 6,

the first lower electrode is in contact with the first upper electrode.

8. The display device according to claim 1,

the display device further includes:

a first lower electrode disposed in the same layer as the first active pattern and having an island shape,

the first signal wiring is in contact with the first lower electrode and the first upper electrode.

9. The display device according to claim 1,

the first upper electrode and the first signal wiring line contain metal substances different from each other.

10. The display device according to claim 1,

the first active pattern includes a polysilicon,

the second active pattern includes an oxide semiconductor.

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