CN115588661A - Semiconductor structure and capacitor structure forming method - Google Patents
Semiconductor structure and capacitor structure forming method Download PDFInfo
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- CN115588661A CN115588661A CN202211340286.9A CN202211340286A CN115588661A CN 115588661 A CN115588661 A CN 115588661A CN 202211340286 A CN202211340286 A CN 202211340286A CN 115588661 A CN115588661 A CN 115588661A
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The embodiment of the disclosure provides a method for forming a semiconductor structure and a capacitor structure, wherein the method comprises the following steps: providing a first substrate; wherein the first substrate comprises in sequence: the device comprises a bottom supporting layer, a first sacrificial layer and a mask layer, wherein the first sacrificial layer is provided with a lower electrode penetrating through the bottom supporting layer; the surface of the lower electrode is flush with the mask layer and is connected with the capacitance contact pad in the bottom supporting layer; etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer; forming a middle support layer and a top support layer on the second sacrificial layer to form a capacitor structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, but not exclusively, to a method for forming a semiconductor structure and a capacitor structure.
Background
Dynamic Random Access Memory (DRAM) includes a transistor and capacitor structure. In order to improve the capacitance of the capacitor structure, the capacitor often has a high aspect ratio, which requires a structure of two sacrificial layers and three supporting layers to realize the stable structure of the capacitor. However, the conventional process is difficult to satisfy the smoothness of the vertical and sidewall of the capacitor profile, and is liable to affect the stability of the capacitor structure.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a forming method of a capacitor structure.
In a first aspect, an embodiment of the present disclosure provides a method for forming a capacitor structure, where the method includes: providing a first substrate; wherein the first substrate comprises in sequence: the bottom support layer, the first sacrificial layer with a lower electrode penetrating through and the mask layer; the surface of the lower electrode is flush with the mask layer and is connected with the capacitance contact pad in the bottom supporting layer; etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer; forming a middle support layer and a top support layer on the second sacrificial layer to form a capacitor structure.
In some embodiments, the providing a first substrate comprises: providing a second substrate; wherein the second substrate comprises in sequence: the bottom supporting layer, the initial first sacrificial layer and the initial mask layer; etching the initial mask layer and the initial first sacrificial layer by a first pattern which is the same as the pattern of the capacitor hole to form a mask layer with a capacitor hole and a first sacrificial layer; and forming the lower electrode after depositing the electrode material in the capacitor hole.
In some embodiments, etching the initial mask layer and the initial first sacrificial layer in a first pattern identical to a capacitor hole pattern to form a mask layer and a first sacrificial layer having a capacitor hole comprises: etching the initial mask layer by a first pattern which is the same as the pattern of the capacitor hole to form a mask layer with the first pattern; and etching the initial first sacrificial layer by using the mask layer with the first pattern to form a first sacrificial layer with the capacitor hole.
In some embodiments, etching the initial mask layer in a first pattern identical to the capacitor hole pattern to form a mask layer having the first pattern includes: forming a composite mask layer with a second pattern on the initial mask layer; and patterning the initial mask layer based on the composite mask layer with the second pattern to form a mask layer with the first pattern.
In some embodiments, etching the initial first sacrificial layer with the mask layer having the first pattern to form a first sacrificial layer having the capacitor hole includes: forming a first electrode which is flush with the mask layer in the pores of the first pattern; and etching the initial first sacrificial layer by adopting a metal auxiliary chemical etching process to form a first sacrificial layer with the capacitor hole, wherein the first electrode is connected with the capacitor contact pad to form a second electrode along with consumption of the initial first sacrificial layer.
In some embodiments, forming a first electrode flush with the mask layer in the apertures of the first pattern comprises: depositing the electrode material in the pores of the first pattern, forming an initial first electrode; and etching the initial first electrode by adopting a dry etching process, a wet etching process or a chemical mechanical grinding process to form the first electrode which is flush with the mask layer.
In some embodiments, after forming the second electrode, forming the lower electrode after depositing an electrode material in the capacitive hole includes: depositing the electrode material in the capacitor hole after the second electrode is formed; and removing redundant electrode materials by adopting the dry etching process, the wet etching process or the chemical mechanical grinding process to form a lower electrode which is flush with the mask layer.
In some embodiments, etching the first sacrificial layer to a predetermined first thickness to form a second sacrificial layer includes: removing the mask layer by adopting a dry etching process or a wet etching process; and etching the first sacrificial layer by adopting a dry etching process or a wet etching process to form the second sacrificial layer with a first preset thickness.
In some embodiments, on the second sacrificial layer, forming an intermediate support layer comprises: covering the second sacrificial layer and the lower electrode with an intermediate support material layer; forming a spin-on hard mask layer on the intermediate support material layer; and simultaneously removing the middle support material layer and the spin-on hard mask layer on the top and the side wall of the lower electrode to form the middle support layer.
In some embodiments, forming a middle support layer and a top support layer on the second sacrificial layer to form a capacitor structure comprises: forming a third sacrificial layer on the middle support layer; wherein a top surface of the third sacrificial layer is lower than a top surface of the lower electrode; forming the top support layer on the third sacrificial layer; patterning the top support layer, forming a first opening in the top support layer, and removing the second sacrificial layer and the third sacrificial layer through the first opening; and sequentially forming a dielectric layer and an upper electrode on the lower electrode to obtain the capacitor structure.
In some embodiments, the second sacrificial layer is a different material than the third sacrificial layer; the material of the third sacrificial layer is oxide.
In some embodiments, forming a third sacrificial layer on the middle support layer comprises: forming an initial third sacrificial material layer on the middle support layer, wherein a top surface of the initial third sacrificial material layer is higher than a top surface of the lower electrode; removing part of the initial third sacrificial material layer by adopting a chemical mechanical polishing process to form an initial third sacrificial layer which is flush with the top surface of the lower electrode; and etching the initial third sacrificial layer by adopting a dry etching process or a wet etching process to form a third sacrificial layer lower than the top surface of the lower electrode.
In some embodiments, patterning the top support layer, forming a first opening in the top support layer, removing the second sacrificial layer and the third sacrificial layer through the first opening, comprises: etching the top support layer, the middle support layer, the second sacrificial layer and the third sacrificial layer between any adjacent lower electrodes to form the first opening; and removing the second sacrificial layer and the third sacrificial layer through the first opening by adopting a wet etching process.
In a second aspect, embodiments of the present disclosure provide a semiconductor structure, including: a capacitor structure formed using the method described in any of the embodiments above.
In the embodiment of the present disclosure, first, a first substrate is provided; wherein, first basement includes in proper order: the bottom support layer, the first sacrificial layer with a lower electrode penetrating through and the mask layer; the surface of the lower electrode is flush with the mask layer and is connected with the capacitance contact pad in the bottom supporting layer, so that the short circuit between the adjacent capacitance contact pads can be reduced; secondly, etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer, so that a relatively flat surface can be provided for the subsequent formation of a middle supporting layer; finally, a middle support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure. As can be seen from the above, the embodiments of the present disclosure form the lower electrode first, and then form the middle supporting layer and the top supporting layer, that is, the embodiments of the present disclosure provide a new method for forming the capacitor structure; in addition, the first substrate comprises the first sacrificial layer and the mask layer which are penetrated by the lower electrode, namely, only the first sacrificial layer made of a single material is required to be etched when the capacitor hole is etched, and the supporting layer and the sacrificial layer made of different materials are not required to be etched simultaneously, so that the formed capacitor hole is vertical and smooth, and a capacitor structure with a vertical section and a smooth side wall and an excellent appearance can be obtained.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
FIG. 1 is a schematic diagram illustrating a process for forming a capacitor structure according to the related art;
fig. 2 is a schematic implementation flow diagram of a method for forming a capacitor structure according to an embodiment of the disclosure;
fig. 3 to 18 are schematic structural views illustrating a forming process of a capacitor structure according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order not to obscure the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "8230;" \8230 "", "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," 8230; \8230 ";," "directly adjacent," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Fig. 1 is a schematic diagram of a capacitor structure forming process in the related art, wherein the capacitor structure forming process includes the following steps:
referring first to the left drawing of fig. 1, the substrate comprises, from bottom to top: the stacked structure 10, the first mask layer 116, and the patterned second mask layer 117, wherein the stacked structure 10 includes a bottom support layer 111, a first sacrificial layer 112, a middle support layer 113, a second sacrificial layer 114, and a top support layer 115 in this order; next, the first mask layer 116 and the stacked structure 10 are etched through the patterned second mask layer 117 to form a capacitor hole (not shown). Thereafter, the remaining first masking layer 116 over the top support layer 115 is etched back, exposing the top support layer. Next, electrode material is deposited in the capacitor holes and etched back above the top surface of the top support layer 115 to form the bottom electrode. Finally, between any adjacent lower electrodes, the top support layer 115, the second sacrificial layer 114, the middle support layer 113 and the first sacrificial layer 112 are etched to form an opening 118 as shown in the right drawing of fig. 1; based on the opening 118, removing the first sacrificial layer 112 and the second sacrificial layer 114 by wet etching; finally, a support structure is formed as shown in the right drawing of fig. 1, and then a dielectric layer material and an upper electrode material are deposited on the lower electrode and the support structure to form a capacitor structure.
In the related art, a dry etching process or a wet etching process is generally adopted to etch a laminated structure to form a capacitor hole, and the laminated structure comprises a sacrificial layer and a middle supporting layer which are made of different materials, so that the etched materials are different and the number of layers is large in the etching process, the depth-to-width ratio of the capacitor hole is large, the outline of the capacitor hole is difficult to be vertical, and the side wall is rough, so that the obtained capacitor has a poor appearance structure.
In view of this, the present disclosure provides a method for forming a capacitor structure, and referring to fig. 2, the method includes steps S201 to S203, where:
step S201, providing a first substrate; wherein, first basement includes in proper order: the device comprises a bottom supporting layer, a first sacrificial layer and a mask layer, wherein the first sacrificial layer is provided with a lower electrode penetrating through the bottom supporting layer; the surface of the lower electrode is flush with the mask layer and is connected with the capacitance contact pad in the bottom supporting layer;
here, the material of the bottom support layer may include at least one of: silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon boronitride. The material of the first sacrificial layer may include silicon oxide, phosphosilicate Glass (PSG), borophosphosilicate Glass (BPSG), or fluorosilicate Glass (FSG), polysilicon (Poly), silicon (Si), germanium (Ge), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), silicon carbide (SiC), or the like.
The mask layer can be of a single-layer structure or a double-layer structure; wherein, the material of each layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride and titanium. In the following embodiments, a mask layer having a single-layer structure and a silicon oxide layer will be described as an example.
The material of the lower electrode may include a metal, a metal nitride, or a metal silicide, for example, titanium nitride (TiN). In some embodiments, the bottom electrode may be formed by depositing a bottom electrode material in the capacitor hole through any suitable Deposition process, such as a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, a spin-on process, a coating process, a thin film process, or the like.
In other embodiments, the lower electrode may be formed by forming a part of the lower electrode while forming the capacitor hole through a metal-assisted chemical etching process, and then depositing a lower electrode material in the capacitor hole, and the method for forming the lower electrode according to the embodiments of the present disclosure is not limited.
The capacitor contact pad is used for electrically connecting the drain electrode of the transistor and the capacitor structure, and a plurality of capacitor holes formed subsequently can expose the plurality of capacitor contact pads, so that a plurality of capacitor structures corresponding to the plurality of capacitor contact pads can be formed.
Step S202, etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer;
here, step S202 is a process of thinning the first sacrificial layer, which may reserve a space for the middle support layer and the top support layer. In implementation, the first sacrificial layer may be etched by a dry or wet etching process to form a second sacrificial layer having a first predetermined thickness, so as to provide a relatively flat plane for forming a middle support layer on the second sacrificial layer. The preset first thickness can be set according to the thickness of the first sacrificial layer and the etching precision.
Here, the etching gas used in the dry etching process may include: trifluoromethane (CHF) 3 ) Carbon tetrafluoride (CF) 4 ) Hydrogen bromide (HBr) and chlorine (Cl) 2 ). In other entitiesIn one embodiment, the etching gas may also include other fluorocarbon based gases, such as difluoromethane (CH) 2 F 2 ) Octafluoropropane (C) 3 F 8 ) Perfluorobutadiene (C) 4 F 6 ) Octafluorocyclobutane (C) 4 F 8 ) And octafluorocyclopentene (C) 5 F 8 ) One or more of them. The etching solution used in the wet etching process may include a diluted hydrofluoric acid solution, wherein a volume ratio of hydrogen fluoride to deionized water in the diluted hydrofluoric acid solution is 1.
Step S203, forming a middle supporting layer and a top supporting layer on the second sacrificial layer to form a capacitor structure;
here, the bottom support layer, the middle support layer and the top support layer are used to form a support structure for supporting the capacitor structure, and in implementation, the material of the middle support layer and the top support layer may be the same as that of the bottom support layer, for example, all three layers are silicon nitride.
In practice, the middle support layer and the top support layer may be formed by any suitable deposition process, such as, for example, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a plasma chemical vapor deposition process, a spin-on process, a coating process, a thin film process, or the like.
After forming the middle support layer and the top support layer to form the support structures, it is also necessary to deposit a dielectric layer material and an upper electrode material on the lower electrodes and the support structures to form dielectric layers and upper electrodes to form the capacitor structure.
In the embodiment of the present disclosure, first, a first substrate is provided; wherein, first basement includes in proper order: the device comprises a bottom supporting layer, a first sacrificial layer and a mask layer, wherein the first sacrificial layer is provided with a lower electrode penetrating through the bottom supporting layer; the surface of the lower electrode is flush with the mask layer and is connected with the capacitance contact pad in the bottom supporting layer, so that the short circuit between the adjacent capacitance contact pads can be reduced; secondly, etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer, so that a relatively flat surface can be provided for the subsequent formation of a middle supporting layer; finally, a middle support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure. As can be seen from the above, the embodiments of the present disclosure form the lower electrode first, and then form the middle supporting layer and the top supporting layer, that is, the embodiments of the present disclosure provide a new method for forming the capacitor structure; in addition, the first substrate comprises the first sacrificial layer and the mask layer which are penetrated by the lower electrode, namely, only the first sacrificial layer made of a single material is required to be etched when the capacitor hole is etched, and the supporting layer and the sacrificial layer made of different materials are not required to be etched simultaneously, so that the formed capacitor hole is vertical and smooth, and a capacitor structure with a vertical section and a smooth side wall and an excellent appearance can be obtained.
A method for forming a capacitor structure according to an embodiment of the present disclosure will be described in detail with reference to fig. 3 to 18.
First, referring to fig. 3 to 8, step S201 is performed to provide the first substrate 20. Wherein the first substrate 20 includes, in order: a bottom support layer 21, a first sacrificial layer 22 having a lower electrode 26 therethrough, and a mask layer 23. The surface of the lower electrode 26 is flush with the mask layer 23 and is connected to the capacitor contact pad 21a on the bottom support layer 21.
In some embodiments, the first substrate may be formed by steps S301 to S303, wherein:
step S301, providing a second substrate; wherein, the second basement includes in proper order: the mask layer comprises a bottom supporting layer, an initial first sacrificial layer and an initial mask layer;
step S302, etching the initial mask layer and the initial first sacrificial layer by a first pattern which is the same as the pattern of the capacitor hole to form a mask layer with a capacitor hole and a first sacrificial layer;
here, the capacitor hole pattern may be a plurality of capacitor holes arranged in an array, and the plurality of capacitor holes correspond to the capacitor contact pads in the bottom supporting layer. Step S302 is a process of transferring the first pattern to the initial mask layer and the initial first sacrificial layer, and in implementation, the first pattern may be transferred at one time or may be transferred twice, for example, the first pattern is first transferred to the initial mask layer to form a mask layer with a first pattern, and then the first pattern in the mask layer is transferred to the initial first sacrificial layer to form a first sacrificial layer with a capacitor hole.
Step S303, after depositing electrode material in the capacitor hole, forming a lower electrode.
In some embodiments, the implementation of step S302 may include step S3021 and step S3022, wherein:
step S3021, etching the initial mask layer by using a first pattern identical to the pattern of the capacitor hole to form a mask layer with the first pattern;
step S3022, etching the initial first sacrificial layer with the mask layer having the first pattern to form a first sacrificial layer having a capacitor hole.
In some embodiments, the implementation of step S3021 may include step S311 and step S312, wherein:
step S311, forming a composite mask layer having a second pattern on the initial mask layer;
here, the composite mask layer may include a hard mask layer, an Anti-reflection layer, and the like, and the Anti-reflection layer may be a stack of one or both of a Bottom Anti-reflection Coating (BARC) and a Dielectric Anti-reflection Coating (DARC).
In step S312, the initial mask layer is patterned based on the composite mask layer with the second pattern to form a mask layer with the first pattern.
Here, the pattern of the composite mask layer may be transferred into the initial mask layer using a Self-aligned Double Patterning (SADP) technique to form a mask layer having a first pattern. Therefore, spatial frequency doubling of the photoetching pattern can be realized, so that capacitor holes with smaller space are formed, and further micro-shrinkage is realized.
First, referring to fig. 3, a second substrate 20a is provided, the second substrate 20a sequentially including: a bottom support layer 21 comprising a capacitor contact pad 21a, an initial first sacrificial layer 22a and an initial mask layer 23 a. Referring to fig. 3 and 4, the initial mask layer 23a is etched by a wet or dry etching process with a first pattern that is the same as the capacitor hole pattern, so as to form a mask layer 23 with the first pattern; the initial first sacrificial layer 22a is then etched with a mask layer 23 having a first pattern to form a first sacrificial layer 22 having a capacitor hole therethrough, exposing the capacitor contact pad 21a, thereby forming a capacitor hole 25 through the mask layer 23 and the first sacrificial layer 22 as shown in fig. 5, thereby forming the first substrate 20.
Next, referring to fig. 5, when the electrode material is deposited in the capacitor hole 25, in practice, the deposited electrode material layer may be higher than the mask layer 23 or uneven deposited electrode material, so that the electrode material layer may be etched by a dry etching process (for example, a plasma etching process, a reactive ion etching process or an ion milling process) or a wet etching process (for example, a strong acid etching process using concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.), or the electrode material may be planarized by Chemical Mechanical Polishing (CMP), so as to form the lower electrode 26 connected to the capacitor contact pad 21a as shown in fig. 6, as can be seen from fig. 6: the top surface of the lower electrode 26 is flush with the top surface of the mask layer 23.
In some embodiments, the step S3022 "etching the initial first sacrificial layer with the mask layer having the first pattern to form the first sacrificial layer having the capacitor hole" may include steps S321 and S322, wherein:
step S321, forming a first electrode flush with the mask layer in the hole of the first pattern;
here, the first electrode may be used as a metal catalyst in a metal-assisted chemical etching process, and thus, the material of the first electrode may include at least one of: silver, platinum, gold, titanium nitride, copper, plutonium, palladium, titanium oxide, titanium carbide, tungsten. The formation process of the first electrode may be any suitable deposition process, which is not limited by the embodiments of the disclosure.
In some embodiments, the implementation of step S321 may include step S3211 and step S3212, wherein:
step S3211, depositing an electrode material in the pores of the first pattern to form an initial first electrode;
step S3212, etching the initial first electrode using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form a first electrode flush with the mask layer.
In the embodiment of the disclosure, an electrode material is deposited in the pores of the first pattern to form an initial first electrode, and then the initial first electrode is etched by adopting a dry etching process, a wet etching process or a chemical mechanical polishing process to form the first electrode which is flush with the mask layer, so that the top surface of the first electrode can be relatively flat, a flat surface is provided for a lower electrode formed by subsequent deposition of the electrode material, the interface bonding force between the electrode materials deposited twice can be improved, and the condition of breakage of the lower electrode is reduced.
Step S322, etching the initial first sacrificial layer by using a metal assisted chemical etching process to form a first sacrificial layer having a capacitor hole, wherein the first electrode is connected to the capacitor contact pad to form a second electrode as the initial first sacrificial layer is consumed.
Here, the metal-assisted chemical etching process is different from a conventional dry etching technique, which is biased to wet etching, and is capable of forming a semiconductor structure such as an anisotropic silicon structure. Metal-assisted chemical etching is the etching of semiconductors by conducting materials such as metals as catalysts, so that the roughness of the sidewalls is related to the roughness of the metal catalyst itself used, without creating a large roughness during the etching process. The metal-assisted chemical etching only reacts on the surface of the metal catalyst and the semiconductor, and the over-etching phenomenon cannot occur, so that the generated pattern is consistent with the shape of the metal catalyst, extremely high etching precision is provided, and the patterns can be transferred in the same way. Therefore, the conditions of non-perpendicularity and rough inner wall of the capacitor hole can be reduced to the greatest extent; meanwhile, the method can prevent the capacitor holes from being influenced by other factors in the process of forming the capacitor holes, and finally form the capacitor holes with ideal appearance. In addition, the metal-assisted chemical etching process can also form a capacitor hole with a smaller size, thereby realizing micro-shrinkage.
Referring to fig. 4, in the pores of the first pattern, an electrode material is deposited to form an initial first electrode (not shown), the initial first electrode is etched using a dry etching process (e.g., a plasma etching process, a reactive ion etching process, or an ion milling process) or a wet etching process (e.g., a strong acid etching process using concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, or the like), or a chemical mechanical polishing process may be used to form a first electrode 261 flush with the mask layer as shown in fig. 7; then, the initial first sacrificial layer 22a is etched using a metal assisted chemical etching process to form the first sacrificial layer 22 having the capacitor hole 25 as shown in fig. 8, wherein the first electrode 261 is connected to the capacitor contact pad 21a as the initial first sacrificial layer 22a is consumed to form the second electrode 262 as shown in fig. 8. That is, when the capacitor hole 25 is formed, the first electrode 261, which is originally a metal catalyst, drops to the bottom of the capacitor hole 25 with the consumption of the initial first sacrificial layer 22a, and the second electrode 262 is formed as a part of the lower electrode to be formed later.
In the embodiment of the disclosure, the first electrode flush with the mask layer is formed in the gap of the first pattern, then the initial first sacrificial layer is etched by adopting a metal-assisted chemical etching process, and the capacitor hole is formed while a part of the lower electrode, namely the second electrode, is formed, so that the size of the obtained capacitor hole is smaller, the side wall of the capacitor hole is more vertical and smooth, namely the appearance structure of the capacitor hole is more excellent, and the appearance of the capacitor structure can be further more excellent.
In some embodiments, the implementation of the step S303 "forming the lower electrode after depositing the electrode material in the capacitive hole" after forming the second electrode may include steps S3031 and S3032, wherein:
step 3031, depositing electrode material in the capacitor hole after the second electrode is formed;
step S3032, a dry etching process, a wet etching process or a chemical mechanical polishing process is used to remove the excess electrode material, so as to form a lower electrode flush with the mask layer.
Referring to fig. 8, first, an electrode material is deposited in the capacitor hole 25 where the second electrode 262 is formed; then, a dry etching process, a wet etching process or a chemical mechanical polishing process is used to remove the excess electrode material, so as to form the lower electrode 26 flush with the surface of the mask layer as shown in fig. 6.
As can be seen from the above description, the lower electrode 26 can be formed in at least two ways, among which: mode 1: etching the initial first sacrificial layer 22a with a mask layer 23 having a first pattern to form a capacitor hole 25, and then depositing an electrode material in the capacitor hole to form a lower electrode 26; mode 2: depositing electrode material in the gaps of the first pattern to form a first electrode 261, etching the initial first sacrificial layer 22a by using a metal assisted chemical etching process, forming a capacitor hole 25 while dropping the first electrode 261 to the bottom of the capacitor hole 25 to form a second electrode 262, and finally depositing electrode material again to form a lower electrode 26.
Referring to fig. 9 and 10, step S202 is performed to etch the first sacrificial layer 22 to a predetermined first thickness, and form a second sacrificial layer 27.
In some embodiments, the step S202 "etching the first sacrificial layer to a predetermined first thickness and forming the second sacrificial layer" includes a step S2021 and a step S2022, where:
step S2021, removing the mask layer by adopting a dry etching process or a wet etching process;
step S2022, the first sacrificial layer is etched by a dry etching process or a wet etching process to form a second sacrificial layer having a first predetermined thickness.
In implementation, referring to fig. 9, the mask layer 23 (refer to fig. 6) is removed by a dry or wet etching process to expose the first sacrificial layer 22; then, the first sacrificial layer 22 is etched by using a dry etching process (e.g., a plasma etching process, a reactive ion etching process, or an ion milling process) or a wet etching process (e.g., a strong acid etching process using concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, or the like), so as to form a second sacrificial layer 27 having a first predetermined thickness as shown in fig. 10.
In the embodiment of the disclosure, the mask layer is removed after the lower electrode is formed, and compared with a process flow of removing the mask layer immediately after the capacitor hole is formed in the related art, the situation that a byproduct (such as a polymer) generated when the mask layer is removed falls into the capacitor hole can be reduced, so that the quality of the lower electrode formed subsequently can be improved.
Referring to fig. 11 to 18, step S203 is performed to form the middle support layer 28 and the top support layer 31 on the second sacrificial layer 27 to form the capacitor structure 35.
In some embodiments, the implementation of forming the intermediate support layer on the second sacrificial layer may include steps S231 to S233, wherein:
step S231, covering the middle support material layer on the second sacrificial layer and the lower electrode;
step S232, forming a spin-on hard mask layer on the middle support material layer;
in step S233, the middle support material layer and the spin-on hard mask layer on the top and the sidewall of the lower electrode are removed simultaneously to form a middle support layer.
First, referring to fig. 11, an intermediate support material layer 28a is covered on the second sacrificial layer 27 and the lower electrode 26; next, a spin-on hard mask layer 29 is formed on the intermediate support material layer 28a; finally, the middle support material layer 28a and the spin-on hard mask layer 29 on the top and the sidewalls of the lower electrode 26 are removed simultaneously to form the middle support layer 28 as shown in fig. 12.
In the embodiment of the present disclosure, first, a middle support material layer is covered on the second sacrificial layer and the lower electrode; then, a spin-on hard mask layer is formed on the intermediate support material layer, so that the spin-on hard mask layer can support the intermediate support material layer, the situation that the support intermediate support material layer collapses is reduced, and the influence on a subsequently formed intermediate support layer is further reduced; and finally, removing the middle supporting material layer and the spin-on hard mask layer on the top and the side wall of the lower electrode to form a middle supporting layer. Therefore, the middle support layer formed in the embodiment of the disclosure has a good appearance, and the thickness meets the preset thickness.
In some embodiments, the implementation of step S203 may include steps S2031 to S2034, wherein:
step S2031, forming a third sacrificial layer on the middle support layer; wherein a top surface of the third sacrificial layer is lower than a top surface of the lower electrode;
here, the material of the third sacrificial layer may be the same as that of the second sacrificial layer, for example, the material of the third sacrificial layer and the material of the second sacrificial layer are both polysilicon; the material of the third sacrificial layer may also be different from the material of the second sacrificial layer, for example, the material of the third sacrificial layer is an oxide, the material of the second sacrificial layer is polysilicon, and the material of the second sacrificial layer and the material of the third sacrificial layer are not limited in this disclosure.
In practice, in some embodiments, the thickness of the sacrificial layer may be controlled by controlling the deposition process parameters, for example, by controlling the deposition time and deposition rate to form a third sacrificial layer of a predetermined thickness; wherein the top surface of the third sacrificial layer with a predetermined thickness is lower than the top surface of the lower electrode. In other embodiments, an initial third sacrificial material layer may be deposited completely covering the lower electrode, the middle support layer, and then etched back to form a third sacrificial layer of a predetermined thickness.
In some embodiments, the implementation of step S2031 may include steps S2311 to S2313, wherein:
step S2311, forming an initial third sacrificial material layer on the middle support layer, wherein a top surface of the initial third sacrificial material layer is higher than a top surface of the lower electrode;
here, the material of the initial third sacrificial material layer may include: silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof.
Step S2312, removing a portion of the initial third sacrificial material layer by a chemical mechanical polishing process to form an initial third sacrificial layer flush with the top surface of the lower electrode;
step S2313, the initial third sacrificial layer is etched by a dry or wet etching process to form a third sacrificial layer lower than the top surface of the lower electrode.
In the embodiment of the disclosure, an initial third sacrificial material layer with a top surface higher than that of the lower electrode is deposited on the middle support layer, and then a part of the initial third sacrificial material layer is removed by a chemical mechanical polishing process to form an initial third sacrificial layer which is flush with the top surface of the lower electrode, so that an initial third sacrificial layer with a relatively flat top surface can be formed; and finally, etching the initial third sacrificial layer by adopting a dry etching process or a wet etching process to form a third sacrificial layer lower than the top surface of the lower electrode. Because the top surface of the initial third sacrificial layer is relatively flat, the top surface of the third sacrificial layer formed after etching is relatively flat and has good quality, and an excellent plane is provided for the formation of the top supporting layer, so that the supporting effect of the subsequently formed supporting structure can be improved.
Step S2032, forming a top supporting layer on the third sacrificial layer;
step S2033, patterning the top supporting layer, forming a first opening in the top supporting layer, and removing the second sacrificial layer and the third sacrificial layer through the first opening;
in some embodiments, the implementation of step S2033 may include step S2331 and step S2332, wherein:
step S2331, etching a top supporting layer, a middle supporting layer, a second sacrificial layer and a third sacrificial layer between any adjacent lower electrodes to form a first opening;
step S2332, a wet etching process is used to etch the second sacrificial layer and the third sacrificial layer through the first opening.
It should be noted that, since all the sacrificial layers located between the bottom supporting layer and the top supporting layer are communicated, in the subsequent process of removing the sacrificial layer, the first opening may be formed by one dry etching, and all the sacrificial layers may be removed by one wet etching, so that the process flow of forming the capacitor may be simplified.
Step S2034, a dielectric layer and an upper electrode are sequentially formed on the lower electrode to obtain a capacitor structure.
Referring to fig. 13, an initial third sacrificial material layer 30a is formed on the middle support layer 28, wherein a top surface of the initial third sacrificial material layer 30a is higher than a top surface of the lower electrode 26; next, referring to fig. 13 and 14 together, a chemical mechanical polishing process is used to remove a portion of the initial third sacrificial material layer 30a, forming an initial third sacrificial layer 30b flush with the top surface of the lower electrode 26; finally, referring to fig. 14 and 15 together, the initial third sacrificial layer 30b is etched using a dry etching process (e.g., a plasma etching process, a reactive ion etching process, or an ion milling process) or a wet etching process (e.g., a strong acid etching process using concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, or the like) to form the third sacrificial layer 30 below the top surface of the lower electrode 26.
Referring to fig. 16, a top support material is deposited on the third sacrificial layer 30, forming a top support layer 31. Here, the top surface of the top support layer 31 may be flush with the top surface of the lower electrode 26 or may be higher than the top surface of the lower electrode 26. Between any adjacent lower electrodes 26, the top support layer 31, the middle support layer 28, the second sacrificial layer 27 and the third sacrificial layer 30 are etched to form first openings 32 as shown in fig. 17. The second sacrificial layer 27 and the third sacrificial layer 30 are etched through the first opening 32 by a wet etching process (for example, etching with strong acid such as concentrated sulfuric acid, hydrofluoric acid, and concentrated nitric acid), and all of the second sacrificial layer 27 and the third sacrificial layer 30 are removed, thereby forming a support structure as shown in fig. 17, which includes the top support layer 31, the middle support layer 28, and the bottom support layer 21 remaining after etching the first opening.
With continued reference to fig. 17, after removal of the second sacrificial layer 27 and the third sacrificial layer 30, a dielectric layer 33 and an upper electrode 34 are sequentially formed on the top support layer 31 and the middle support layer 28, resulting in a capacitor structure 35 as shown in fig. 18.
Embodiments of the present disclosure also provide a semiconductor structure, including: the capacitor structure formed by the forming method in any one of the above embodiments. Referring to fig. 18, the capacitor structure 35 includes a lower electrode 26, a dielectric layer 33, and an upper electrode 34. Because the capacitor structure is formed by adopting the forming method provided by the embodiment of the disclosure, the cross section of the capacitor structure is vertical, and the side wall of the capacitor structure is smooth, namely the appearance of the capacitor structure is excellent.
In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, for example, the division of the unit is only one logic function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The features disclosed in the several method or structure embodiments provided in this disclosure may be combined in any combination to arrive at a new method embodiment or structure embodiment without conflict.
The above description is only a few embodiments of the present disclosure, but the scope of the embodiments of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the embodiments of the present disclosure, and all the changes or substitutions should be covered by the scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.
Claims (14)
1. A method of forming a capacitor structure, the method comprising:
providing a first substrate; wherein the first substrate comprises in sequence: the bottom support layer, the first sacrificial layer with a lower electrode penetrating through and the mask layer; the surface of the lower electrode is flush with the mask layer and is connected with the capacitance contact pad in the bottom supporting layer;
etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer;
forming a middle support layer and a top support layer on the second sacrificial layer to form a capacitor structure.
2. The method of forming as claimed in claim 1, wherein said providing a first substrate comprises:
providing a second substrate; wherein the second substrate comprises in sequence: the bottom supporting layer, the initial first sacrificial layer and the initial mask layer;
etching the initial mask layer and the initial first sacrificial layer by a first pattern which is the same as the pattern of the capacitor hole to form a mask layer with a capacitor hole and a first sacrificial layer;
and forming the lower electrode after depositing the electrode material in the capacitor hole.
3. The method of claim 2, wherein etching the initial masking layer and the initial first sacrificial layer in a first pattern that is the same as a capacitive via pattern to form a masking layer and a first sacrificial layer having a capacitive via comprises:
etching the initial mask layer by a first pattern which is the same as the pattern of the capacitor hole to form a mask layer with the first pattern;
and etching the initial first sacrificial layer by using the mask layer with the first pattern to form a first sacrificial layer with the capacitor hole.
4. The method of claim 3, wherein etching the initial mask layer in a first pattern identical to the capacitor hole pattern to form a mask layer having the first pattern comprises:
forming a composite mask layer with a second pattern on the initial mask layer;
and patterning the initial mask layer based on the composite mask layer with the second pattern to form a mask layer with the first pattern.
5. The method of claim 3, wherein etching the initial first sacrificial layer with the mask layer having the first pattern to form the first sacrificial layer having the capacitor hole comprises:
forming a first electrode which is flush with the mask layer in the pores of the first pattern;
and etching the initial first sacrificial layer by adopting a metal auxiliary chemical etching process to form a first sacrificial layer with the capacitor hole, wherein the first electrode is connected with the capacitor contact pad to form a second electrode along with consumption of the initial first sacrificial layer.
6. The method of claim 5, wherein forming a first electrode flush with the mask layer in the apertures of the first pattern comprises:
depositing the electrode material in the pores of the first pattern, forming an initial first electrode;
and etching the initial first electrode by adopting a dry etching process, a wet etching process or a chemical mechanical grinding process to form the first electrode which is flush with the mask layer.
7. The method of forming as claimed in claim 6, wherein forming the lower electrode after depositing electrode material in the capacitive hole after forming the second electrode comprises:
depositing the electrode material in the capacitor hole after the second electrode is formed;
and removing redundant electrode materials by adopting the dry etching process, the wet etching process or the chemical mechanical grinding process to form a lower electrode which is flush with the mask layer.
8. The method of any of claims 1-7, wherein etching the first sacrificial layer to a predetermined first thickness to form a second sacrificial layer comprises:
removing the mask layer by adopting a dry etching process or a wet etching process;
and etching the first sacrificial layer by adopting a dry etching process or a wet etching process to form the second sacrificial layer with a first preset thickness.
9. The method of forming as claimed in claim 8, wherein forming an intermediate support layer on the second sacrificial layer comprises:
covering the second sacrificial layer and the lower electrode with an intermediate support material layer;
forming a spin-on hard mask layer on the intermediate support material layer;
and simultaneously removing the middle support material layer and the spin-on hard mask layer on the top and the side wall of the lower electrode to form the middle support layer.
10. The method of forming as claimed in any one of claims 1 to 7, wherein forming a middle support layer and a top support layer on the second sacrificial layer to form a capacitor structure comprises:
forming a third sacrificial layer on the middle support layer; wherein a top surface of the third sacrificial layer is lower than a top surface of the lower electrode;
forming the top support layer on the third sacrificial layer;
patterning the top support layer, forming a first opening in the top support layer, and removing the second sacrificial layer and the third sacrificial layer through the first opening;
and sequentially forming a dielectric layer and an upper electrode on the lower electrode to obtain the capacitor structure.
11. The method of forming as claimed in claim 10, wherein the second sacrificial layer is a different material than the third sacrificial layer;
the material of the third sacrificial layer is oxide.
12. The method of forming of claim 10, wherein forming a third sacrificial layer on the middle support layer comprises:
forming an initial third sacrificial material layer on the intermediate support layer, wherein a top surface of the initial third sacrificial material layer is higher than a top surface of the lower electrode;
removing part of the initial third sacrificial material layer by adopting a chemical mechanical polishing process to form an initial third sacrificial layer which is flush with the top surface of the lower electrode;
and etching the initial third sacrificial layer by adopting a dry etching process or a wet etching process to form a third sacrificial layer lower than the top surface of the lower electrode.
13. The method of forming as claimed in claim 10, wherein patterning the top support layer, forming a first opening in the top support layer, removing the second sacrificial layer and the third sacrificial layer via the first opening comprises:
etching the top support layer, the middle support layer, the second sacrificial layer and the third sacrificial layer between any adjacent lower electrodes to form the first opening;
and etching the second sacrificial layer and the third sacrificial layer through the first opening by adopting a wet etching process.
14. A semiconductor structure, comprising: a capacitor structure formed by the formation method according to any one of claims 1 to 13.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115955840A (en) * | 2023-03-09 | 2023-04-11 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN116234312A (en) * | 2023-05-05 | 2023-06-06 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and memory |
| CN117318646A (en) * | 2023-10-12 | 2023-12-29 | 中微龙图电子科技无锡有限责任公司 | Manufacturing method of surface acoustic wave filter with temperature compensation function |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115955840A (en) * | 2023-03-09 | 2023-04-11 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN115955840B (en) * | 2023-03-09 | 2023-06-02 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN116234312A (en) * | 2023-05-05 | 2023-06-06 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and memory |
| CN116234312B (en) * | 2023-05-05 | 2023-09-22 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and memory |
| CN117318646A (en) * | 2023-10-12 | 2023-12-29 | 中微龙图电子科技无锡有限责任公司 | Manufacturing method of surface acoustic wave filter with temperature compensation function |
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