CN116156875A

CN116156875A - Semiconductor structure and forming method thereof

Info

Publication number: CN116156875A
Application number: CN202211333627.XA
Authority: CN
Inventors: 杨校宇
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2023-05-23

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a substrate, a laminated structure and an initial mask layer, the laminated structure is positioned on the substrate, and the initial mask layer is positioned on the top surface of the laminated structure; forming a capacitor hole, wherein the capacitor hole penetrates through the initial mask layer and the laminated structure to form an initial conductive layer, and the initial conductive layer covers the inner wall of the capacitor hole and covers the top surface of the initial mask layer; etching the initial conductive layer and the initial mask layer to form a first opening, forming a first mask layer by the residual initial mask layer, and forming a first conductive layer by the residual initial conductive layer above the first mask layer; and etching the first conductive layer and the first mask layer to form a capacitor structure and a supporting structure while etching the laminated structure through the first opening.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor fabrication, and relates to, but is not limited to, a semiconductor structure and a method of forming the same.

Background

A dynamic random access memory (Dynamic Random Access Memory, DRAM) cell includes a capacitor and a transistor for storing charge. DRAM stores data in the form of charge on a capacitor, so regular recharging of the capacitor is required every few milliseconds. The larger the capacitance of the capacitor, the longer the data stored in the DRAM can be maintained. However, the height of the lower electrode is reduced when the capacitor is formed by the conventional process, thereby reducing the capacitance value of the capacitor to be formed later.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.

In a first aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, the method including: providing a substrate, wherein the substrate comprises a substrate, a laminated structure and an initial mask layer, the laminated structure is positioned on the substrate, and the initial mask layer is positioned on the top surface of the laminated structure; forming a capacitor hole, wherein the capacitor hole penetrates through the initial mask layer and the laminated structure; forming an initial conductive layer, wherein the initial conductive layer covers the inner wall of the capacitor hole and covers the top surface of the initial mask layer; etching the initial conductive layer and the initial mask layer to form a first opening, forming a first mask layer by the residual initial mask layer, and forming a first conductive layer by the residual initial conductive layer above the first mask layer; and etching the first conductive layer and the first mask layer to form a capacitor structure and a supporting structure while etching the laminated structure through the first opening.

In some embodiments, the forming an initial conductive layer includes: filling the initial conductive layer in the capacitor hole to form a columnar lower electrode; or depositing the initial conductive layer on the bottom and the side wall of the capacitor hole to form a cylindrical lower electrode.

In some embodiments, forming the capacitive structure and the support structure includes: etching the first conducting layer above the first mask layer while etching the laminated structure through the first opening, wherein the rest of the initial conducting layer forms a lower electrode, and the rest of the laminated structure forms the supporting structure; and sequentially forming a dielectric layer and an upper electrode on the surfaces of the lower electrode and the supporting structure to form the capacitor structure.

In some embodiments, the laminated structure includes a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer laminated in sequence; etching the laminated structure through the first opening, including: etching to remove the first conductive layer while forming a second opening by etching the top support layer through the first opening; and removing the second sacrificial layer through the second opening.

In some embodiments, etching the stacked structure through the first opening further comprises: removing the second sacrificial layer through the second opening to expose a part of the intermediate support layer; removing the first mask layer while patterning the intermediate support layer to form a third opening; and removing the first sacrificial layer through the third opening to expose the bottom support layer.

In some embodiments, the second opening is etched using a dry etching process while removing the first conductive layer; the etching gas in the dry etching process comprises the following components: chlorine, oxygen, argon.

In some embodiments, the material of the first sacrificial layer comprises borophosphosilicate glass, the material of the second sacrificial layer comprises an oxide, and the second sacrificial layer and the first sacrificial layer are removed using a hydrofluoric acid solution.

In some embodiments, a dry etching process is used to etch the third opening, and the first mask layer is removed; wherein the etching gas in the dry etching process comprises at least one of the following: c (C) ₄ F ₈ 、C ₄ F ₆ 、O ₂ 、CH ₂ F ₂ 。

In some embodiments, forming the first conductive layer and the first mask layer includes: sequentially forming an initial composite mask layer and a patterned photoresist layer on the initial conductive layer; etching the initial composite mask layer based on the patterned photoresist layer to form a patterned composite mask layer; and etching the initial conductive layer and the initial mask layer based on the patterned composite mask layer to form the first opening, the first conductive layer and the first mask layer.

In some embodiments, the forming the capacitive aperture includes: etching the initial mask layer with a first pattern identical to the capacitor hole pattern to form an initial mask layer with the first pattern; and etching the laminated structure through the initial mask layer with the first pattern to form the capacitor hole exposing the substrate.

In some embodiments, the initial mask layer includes a polysilicon layer and a silicon oxide layer on the polysilicon layer.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure, wherein the semiconductor structure includes: a substrate; the capacitive structure and the support structure on the substrate and formed using the method of any of the embodiments described above; wherein the top surface of the capacitive structure is higher than the top surface of the support structure.

In some embodiments, the capacitive structures comprise double sided capacitive structures or columnar capacitive structures.

In some embodiments, the height difference between the top surface of the capacitive structure and the top surface of the support structure ranges from 30nm to 45nm.

In an embodiment of the present disclosure, first, a substrate is provided, the substrate including a substrate, a stacked structure, and an initial mask layer, the stacked structure being located on the substrate, the initial mask layer being located on a top surface of the stacked structure; secondly, forming a capacitor hole penetrating the initial mask layer and the laminated structure; then, forming an initial conductive layer covering the inner wall of the capacitor hole and the top surface of the initial mask layer; secondly, etching the initial conductive layer and the initial mask layer to form a first opening, forming a first mask layer by the residual initial mask layer, and forming a first conductive layer by the residual initial conductive layer above the first mask layer; finally, etching the laminated structure through the first opening and simultaneously removing the first conductive layer and the first mask layer to form the capacitor structure and the support structure.

Because the initial mask layer is not removed after the capacitor hole is formed, byproducts are not generated and fall into the capacitor hole, so that the capacitor hole is clean, the quality of a subsequently formed lower electrode is good, and the situation that the peripheral area structure is damaged by permeation is avoided; meanwhile, as the etching process of removing the initial mask layer is omitted, on one hand, the top supporting layer is not consumed, and the capacitance hole is not enlarged, so that the height of the lower electrode is not reduced, the adjacent lower electrodes are connected to be short-circuited, and the capacitance value can be improved; on the other hand, the supporting effect of the supporting structure can be improved.

Because the first mask layer and the first conductive layer are formed on the laminated structure, the first mask layer and the first conductive layer protect the top support layer in the laminated structure when the laminated structure is etched through the first opening, so that the consumption of the top support layer is reduced; meanwhile, the lower electrode in the capacitor hole is not consumed, so that the supporting effect of the supporting structure can be improved, the height of the lower electrode can be improved, and the capacitance value of the capacitor structure is further improved.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic implementation flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 2 to 14 are schematic views illustrating a process of forming a semiconductor structure according to an embodiment of the disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the related art, after forming the capacitor hole, a hard mask layer of about 100 nanometers (nm) (the material of the hard mask layer may be polysilicon) is still present on the top support layer, and this polysilicon layer needs to be removed by an additional first etching process; then removing byproducts by adopting nitrogen, and then carrying out ashing treatment; and finally, cleaning by adopting a cleaning liquid. After the titanium nitride (TiN) material forming the lower electrode is deposited subsequently, a second etching process is continuously required to remove the TiN positioned on the top supporting layer; and then removing byproducts by adopting nitrogen etching, and cleaning the surface by adopting cleaning liquid to enable each lower electrode to be independent. In addition, it can be seen from the above that at least 7 processes are required to remove the polysilicon and the excess titanium nitride.

However, the presence of the two processes, the first etching process and the second etching process, creates a number of problems. On the one hand, when the polysilicon is removed by the first etching process, byproducts (such as polymers) are generated, and the byproducts drop into the capacitor holes with high aspect ratio and are difficult to clean, thus affecting the quality of the subsequently formed lower electrode. On the other hand, the two processes consume the top supporting layer higher than 20nm, so that the height of the lower electrode can be reduced, and the capacitance value of a capacitor formed subsequently is reduced; the first etch process also increases the critical dimensions (Critical Dimension, CD) of the top of the capacitor hole, which shorts adjacent two bottom electrodes.

In addition, since the byproduct particles are present in the relevant capacitor holes, when the lower electrode is formed later, the point of the byproduct particles is present on the lower electrode, so that a hole is formed on the lower electrode; subsequently, when the sacrificial layers of the array region and the peripheral region are opened, the etching solution may penetrate into the peripheral region through the holes on the lower electrode, thereby etching the bottom support layer of the peripheral region, exposing some structures of the peripheral region in advance, and thus damaging the structures of the peripheral region.

An embodiment of the present disclosure provides a method for forming a semiconductor structure, referring to fig. 1, the method includes steps S101 to S105, wherein:

step S101, providing a substrate, wherein the substrate comprises a substrate, a laminated structure and an initial mask layer, the laminated structure is positioned on the substrate, and the initial mask layer is positioned on the top surface of the laminated structure;

the substrate may be a single-layer substrate, for example, the substrate may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display; the substrate may also include multiple layers, such as a silicon-on-insulator (Silicon On Insulator, SOI) substrate, or a germanium-on-insulator (Germanium On Insulator, GOI) substrate, or the like. In some embodiments, the substrate may also be an ion doped substrate, such as a P-doped substrate or an N-doped substrate.

In practice, landing Pads (LP) for connecting the drain of the transistor to a subsequently formed capacitive structure (i.e., capacitor) and isolation structures located between adjacent Landing pads may be included in the substrate; the landing pads may be arranged in an array corresponding to the arrangement of capacitors. In some embodiments, the substrate includes a peripheral region for forming peripheral devices, such as field effect transistors, capacitors, inductors, diodes, and the like, and an array region. The array region is used to form memory structures, such as structures including word lines, bit lines, and memory transistors, in a subsequent process.

The laminated structure may include a support layer and a sacrificial layer laminated in this order. The support layer is used for forming a support structure and supporting a capacitor structure formed subsequently; the sacrificial layer is consumed in the subsequent process, leaving room for depositing the dielectric layer material and the upper electrode material. In practice, the laminated structure may include a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer, which are laminated in that order. Wherein the material of the support layer may comprise at least one of: silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, silicon boride nitride. The material of the sacrificial layer may include silicon oxide, phosphosilicate glass (Phosphoro Silicate Glass, PSG), borophosphosilicate glass (Boro phosphor silicate Glass, BPSG), fluorosilicate glass (Fluoro Silicate Glass, FSG), or the like.

The initial mask layer is not only used as a mask layer, but also can protect the top support layer during subsequent etching of the laminated structure, so that the reduction amount of the top support layer and the lower electrode is reduced, and the capacitance value of the capacitor structure and the supporting effect of the support structure are improved. The initial mask layer can be of a single-layer structure or a double-layer structure; the material of each layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride and titanium. In practice, the initial mask layer may be a bilayer structure of a polysilicon layer and a silicon oxynitride layer (or silicon oxide layer) on the polysilicon layer.

The support layer, sacrificial layer, and initial mask layer may be formed by any suitable deposition process, such as, for example, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, a plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, a spin-on process, a coating process, a thin film process, or the like.

Step S102, forming a capacitor hole, wherein the capacitor hole penetrates through the initial mask layer and the laminated structure;

here, the capacitor hole may expose the substrate, and a dry process (e.g., a plasma etching process, a reactive ion etching process, or an ion milling process) may be used to pattern the initial mask layer and the stacked structure to form the capacitor hole. The gas used for dry etching may be trifluoromethane (CHF) ₃ ) Carbon tetrafluoride (CF) ₄ ) Difluoromethane (CH) ₂ F ₂ ) Hydrobromic acid (HBr), chlorine (Cl) ₂ ) Sulfur hexafluoride (SF) ₆ ) Octafluorocyclobutane (C) ₄ F ₈ ) Hexafluoro-2-butyne (C) ₄ F ₆ ) Oxygen (O) ₂ ) One of argon (Ar) or a combination thereof. In some embodiments, it is also possible toAnd forming the capacitor hole by adopting a wet etching process.

Step S103, forming an initial conductive layer, wherein the initial conductive layer covers the inner wall of the capacitor hole and covers the top surface of the initial mask layer;

Here, the initial conductive layer may include two parts, and one part is an initial conductive layer covering the inner wall of the capacitor hole (the initial conductive layer may fill the capacitor hole, or the initial conductive layer may not fill the capacitor hole, and is formed only at the bottom and the side wall of the capacitor hole); another part is an initial conductive layer that covers the initial mask layer.

In practice, the initial conductive layer may be formed using any suitable deposition process, such as low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) and the like.

In some embodiments, the implementation of step S103 may include step S1031 or step S1032, wherein: step S1031, filling the initial conductive layer in the capacitor hole to form a columnar lower electrode, and forming a columnar capacitor later, wherein compared with a double-sided capacitor, the area of the columnar capacitor is smaller, so that the integration level can be improved, and the miniaturization is realized; in step S1032, an initial conductive layer is deposited at the bottom and sidewalls of the capacitor hole. That is to say, the initial conductive layer in the capacitor hole is consistent with the shape of the capacitor hole, so that a cylindrical lower electrode is formed, and a cylindrical capacitor can be formed subsequently, so that the capacitance value is improved.

Step S104, etching the initial conductive layer and the initial mask layer to form a first opening, forming a first mask layer by the residual initial mask layer, and forming a first conductive layer by the residual initial conductive layer above the first mask layer;

Here, the differences from the related art in step S104 include at least: in the related art, the initial conductive layer and the initial mask layer are removed, and step S104 etches only the initial conductive layer and the initial mask layer to form the first opening. The initial conductive layer and the initial mask layer may be etched using a dry etching or a wet etching process to form the first opening. In order to reduce damage to the lower electrode when forming the first opening, the projection of the first opening in the thickness direction of the laminated structure should be located between adjacent columnar lower electrodes or cylindrical lower electrodes.

In step S105, the first conductive layer and the first mask layer are etched and removed while the stacked structure is etched through the first opening, so as to form a capacitor structure and a support structure.

Here, etching the laminated structure through the first opening may include a plurality of etching processes, the number of etching being related to the number of layers in the laminated structure, for example, the laminated structure including the bottom support layer, the sacrificial layer, and the top support layer, and then the number of etching may be two. The top support layer is opened once through the first opening and the sacrificial layer is removed once through the opening in the top support layer. The timing of the removal of the first conductive layer and the first mask layer is related to the etching gas or etching solution in the etching process. In practice, the first mask layer should be removed as much as possible in the previous step of removing the sacrificial layer located at the lowermost part of the stacked structure, so that the consumption of the top support layer can be reduced while simplifying the process flow.

A process of forming a semiconductor structure provided by an embodiment of the present disclosure will be described in detail with reference to fig. 2 to 14.

Referring to fig. 2, a step S101 is performed to provide a base 100, where the base 100 includes a substrate 10, a laminated structure 20, and an initial mask layer 30, the laminated structure 20 being located on the substrate 10, the initial mask layer 30 being located on a top surface of the laminated structure 20.

Here, the stacked structure 20 may include a bottom support layer 201, a first sacrificial layer 202, an intermediate support layer 203, a second sacrificial layer 204, and a top support layer 205, wherein the materials of the bottom support layer 201, the intermediate support layer 203, and the top support layer 205 are silicon nitride or silicon carbide nitride, the material of the first sacrificial layer 202 is borophosphosilicate glass, and the material of the second sacrificial layer 204 is oxide, such as silicon oxide. The initial mask layer 30 includes a polysilicon layer 301 and a silicon oxide layer 302 on the polysilicon layer 301.

Next, referring to fig. 2 and 3, step S102 is performed to form a capacitor hole 40, where the capacitor hole 40 penetrates through the initial mask layer 30 and the laminated structure 20. Note that, part of the initial mask layer 30 is consumed while the capacitor hole 40 is formed, and therefore, the initial mask layer 30 on the laminated structure 20 becomes thin after the capacitor hole 40 is formed. In order to leave the initial mask layer in the laminated structure after the capacitor holes are formed, the etching rate of the etching substance on the laminated structure needs to be greater than the etching rate of the initial mask layer.

In implementation, the initial mask layer can be etched in a first pattern identical to the capacitor hole pattern to form an initial mask layer with the first pattern; and etching the laminated structure by using the initial mask layer with the first pattern, and forming the laminated structure penetrated by the capacitor holes while forming the capacitor holes exposing the substrate. The capacitor hole pattern comprises a plurality of capacitor holes which are arranged in an array, the capacitor holes are in one-to-one correspondence with the landing pads, and each capacitor hole is communicated with the corresponding landing pad. In some embodiments, self-aligned dual imaging (Self-aligned Double Patterning, SADP) techniques may also be used to form capacitive holes, thereby enabling spatial frequency doubling of the lithographic pattern, which may result in smaller, denser capacitive holes.

Next, referring to fig. 3 to 5, step S103 is performed, and an initial conductive layer 50 is formed, where the initial conductive layer 50 covers the inner wall of the capacitor hole 40 and covers the top surface of the initial mask layer 30. Fig. 4 is a schematic diagram of filling the capacitor hole with the initial conductive layer 50 to form a columnar bottom electrode. In some embodiments, as shown in fig. 5, an initial conductive layer 50 is deposited at the bottom and sidewalls of the capacitor hole to form a cylindrical bottom electrode, which in the disclosed embodiments is mainly described as an example.

Step S104 is performed with reference to fig. 6 to 8, where the initial conductive layer 50 and the initial mask layer 30 are etched to form a first opening 605, the remaining initial mask layer 30 forms a first mask layer 31, and the remaining initial conductive layer 50 located above the first mask layer 31 forms a first conductive layer 51.

In some embodiments, forming the first conductive layer and the first mask layer may include steps S1041 to S1043, wherein:

step S1041, an initial composite mask layer and a patterned photoresist layer are sequentially formed on the initial conductive layer;

here, the initial composite mask layer may include at least two mask layers, and each mask layer may be made of any one of silicon dioxide, silicon nitride, amorphous carbon (Amorphous Carbon Layer, ACL), silicon oxynitride, and polysilicon, for example, the initial composite mask layer includes a silicon nitride layer and an amorphous carbon layer on the silicon nitride layer. In practice, a Bottom Anti-reflective layer (BARC) may also be formed on the initial composite mask layer, followed by a patterned photoresist layer on the Bottom Anti-reflective layer. Thus, the photoetching reflected light can be absorbed, and the accuracy of pattern transfer is improved. The material of the bottom anti-reflection layer may be silicon oxynitride (SiON) or the like.

Referring to fig. 6, step S1041 is performed to sequentially form an initial composite mask layer 60a, a bottom anti-reflection layer 603, and a patterned photoresist layer 604 on the initial conductive layer 50; wherein the initial composite mask layer 60a includes an initial silicon nitride layer 601a and an amorphous carbon layer 602a on the initial silicon nitride layer 601 a. It can be seen from fig. 6 that the patterned photoresist layer 604 has a plurality of openings, wherein the plurality of openings correspond to the locations of subsequently formed first openings.

Step S1042, etching the initial composite mask layer based on the patterned photoresist layer to form a patterned composite mask layer;

step S1042 is a process of transferring the pattern in the photoresist layer to the initial composite mask layer to form a patterned composite mask layer.

Referring to fig. 6 and 7 together, step S1042 is performed by etching the bottom anti-reflection layer 603 and the initial composite mask layer based on the patterned photoresist layer 604 to form a patterned composite mask layer 60, the patterned composite mask layer 60 comprising a silicon nitride layer 601 and an amorphous carbon layer 602 on the silicon nitride layer 601.

In practice, a dry etching process may be used to transfer the pattern in the patterned photoresist layer to the bottom anti-reflective layer and the initial composite mask layer, and then a dry or wet etching process (the etching solution may be a strong acid such as concentrated sulfuric acid, hydrofluoric acid, and concentrated nitric acid) may be used to remove the patterned photoresist layer and the patterned bottom anti-reflective layer, and when the patterned bottom anti-reflective layer is removed, a portion of the patterned composite mask layer may be removed, thereby forming the patterned composite mask layer 60 shown in fig. 7. To reduce the etching of the patterned composite mask layer, the etch selectivity between the patterned composite mask layer and the patterned bottom antireflective layer may be increased.

In some embodiments, the patterned photoresist layer and the patterned bottom anti-reflective layer may not be removed, and the initial conductive layer and the initial mask layer may be etched using the patterned photoresist layer, the patterned bottom anti-reflective layer, and the patterned composite mask layer as masks.

In step S1043, the initial conductive layer and the initial mask layer are etched based on the patterned composite mask layer, so as to form a first opening, a first conductive layer and a first mask layer.

Here, the patterned composite mask layer, the first opening, the first conductive layer, and the first mask layer may be formed using a dry or wet etching process.

Referring to fig. 7 and 8 simultaneously, step S1043 is performed to etch the initial conductive layer 50 and the initial mask layer 30 based on the patterned composite mask layer 60, form a first opening 605 exposing the top support layer 205 with the top support layer 205 as an etch stop layer, form a first mask layer 31 from the remaining initial mask layer 30, and form a first conductive layer 51 from the remaining initial conductive layer 50 located above the first mask layer 31. In practice, after etching the initial conductive layer 50 and the initial mask layer 30, the method of forming a semiconductor structure further includes: the patterned composite mask layer 60 located on the first conductive layer 51 is removed.

Next, step S105 will be performed with reference to fig. 9 to 14, in which the first conductive layer 51 and the first mask layer 31 are etched away to form the capacitor structure 55 and the support structure 21 while the laminated structure 20 is etched through the first opening 605.

In some embodiments, step S105 may be implemented by step S1051 and step S1052, wherein:

step S1051, etching the laminated structure through the first opening, and simultaneously removing the first conductive layer above the first mask layer by etching, wherein the rest initial conductive layer forms a lower electrode, and the rest laminated structure forms a supporting structure;

here, since the first conductive layer located above the first mask layer is removed, the lower electrode is formed higher, and thus the capacitor structure formed later is also higher. The embodiments of the present disclosure may increase the height of the capacitor structure relative to the capacitor structure in the related art, which may increase the capacitance value. For example, the capacitance value of the capacitive structure may increase by at least 0.3 femtofarads (fF) when the height of the capacitive structure increases by 30 nm.

It should be noted that step S1051 includes at least a process of removing the sacrificial layer in the stacked structure (removing the sacrificial layer requires forming an opening on the support layer other than the bottom support layer) and a process of removing the first conductive layer located above the first mask layer to form the lower electrode; the laminated structure comprises a laminated sacrificial layer and a support layer, and the rest laminated structure refers to the support layer which is remained after the sacrificial layer is removed.

In some embodiments, referring to fig. 8, the laminated structure 20 includes a bottom support layer 201, a first sacrificial layer 202, an intermediate support layer 203, a second sacrificial layer 204, and a top support layer 205, which are laminated in sequence. Correspondingly, etching the stacked structure through the first opening in step S1051 may include step S151 and step S152, wherein:

step S151, etching the first conductive layer while forming a second opening by etching the top supporting layer through the first opening;

here, when the second opening is formed by etching the top support layer through the first opening, the etching rates of the selected etching substance to the top support layer and the first conductive layer should be approximately the same so that the first conductive layer can be removed while simultaneously opening the top support layer. In other words, a special process is not required to remove the unnecessary first conductive layer, so that the process flow can be simplified.

In implementation, a second opening can be formed by etching through a dry etching process, and the first conductive layer is removed at the same time, wherein the second opening is positioned in the top supporting layer and is used for removing the second sacrificial layer; the etching gas in the dry etching process comprises: chlorine (Cl) ₂ )、O ₂ Ar, wherein the volume flow rate of chlorine ranges from 100 to 200 standard milliliters per minute (sccm), the volume flow rate of oxygen ranges from 10 to 40sccm, and the volume flow rate of argon ranges from 50 to 80sccm. In the actual process, the proportion of the etching gas is adjusted according to the actual etching condition to ensure that the removal of the first conductive layer is completed while the second opening is formed, for example For example, the volume flow rate of chlorine is 150sccm, the volume flow rate of oxygen is 25sccm, and the volume flow rate of argon is 65sccm.

In step S152, the second sacrificial layer is removed through the second opening.

The material of the second sacrificial layer may include an oxide, and the second sacrificial layer may be removed using a hydrofluoric acid solution, wherein a volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:150 to 1:250, for example, a volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:200.

After removing the second sacrificial layer, a portion of the intermediate support layer may be exposed, after which an opening may be formed in the intermediate support layer, and the first sacrificial layer may be removed, thereby forming a support structure.

In some embodiments, etching the stacked structure through the first opening in step S1051 further includes step S153 and step S154, wherein:

step S153, removing the second sacrificial layer through the second opening, and exposing part of the intermediate support layer;

step S154, removing the first mask layer while patterning the intermediate support layer to form a third opening; and removing the first sacrificial layer through the third opening to expose the bottom support layer.

Here, the material of the first sacrificial layer may include borophosphosilicate glass, and the first sacrificial layer may be removed by using a hydrofluoric acid solution, wherein a volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:150 to 1:250, for example, a volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:200; the third opening is located in the intermediate support layer for removing the first sacrificial layer.

The etch rate of the selected etch species should be approximately the same for the intermediate support layer and the first mask layer when forming the third opening, so that the first mask layer can be removed while the intermediate support layer is opened. Therefore, on one hand, the top supporting layer can be protected, so that the loss of the top supporting layer can be reduced, and the supporting effect is improved; on the other hand, no additional process is required to specially remove the first mask layer, so that the process flow can be further simplified.

In implementation, a dry etching process can be adopted to etch the third opening, and the first mask layer is removed at the same time; wherein the etching gas in the dry etching process may include at least one of: c (C) ₄ F ₈ 、C ₄ F ₆ 、O ₂ 、CH ₂ F ₂ The method comprises the steps of carrying out a first treatment on the surface of the Wherein C is ₄ F ₈ In the range of 5-30sccm, C ₄ F ₆ The volume flow rate of (C) is in the range of 5-35sccm, O ₂ The volume flow rate of (C) is in the range of 40-80sccm, CH ₂ F ₂ The volume flow rate of (2) is in the range of 20-50sccm. In the actual process, the proportion of the etching gas is adjusted according to the actual etching condition to ensure that the removal of the first mask layer, for example, C, is completed while the third opening is formed ₄ F ₈ Is 15sccm, C ₄ F ₆ Is 20sccm, O ₂ Is 60sccm and CH ₂ F ₂ Is 35sccm.

Step S151 to step S154 will be performed with reference to fig. 9 to 13.

First, referring to fig. 9, step S151 is performed to etch the first conductive layer 51 over the first mask layer 31 while forming the second opening 606 by etching the top support layer 205 through the first opening 605 (refer to fig. 8), exposing the first mask layer 31, and forming the lower electrode 52. In practice, over-etching may occur when etching the top support layer 205 to form the second opening 606, which may form a first recess a in the second sacrificial layer 204 as shown in fig. 10.

Next, step S152 and step S153 are performed with reference to fig. 11, and the second sacrificial layer 204 is removed through the second opening 606 (refer to fig. 9 or 10). After the second sacrificial layer is removed, the intermediate support layer 203 is exposed.

Finally, referring to fig. 12 and 13, step S154 is performed to remove the first mask layer while etching the intermediate support layer 203 along the second opening, i.e., patterning the intermediate support layer 203, to form a third opening 607 as shown in fig. 12, thereby exposing the top support layer 205; referring to fig. 13, the first sacrificial layer 202 is removed through the third opening 607, exposing the bottom support layer 201 such that the bottom support layer 201, the remaining intermediate support layer 203, and the remaining top support layer 205 may constitute the support structure 21.

As can be seen from fig. 12, there is a height difference H between the top surface of the bottom electrode 52 and the top surface of the top supporting layer 205, so that the bottom electrode 52 in the embodiment of the disclosure is higher than the bottom electrode in the related art, so that the depth of the capacitor structure formed later is larger, thereby improving the capacitance of the capacitor structure and further maintaining the data stored in the DRAM for a longer time.

It should be noted that, the etching solution may be adjusted to form the third opening on the intermediate support layer, and at the same time, just remove the first mask layer; in addition, over etching may occur when the third opening is etched, so that the second groove B as shown in fig. 12 may be formed in the first sacrificial layer 202. In addition, when the first sacrificial layer 202 is removed, a portion of the top support layer 205 may be consumed, and the thickness of the top support layer 205 may be thinned.

In step S1052, a dielectric layer and an upper electrode are sequentially formed on the surfaces of the lower electrode and the support structure, thereby forming a capacitor structure.

The dielectric layer may be made of high-K dielectric material to increase the capacitance of the capacitor structure per unit area, and may include zirconium oxide (ZrO _x ) Hafnium oxide (HfO) _x ) Zirconium titanium oxide (ZrTiO) _x ) Ruthenium oxide (RuO) _x ) Antimony oxide (SbO) _x ) Alumina (AlO) _x ) Barium titanate (BaTiO) ₃ ) A laminate of two or more of the above materials.

The material of the upper electrode may include one of tantalum (Ta), ruthenium (Ru), cobalt (Co), gold (Au), tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), titanium nitride, tantalum nitride (TaN), N-type polysilicon, P-type polysilicon, or a stack formed by two or more of the above materials. The material of the upper electrode may be the same as that of the lower electrode, for example, the materials of the upper electrode and the lower electrode each include titanium nitride; the material of the upper electrode may be different from that of the lower electrode, for example, the material of the upper electrode is tantalum and the material of the lower electrode is titanium nitride. In practice, the dielectric layer and upper electrode may be formed by any suitable deposition process, such as a chemical vapor deposition process, an atomic layer deposition process, or the like.

Referring to fig. 13, dielectric layer material and upper electrode material are sequentially deposited on support structure 21 and lower electrode 52 to form dielectric layer 53 and upper electrode 54 as shown in fig. 14, thereby forming capacitive structure 55.

Embodiments of the present disclosure also provide a semiconductor structure, referring to fig. 14, the semiconductor structure including: a substrate 10; a capacitor structure 55 and a support structure 21 located on the substrate 10 and formed using the method of any of the embodiments described above; wherein the top surface of the capacitive structure 55 is higher than the top surface of the support structure 21. In practice, the height difference between the top surface of the capacitive structure 55 and the top surface of the support structure 21 ranges from 30nm to 45nm, which may be, for example, 35nm, 38nm, 40nm, 42nm.

In some embodiments, the capacitive structures comprise cylindrical capacitive structures or columnar capacitive structures.

In the embodiment of the disclosure, the capacitor structure and the supporting structure are formed by adopting the method for forming the semiconductor structure provided by the embodiment of the disclosure, so that the lower electrode in the capacitor structure has better quality, the capacitance value of the capacitor structure is larger, and the supporting effect of the supporting structure is better, thereby improving the stability of the capacitor structure.

In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of the units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.

While the foregoing is directed to embodiments of the present disclosure, the scope of the embodiments of the present disclosure is not limited to the foregoing, and any changes and substitutions that are within the scope of the embodiments of the present disclosure will be readily apparent to those skilled in the art. Therefore, the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of forming a semiconductor structure, the method comprising:

providing a substrate, wherein the substrate comprises a substrate, a laminated structure and an initial mask layer, the laminated structure is positioned on the substrate, and the initial mask layer is positioned on the top surface of the laminated structure;

forming a capacitor hole, wherein the capacitor hole penetrates through the initial mask layer and the laminated structure;

forming an initial conductive layer, wherein the initial conductive layer covers the inner wall of the capacitor hole and covers the top surface of the initial mask layer;

etching the initial conductive layer and the initial mask layer to form a first opening, forming a first mask layer by the residual initial mask layer, and forming a first conductive layer by the residual initial conductive layer above the first mask layer;

And etching the first conductive layer and the first mask layer to form a capacitor structure and a supporting structure while etching the laminated structure through the first opening.

2. The method of claim 1, wherein forming an initial conductive layer comprises:

filling the initial conductive layer in the capacitor hole to form a columnar lower electrode;

or depositing the initial conductive layer on the bottom and the side wall of the capacitor hole to form a cylindrical lower electrode.

3. The method of claim 1, wherein forming the capacitive structure and the support structure comprises:

etching the first conducting layer above the first mask layer while etching the laminated structure through the first opening, wherein the rest of the initial conducting layer forms a lower electrode, and the rest of the laminated structure forms the supporting structure;

and sequentially forming a dielectric layer and an upper electrode on the surfaces of the lower electrode and the supporting structure to form the capacitor structure.

4. A method according to claim 3, wherein the laminated structure comprises a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer and a top support layer laminated in that order;

Etching the laminated structure through the first opening, including: etching to remove the first conductive layer while forming a second opening by etching the top support layer through the first opening; and removing the second sacrificial layer through the second opening.

5. The method of claim 4, wherein etching the stacked structure through the first opening further comprises: removing the second sacrificial layer through the second opening to expose a part of the intermediate support layer; removing the first mask layer while patterning the intermediate support layer to form a third opening; and removing the first sacrificial layer through the third opening to expose the bottom support layer.

6. The method of claim 4, wherein the second opening is etched using a dry etching process while removing the first conductive layer;

the etching gas in the dry etching process comprises the following components: chlorine, oxygen, argon.

7. The method of claim 5, wherein the material of the first sacrificial layer comprises borophosphosilicate glass and the material of the second sacrificial layer comprises an oxide, and wherein the second sacrificial layer and the first sacrificial layer are removed using a hydrofluoric acid solution.

8. The method of claim 7, wherein the third opening is etched using a dry etching process while removing the first mask layer;

wherein the etching gas in the dry etching process comprises at least one of the following: c (C) ₄ F ₈ 、C ₄ F ₆ 、O ₂ 、CH ₂ F ₂ 。

9. The method of any of claims 1 to 8, wherein forming the first conductive layer and the first mask layer comprises:

sequentially forming an initial composite mask layer and a patterned photoresist layer on the initial conductive layer;

etching the initial composite mask layer based on the patterned photoresist layer to form a patterned composite mask layer;

and etching the initial conductive layer and the initial mask layer based on the patterned composite mask layer to form the first opening, the first conductive layer and the first mask layer.

10. The method of any one of claims 1 to 8, wherein forming the capacitive aperture comprises:

etching the initial mask layer with a first pattern identical to the capacitor hole pattern to form an initial mask layer with the first pattern;

and etching the laminated structure through the initial mask layer with the first pattern to form the capacitor hole exposing the substrate.

11. The method of claim 10, wherein the initial mask layer comprises a polysilicon layer and a silicon oxide layer on the polysilicon layer.

12. A semiconductor structure, wherein the semiconductor structure comprises:

a substrate;

the capacitive structure and the support structure on the substrate and formed using the method of any one of claims 1 to 11;

wherein the top surface of the capacitive structure is higher than the top surface of the support structure.

13. The structure of claim 12, wherein the capacitive structure comprises a double sided capacitive structure or a columnar capacitive structure.

14. The structure of claim 12, wherein a height difference between a top surface of the capacitive structure and a top surface of the support structure ranges from 30nm to 45nm.