CN115586391A

CN115586391A - Electrical test circuit, chip, system, method, electronic device, and storage medium

Info

Publication number: CN115586391A
Application number: CN202211355168.5A
Authority: CN
Inventors: 孙凌; 陈羿桦
Original assignee: Pingtouge Shanghai Semiconductor Co Ltd
Current assignee: Pingtouge Shanghai Semiconductor Co Ltd
Priority date: 2022-11-01
Filing date: 2022-11-01
Publication date: 2023-01-10

Abstract

The embodiment of the application provides an electrical test circuit, a chip, a system, a method, electronic equipment and a storage medium, and the electrical test circuit, the chip, the system, the method, the electronic equipment and the storage medium are suitable for electrically testing electrical elements in various chips comprising an ARM or RISC-V instruction set architecture, such as electrical elements in an Internet of things chip and an audio/video chip based on the ARM or RISC-V instruction set architecture. The electrical property test circuit includes: at least one input signal pad and at least one array of devices under test, each array of devices under test comprising a plurality of devices under test; each device under test is connected to at least one input signal pad through a metal line formed on the semiconductor substrate; each input signal bonding pad and each tested device connected to the input signal bonding pad through a metal wire in the same tested device array form a tree structure, and the lengths of the metal wires between each tested device connected to the input signal bonding pad in the same tested device array and the input signal bonding pad are equal.

Description

Electrical test circuit, chip, system, method, electronic device, and storage medium

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to an electrical property testing circuit, a chip, a system, a method, electronic equipment and a storage medium.

Background

Integrated Circuits (ICs) include millions to billions of logic gates, each of which and other devices whose electrical parameters are required to meet their respective standard requirements, or else the IC may not operate properly. In the chip design process, a Wafer Acceptance Test (WAT) is required to measure the electrical parameters of a specific Test structure after the Wafer product flow interpretation is finished and before the quality inspection, so as to detect the process condition of each Wafer product, evaluate the quality and stability of the chip manufacturing process, and determine whether the Wafer product meets the electrical specification requirements of the process technology platform.

Currently, in electrical Test circuits for electrical parametric testing, multiple Devices Under Test (DUTs) are connected to the same input signal pad.

However, the lengths of the metal wires between the dut and the input signal pads at different positions are different, which causes different resistances of the metal wires between the dut and the input signal pads, and further causes a difference in the test voltage actually applied to the dut due to the different positions of the dut, which affects the accuracy of the electrical test result.

Disclosure of Invention

Embodiments of the present disclosure provide an electrical test structure circuit, a chip, a system, a method, an electronic device and a storage medium to at least solve the above problems.

According to a first aspect of embodiments of the present application, there is provided an electrical property testing circuit, including: at least one input signal pad and at least one array of devices under test formed on a semiconductor substrate, each said array of devices under test comprising at least two devices under test; each of the devices under test is connected to at least one of the input signal pads through metal lines formed on the semiconductor substrate; each input signal pad and the tested devices connected to the input signal pad through metal wires in the same tested device array form a tree structure, and the lengths of the metal wires between the tested devices connected to the input signal pad in the same tested device array and the input signal pad are equal.

According to a second aspect of the embodiments of the present application, there is provided an electrical testing chip, including the electrical testing circuit according to the first aspect.

According to a third aspect of the embodiments of the present application, there is provided an electrical testing system including the electrical testing chip of the second aspect.

According to a fourth aspect of the embodiments of the present application, there is provided an electrical testing method, including: sending an electrical test signal to a device under test through at least one input signal pad, wherein at least one input signal pad and at least one device under test array are formed on a semiconductor substrate, each device under test array comprises at least two devices under test, each device under test is connected with at least one input signal pad through a metal wire formed on the semiconductor substrate, each input signal pad and each device under test connected to the input signal pad through the metal wire in the same device under test array form a tree structure, and the lengths of the metal wires between the device under test connected to the input signal pad in the same device under test array and the input signal pad are equal; acquiring an electrical feedback signal formed by the tested device in response to the electrical test signal; and determining an electrical test result of the tested device according to the electrical feedback signal.

According to a fifth aspect of embodiments of the present application, there is provided an electronic apparatus, including: the system comprises a processing unit, a memory, a communication interface and a communication bus, wherein the processing unit, the memory and the communication interface complete mutual communication through the communication bus; the memory is used for storing at least one executable instruction, and the executable instruction enables the processing unit to execute the operation corresponding to the electrical testing method provided by the fourth aspect.

According to a sixth aspect of embodiments of the present application, there is provided a computer storage medium having a computer program stored thereon, the program, when executed by a processor, implementing the electrical testing method of the fourth aspect.

According to the technical scheme, each input signal bonding pad and each tested device connected to the input signal bonding pad through a metal wire in the same tested device array form a tree structure, so that the lengths of the metal wires between each tested device connected to the input signal bonding pad in the same tested device array and the input signal bonding pad are equal. Each tested device in the same tested device array and the input signal pad connected with each tested device form a tree structure, and the length of the metal wire between each tested device and the input signal pad is the same, so that the resistances of the metal wires between the tested devices at different positions and the input signal pad are the same, and different voltage drops cannot be generated due to introduction of different resistance values when voltages are applied to the tested devices through the input signal pads respectively, thereby reducing the interference on test results and improving the accuracy of electrical test on the tested devices.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a schematic diagram of an exemplary circuit employed by one embodiment of the present application;

FIG. 2 is a schematic diagram of a conventional electrical test circuit according to one embodiment of the present application;

FIG. 3 is a schematic diagram of an electrical testing circuit according to one embodiment of the present application;

FIG. 4 is a schematic diagram of an input signal pad and a device under test according to an embodiment of the present application;

FIG. 5 is a schematic illustration of a metal line segment according to one embodiment of the present application;

FIG. 6 is a schematic diagram of an electrical test circuit according to another embodiment of the present application;

FIG. 7 is a flow chart of a method of electrical testing according to one embodiment of the present application;

FIG. 8 is a schematic view of an electronic device of an embodiment of the application.

Detailed Description

The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of the present application, some specific details are set forth in detail. It will be apparent to one skilled in the art that the present application may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present application. The figures are otherwise not necessarily drawn to scale.

First, some nouns or terms appearing in the process of describing the embodiments of the present application are applicable to the following explanations.

Electrical property test: and testing performance indexes of the electrical element, such as rated voltage, current, active power, reactive power, resistance, capacitance, inductance, conductance and the like. In the embodiments of the present application, the test is performed on one or more of dc amplification, ac amplification, rectified current, reverse breakdown voltage, forward on voltage, junction capacitance, noise figure, characteristic frequency, cut-off frequency, and dissipated power of a device under test formed on a semiconductor substrate.

The device under test: and electrical elements such as MOS transistors, resistors, etc. formed on the semiconductor substrate. The device under test can be a single electric element, or can be a combination of a plurality of electric elements connected according to a certain topological relation to form the electric element.

Input signal pad: the metal wire is used for connecting an external power supply so as to apply set voltage, current and the like to the tested device connected through the metal wire when the tested device is electrically tested.

A metal wire: the metal wires are formed on the wafer and used for connecting the tested device and the input signal bonding pad, and the metal wires can be made of gold, aluminum, alloy copper and the like.

Exemplary Circuit

FIG. 1 illustrates an exemplary circuit suitable for use in an electrical testing circuit according to embodiments of the present application. As shown in fig. 1, the circuit includes a plurality of input signal pads 10 formed on a semiconductor substrate and a plurality of device under test arrays 20, each device under test array 20 including a plurality of devices under test 21, each device under test 21 connected to one or more of the input signal pads 10. Each device under test 21 in the same device under test array 20 is the same type of electrical component, and the devices under test 21 in different device under test arrays 20 may be the same type of electrical component or different types of electrical components.

Since each device under test 21 in the same device under test array 20 is the same type of electrical component, the input signal pads 10 to which each device under test 21 in the same device under test array 20 is connected are the same. For example, if the dut 21 in one dut array 20 is a MOS transistor, each dut 21 in the dut array 20 needs to be connected to three input signal pads 10, which serve as a gate, a source, and a drain, respectively.

Each device under test 21 in the same device under test array 20 multiplexes the same one or more input signal pads 10, which can reduce the area occupied by the electrical test circuit, thereby forming a plurality of device under test arrays 20 on the same wafer and reducing the cost of performing electrical tests on the device under test 21.

The number of devices under test 21 in different arrays of devices under test 20 may be the same or different. For example, the type of the device under test 21 in one device under test array 20 is a MOS transistor, the device under test array 20 includes 32 devices under test 21, the type of the device under test 21 in another device under test array 20 is a resistor, and the device under test array 20 includes 128 devices under test 21.

It should be noted that the semiconductor substrate in the embodiment of the present application may be a wafer.

Fig. 2 is a schematic diagram of a conventional electrical test circuit according to an embodiment of the present application. As shown in fig. 2, a first-level metal line 201 is connected to the input signal pad 10, a plurality of second-level metal lines 202 are connected to the first-level metal line 201, and each second-level metal line 202 is connected to a plurality of devices under test 21 through a plurality of third-level metal lines 203. As can be seen from fig. 2, the lengths of the metal lines between the devices under test 21 and the input signal pads 10 are different, the length of the metal line between the device under test 21 and the input signal pad 10 in the lower left corner is the smallest, and the length of the metal line between the device under test 21 and the input signal pad 10 in the upper right corner is the largest. Because the lengths of the metal wires connecting the tested devices 21 at different positions to the input signal pad 10 are different, the resistances of the metal wires between different tested devices 21 and the input signal pad 10 are different, and thus different resistance values are introduced when electrical tests are performed on different tested devices 21, and different voltage drops (IR drop) are caused, so that interference is caused on test results, and the accuracy of the electrical test results is affected.

The embodiment of the present application provides an electrical property testing circuit, an electrical property testing chip and an electrical property testing system, so as to at least partially solve the above problems, and enable the metal wires connecting the device under test 21 and the input signal pads 10 to introduce the same resistance value, thereby ensuring the accuracy of the electrical property testing result.

Electrical property test circuit

FIG. 3 is a schematic diagram of an electrical testing circuit according to an embodiment of the present application. As shown in fig. 3, the electrical test circuit includes at least one input signal pad 10 and at least one device under test array 20 formed on a semiconductor substrate, each device under test array 20 includes at least two devices under test 21, and each device under test 21 is connected to at least one input signal pad 10 through a metal line formed on the semiconductor substrate. Each input signal pad 10 and each device under test 21 connected to the input signal pad 10 by a metal wire in the same device under test array 20 form a tree structure, and the lengths of the metal wires between each device under test 21 connected to the input signal pad 10 in the same device under test array 20 and the input signal pad 10 are equal.

Depending on the type of device under test 21, the device under test 21 is connected to one or more input signal pads 10. For example, if the device under test 21 is a MOS transistor, the device under test 21 needs to be connected to 3 input signal pads 10 corresponding to a gate, a source, and a drain, respectively, and if the device under test 21 is a resistor, the device under test 21 needs to be connected to 2 input signal pads 10 serving as an anode and a cathode, respectively.

The devices under test 21 in the same array of devices under test 20 are the same type of electrical element, so the input signal pads 10 to which each device under test 21 in the same array of devices under test 20 is connected are the same. For example, if the device under test 21 in a certain device under test array 20 is a MOS transistor, the gate, the source and the drain of each device under test 21 in the device under test array 20 are respectively connected to 3 input signal pads 10.

For each input signal pad 10, when the device under test 21 in a certain device under test array 20 is connected to the input signal pad 10, the input signal pad 10 is connected to each device under test 21 in the device under test array 20 through a metal wire to form a tree structure, so that the lengths of the metal wires between the input signal pad 10 and each device under test 21 in the device under test array 20 are equal.

Since the same input signal pad 10 can be connected to the devices under test 21 in different device under test arrays 20, the input signal pad 10 and each device under test 21 in the same device under test array 20 are connected by metal wires to form a tree structure, when a certain input signal pad 10 is connected to the devices under test 21 in a plurality of device under test arrays 20, the input signal pad 10 and each device under test 21 in each device under test array 20 form a tree structure, that is, when the input signal pad 10 is connected to the devices under test 21 in M device under test arrays 20, M tree structures including the input signal pad 10 can be formed. In different tree structures, the lengths of the metal lines between the input signal pads 10 and the devices under test 21 may be the same or different.

In the embodiment of the present application, each input signal pad 10 and each device under test 21 connected to the input signal pad 10 through a metal line in the same device under test array 20 form a tree structure, so that the lengths of the metal lines between each device under test 21 connected to the input signal pad 10 in the same device under test array 20 and the input signal pad 10 are equal. Each device under test 21 in the same device under test array 20 and the input signal pad 10 connected to each other form a tree structure, and the lengths of the metal wires between each device under test 21 and the input signal pad 10 are the same, so that the resistances of the metal wires between the device under test 21 and the input signal pad 10 at different positions are the same, and when voltages are respectively applied to each device under test 21 through the input signal pad 10, different voltage drops cannot be generated due to introduction of different resistance values, thereby reducing interference on test results and improving accuracy of electrical tests on the device under test 21.

In one possible implementation, the metal lines between the input signal pad 10 and each device under test 21 connected to the input signal pad 10 in the same device under test array 20 include 2N-1 metal line segments, where N is the number of devices under test 21 in the device under test array 20. In 2N-1 metal line segments, the first end of the 1 st metal line segment is connected with the input signal pad 10, the second end of each ith metal line segment is respectively connected with the first ends of two (i + 1) th metal selection segments, i is a positive integer less than h, and h =1+ log + ₂ And N, the second end of each h-th metal line segment is connected with a tested device 21.

The number of devices under test 21 in the device under test array 20 is N, and each device under test 21 is connected to the input signal pad 10 through a metal line. The first end of the 1 st metal line segment is connected with the input signal pad 10, the second end of each ith metal line segment is connected with the first ends of two (i + 1) th metal line segments, the second end of each ith metal line segment is connected with one tested device 21, and the total number of the ith metal line segments is 2 ^i-1 For example, the total number of the 1 st metal line segment is 1, the total number of the 2 nd metal line segment is 2, the total number of the 3 rd metal line segment is 4, and the total number of the h th metal line segment is 2 ^h-1 The number of the 1 st to h th metal line segments forms an equal ratio sequence, and according to a summation formula of the equal ratio sequence, the total number of the 1 st to h th metal line segments can be determined to be equal to 2N-1. Connected by 2N-1 metal line segments according to the mode to form a circuit board comprising an input signal pad 10 and the same testedA tree structure of each device under test 21 in the device array 20.

It should be noted that the number N of devices under test 21 in the device under test array 20 is equal to 2 in the embodiment of the present application ^h-1 For example, in actual business implementation, the number of devices under test 21 in the device under test array 20 may not be equal to the power of 2. When the number of the devices 21 in the device under test array 20 is not equal to the exponential power of 2, the devices 21 are not connected to some h-th metal line segments.

It should be understood that the metal line segment refers to a segment of metal line, and for convenience of describing the technical solution of the present application, the metal line between the input signal pad 10 and the device under test 21 is divided into a plurality of metal line segments, and actually the metal line between the input signal pad 10 and the device under test 21 is a continuous metal wire. In the embodiment of the present application, the branch point on the metal line between the input signal pad 10 and the device under test 21 can be used as a dividing point, and the metal line can be divided into 2N-1 metal line segments.

FIG. 4 is a diagram illustrating an exemplary input signal pad to device under test according to an embodiment of the present application. As shown in fig. 4, if the number of devices under test 21 is 32, the number of the 6 th metal line segments is 32. And every two 6 th metal line segments are connected with a 5 th metal line segment, so that the number of the 5 th metal line segments is 16. And every two 5 th metal line segments are connected with one 4 th metal line segment, so that the number of the 4 th metal line segments is 8. And every two 4 th metal line segments are connected with one 3 rd metal line segment, so that the number of the 3 rd metal line segments is 4. Every two No. 3 metal line segments are connected with a No. 2 metal line segment, and the number of the No. 2 metal line segments is 2. Two No. 2 metal line segments are connected with one No. 1 metal line segment, and the number of the No. 1 metal line segments is 1. Therefore, metal lines between 32 tested devices 21 and input signal pad 10 include 1+2+4+8+16+32=63 metal line segments.

In the embodiment of the present application, the first end of the 1 st metal line segment is connected to the input signal pad 10, the second end of each i th metal line segment is connected to the first ends of two i +1 th metal selection segments, the second end of each h th metal line segment is connected to one tested device 21, the input signal pad 10 is connected to N tested devices 21 through 2N-1 metal line segments, so as to form a tree structure, the lengths of the metal lines between the input signal pad 10 and each tested device 21 can be equal, thereby avoiding introducing different resistance values in the electrical test process, and ensuring the accuracy of the electrical test result.

In one possible implementation manner, the length of each i +1 th metal line segment is equal, that is, when i is greater than 1, the length of each i-th metal line segment is equal. For example, the lengths of the 2 nd metal line segments are equal, the lengths of the 4 rd metal line segments are equal, the lengths of the 8 4 th metal line segments are equal, the lengths of the 16 th metal line segments are equal, and the lengths of the 32 th metal line segments are equal.

It should be understood that, each ith metal line segment has the same length, and each ith +1 metal line segment also has the same length, but the lengths of the ith metal line segment and the ith +1 metal line segment may be the same or different, and the embodiment of the present application is not limited thereto.

In the embodiment of the present application, except for the 1 st metal line segments with the number of 1, the ith metal line segments with the number of 1 have the same length, so that the length of the metal line between each tested device 21 and the input signal pad 10 is equal to the sum of the lengths of the 1 st metal line segment to the h-th metal line segment, and the length of the metal line between each tested device 21 and the input signal pad 10 is equal, thereby avoiding introducing different resistance values in the electrical test process, and ensuring the accuracy of the electrical test result.

In one possible implementation, the array of devices under test includes 2 ^m Line x 2 ⁿ Column of devices under test, 2 ^(m+n) N, m and N are positive integers greater than or equal to 2. The 2 nd metal line segment to the nth metal line segment, and the n +2 th metal line segment to the m + n +1 th metal line segment all comprise a first sub-metal line segment and a second sub-metal line segment, the second end of the first sub-metal line segment in the same metal line segment is connected with the first end of the second sub-metal line segment, and the first sub-metal line segment is perpendicular to the second sub-metal line segment. The (n + 1) th metal line segment comprises a first sub-metal line segment, a second sub-metal line segment and a third sub-metal line segment, and the first sub-metal line segment in the same (n + 1) th metal line segmentThe second end of the second sub-metal line segment is connected with the first end of the second sub-metal line segment, the second end of the second sub-metal line segment is connected with the first end of the third sub-metal line segment, the second end of the third sub-metal line segment is connected with the first end of the first sub-metal line segment in the (n + 2) th metal line segment, and the first sub-metal line segment and the third sub-metal line segment are both perpendicular to the second sub-metal line segment.

The first end of the first sub-metal line segment in the 2 nd metal line segment is connected with the second end of the 1 st metal line segment, the second end of the second sub-metal line segment in the jth metal line segment is connected with the first end of the first sub-metal line segment in the jth metal line segment, j is a positive integer which is larger than 1 and smaller than m + n +1, j is not equal to n +1, and the second end of the second sub-metal line segment in the m + n +1 th metal line segment is connected with a tested device.

As shown in fig. 4, the device under test array 20 includes 32 devices under test 21 in 4 rows × 8 columns, i.e., m =2,n =3. Fig. 5 is a schematic diagram of a metal line segment according to an embodiment of the present application, and referring to fig. 4 and 5, a 2 nd metal line segment 502, a 3 rd metal line segment 503, a 5 th metal line segment 505, and a 6 th metal line segment 506 all include a first sub-metal line segment and a second sub-metal line segment, and the first sub-metal line segment and the second sub-metal line segment in the same metal line segment are perpendicular. The 4 th metal line segment 504 includes a first sub-metal line segment, a second sub-metal line segment, and a third sub-metal line segment, and both the first sub-metal line segment and the third sub-metal line segment are perpendicular to the second sub-metal line segment. The first end of the first sub-segment in the 2 nd segment 502 is connected to the second end of the 1 st segment 501.

In the embodiment of the present application, the first end of the first sub-segment in the 2 nd segment is connected to the second end of the 1 st segment, the second end of the second sub-segment in the jth segment is connected to the first end of the first sub-segment in the j +1 th segment, and the second end of the second sub-segment in the m + n +1 th segment is connected to the device under test. Except for the 1 st metal line segment and the N +1 st metal line segment, the rest metal line segments comprise a first sub-metal line segment and a second sub-metal line segment which are vertically connected, the N +1 st metal line segment comprises a first sub-metal line segment and a third sub-metal line segment which are vertically connected with the second sub-metal line segment, and the value is that 2N-1 metal line segments are connected according to the mode to form a T-shaped tree structure.

In one possible implementation manner, the lengths of the first sub-metal line segments in each jth metal line segment are equal, and the lengths of the second sub-metal line segments in each jth metal line segment are equal. The lengths of the first sub-metal line segments in the m + n + 1-th metal line segments are equal, and the lengths of the second sub-metal line segments in the m + n + 1-th metal line segments are equal. The lengths of the first sub-metal line segments in the (n + 1) th metal line segments are equal, the lengths of the second sub-metal line segments in the (n + 1) th metal line segments are equal, and the lengths of the third sub-metal line segments in the (n + 1) th metal line segments are equal.

In the embodiment of the application, because the length of the metal wire between the input signal pad and the tested device is equal to the sum of the lengths of the 1 st to the m + n +1 th metal wire segments, and the sub-metal wire segments included by each metal wire segment are respectively equal in correspondence, the sum of the lengths of the 1 st to the m + n +1 th metal wire segments connected to each tested device is equal, on the premise that different resistance values cannot be introduced in the electrical test process, the layout of each tested device on the semiconductor substrate is more rounded, the design and processing of each tested device on the semiconductor substrate are facilitated, and the use experience of a user is improved while the accuracy of the test result is ensured.

In one possible implementation, when the number of the device under test arrays is plural, each input signal pad and each device under test array are arranged in a row, and at least one input signal pad is arranged between adjacent device under test arrays.

As shown in fig. 1, each input signal pad 10 and each device under test array 20 are arranged in a row, and at least one input signal pad 10 is arranged between two adjacent device under test arrays 20.

In the embodiment of the application, because different tested device arrays can share the input signal bonding pad, the input signal bonding pad is arranged between the tested device arrays, the tested devices are conveniently connected with the input signal bonding pad through the metal wire, so that the design difficulty of the electrical test circuit can be reduced, and the difficulty of forming the electrical test circuit on the semiconductor substrate can be reduced.

FIG. 6 is a schematic diagram of an electrical testing circuit according to another embodiment of the present application. As shown in fig. 6, the electrical test circuit further includes an address module 30 based on the input signal pads 10 and the device under test array 20. The addressing module 30 is disposed on metal lines connecting the input signal pads 10 and the device under test 21. The addressing module 30 may control the metal wire conduction between the target one of the devices under test 21 and the target one of the input signal pads 10 according to the received control instruction.

The addressing block 30 is disposed between the input signal pad 10 and the device under test 21, and metal lines connected to the input signal pad 10 and the device under test 21 at both ends enter the addressing block 30. The addressing module 30 can control the channels of the accessed metal lines, thereby controlling the on/off between each input signal pad 10 and each device under test 21. When an electrical test needs to be performed on a certain device under test 21, a control instruction may be sent to the addressing module 30, the addressing module 30 may turn on the metal wire between the device under test 21 and the corresponding input signal pad 10 according to the control instruction, so that a voltage may be applied to the device under test 21 to perform the electrical test on the device under test 21, and after the electrical test performed on the device under test 21 is completed, the addressing module 30 may disconnect the metal wire between the device under test 21 and the corresponding input signal pad 10.

In the embodiment of the application, the address selection module can control the on-off of the metal wire between each input signal pad and each tested device, so that the metal wire between each tested device and the corresponding input signal pad is conducted in sequence, each tested device is subjected to electrical test in sequence, multiple tested devices can multiplex the same input signal pads to perform electrical test, the accuracy of test results is guaranteed, and meanwhile the occupied area of an electrical test circuit is reduced.

In one possible implementation, the device under test may be a single electrical component or may be a plurality of connected electrical components. The electrical elements may be various types of electrical elements used in a chip, such as MOS transistors, resistors, and the like.

In the embodiment of the present application, the device under test may be a single electrical component, or may be a circuit structure formed by connecting a plurality of electrical components of the same or different types, so that the electrical test circuit provided in the embodiment of the present application may be suitable for performing electrical tests on the devices under test of different types, and the applicability of the electrical test circuit is improved.

Electric property test chip

The embodiment of the present application provides an electrical property testing chip, which includes the electrical property testing circuit in any of the above embodiments.

The electrical test chip includes a plurality of pins, which are directly or indirectly connected to the input signal pads in the electrical test circuit.

The electrical test chip may include a processing unit, which may be a CPU, or an Application Specific Integrated Circuit ASIC (Application Specific Integrated Circuit), or one or more Integrated circuits configured to implement embodiments of the present Application. The electronic device includes one or more processing units, which may be the same type of processing unit, such as one or more CPUs; or may be different types of processing units such as one or more CPUs and one or more ASICs.

RISC-V is an open source instruction set architecture based on the principle of Reduced Instruction Set (RISC), can be applied to various aspects such as a single chip microcomputer and an FPGA chip, and can be particularly applied to the fields of safety of the Internet of things, industrial control, mobile phones, personal computers and the like, and because the design considers the practical conditions of small size, high speed and low power consumption, the RISC-V is particularly suitable for modern computing equipment such as warehouse-scale cloud computers, high-end mobile phones, micro embedded systems and the like. With the rise of the artificial intelligence internet of things AIoT, the RISC-V instruction set architecture is paid more and more attention and supported, and is expected to become a CPU architecture widely applied in the next generation.

The computer operation instruction in the embodiment of the present application may be a computer operation instruction based on instruction set architectures such as RISC-V, ARM, and X86, and the processing unit may be designed based on a corresponding instruction set architecture. For example, when the computer operation instructions are based on the RSIC-V instruction set architecture, the processing units may be designed based on the instruction set of RISC-V.

Electrical property test system

The embodiment of the application provides an electrical property testing system, which comprises the electrical property testing chip and the controller in any embodiment, wherein the controller can control the electrical property testing chip to work.

The controller can send a control instruction to the electrical property test chip, and the electrical property test chip can test each device to be tested in the device array to be tested in sequence according to the received control instruction and the test rule of influence.

Those of ordinary skill in the art will appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

The above embodiments are only used for illustrating the embodiments of the present application, and not for limiting the embodiments of the present application, and those skilled in the relevant art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also belong to the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Electrical property testing method

FIG. 7 is a flowchart of an electrical testing method according to an embodiment of the present application. As shown in fig. 7, the electrical testing method includes the following steps:

step 701, sending an electrical test signal to a device under test through at least one input signal pad.

At least one input signal pad and at least one device under test array are formed on a semiconductor substrate, each device under test array comprises at least two devices under test, each device under test is connected with at least one input signal pad through a metal wire formed on the semiconductor substrate, each input signal pad and each device under test connected to the input signal pad through a metal wire in the same device under test array form a tree structure, and the lengths of the metal wires between each device under test connected to the input signal pad in the same device under test array and the input signal pad are equal.

The electrical testing method in this embodiment is a specific application of the electrical testing apparatus in the foregoing embodiment, and the structures of the input signal pad and the dut array can be referred to the description in the foregoing electrical testing apparatus embodiment, and are not described herein again.

When an electrical test of a device under test is required, an electrical test signal is sent to the device under test through one or more input signal pads to which the device under test is connected. According to different types of electrical tests performed on the device under test, electrical test signals can be sent to the device under test through different input signal pads. The electrical test signal may be a voltage, a current, etc. applied to the device under test.

Step 702 obtains an electrical feedback signal formed by the device under test in response to the electrical test signal.

After the electrical test signal is sent to the device under test, an electrical feedback signal formed by the device under test in response to the electrical test signal may be obtained. The electrical feedback signal may be obtained through an input signal pad that sends an electrical test signal to the device under test, or may be obtained through other ways, which is not limited in this embodiment of the present application.

In one example, the electrical feedback signal may be a current signal through the device under test when the electrical test signal is a voltage applied to the device under test, and the electrical feedback signal may be a voltage signal applied to the device under test when the electrical test signal is a current flowing through the device under test.

And 703, determining an electrical test result of the tested device according to the electrical test signal and the electrical feedback signal.

Based on the electrical test sent to the device under test and the electrical feedback signal generated by the device under test, the electrical test result of the device under test can be determined. The electrical test results may include resistance, turn-on voltage, etc. of the device under test.

In the embodiment of the present application, each input signal pad and each device under test connected to the input signal pad through a metal wire in the same device under test array form a tree structure, so that the lengths of the metal wires between each device under test connected to the input signal pad in the same device under test array and the input signal pad are equal. Each tested device in the same tested device array and the input signal pad connected with each other form a tree structure, and the length of the metal wire between each tested device and the input signal pad is the same, so that the resistances of the metal wires between the tested devices at different positions and the input signal pad are the same, and different voltage drops cannot be generated due to introduction of different resistance values when the input signal pads respectively send electrical test signals to the tested devices, thereby reducing the interference on test results and improving the accuracy of electrical test on the tested devices.

In a possible implementation manner, before the electrical test signal is sent to the device under test through the input signal pad, a control instruction may be sent to the addressing module, so that the addressing module controls the metal wire between the target device under test to be tested and the input signal pad to be conducted according to the control instruction. The addressing module is arranged on a metal wire connecting an input signal pad and a device to be tested.

Since each input signal pad is connected to a plurality of devices under test in the same device under test array, but when the devices under test are electrically tested, the devices under test need to be electrically tested one by one, and therefore the devices under test need to be electrically connected to the input signal pads one by one. The address selection module is arranged on a metal wire connecting the input signal bonding pad and the tested device, and can respond to the received control instruction to conduct the metal wire between the corresponding tested device and the input signal bonding pad so as to perform electrical test on the tested device.

In the embodiment of the application, the selection module conducts the metal wire between the corresponding tested device and the input signal pad by sending the control instruction to the address selection module, so that the electrical test signal can be sent to the tested device through the input signal pad, the electrical test of the tested devices can be performed one by one through the shared input signal pad, the cost of performing the electrical test on the tested devices is reduced, and meanwhile, the accuracy of the obtained test result is ensured.

It should be noted that the electrical testing method of the present embodiment is a specific application of the electrical testing apparatus in the foregoing embodiments, and specific structures of the electrical testing apparatus can be referred to the description in the foregoing embodiments, and have the beneficial effects of the corresponding apparatus embodiments, which are not described herein again.

Electronic device

Fig. 8 is a schematic block diagram of an electronic device according to an embodiment of the present application, and a specific embodiment of the present application does not limit a specific implementation of the electronic device. As shown in fig. 8, the electronic device may include: a processing unit (processor) 802, a Communications Interface (Communications Interface) 804, a memory (memory) 806, and a Communications bus 808. Wherein:

the processing unit 802, communication interface 804, and memory 806 communicate with one another via a communication bus 808.

A communication interface 804 for communicating with other electronic devices or servers.

The processing unit 802 is configured to execute the program 810, and may specifically perform the relevant steps in any of the above embodiments of the electrical testing method.

In particular, the program 810 may include program code comprising computer operating instructions.

The processing unit 802 may be a CPU, or an Application Specific Integrated Circuit ASIC (Application Specific Integrated Circuit), or one or more Integrated circuits configured to implement embodiments of the present Application. The electronic device includes one or more processing units, which may be the same type of processing unit, such as one or more CPUs; or may be different types of processing units such as one or more CPUs and one or more ASICs.

The computer operation instruction in the embodiment of the present application may be a computer operation instruction based on instruction set architectures such as RISC-V, ARM, and X86, and correspondingly, the processing unit 802 may be designed based on instruction sets such as RISC-V, ARM, and X86. Specifically, the chip of the processing unit in the electronic device provided in the embodiment of the present application may be a chip designed by using an instruction set such as RISC-V, ARM, and X86, and the chip may execute the executable code based on the configured instruction, thereby implementing the electrical testing method in the above embodiment.

The memory 806 stores a program 810. The memory 806 may include high-speed RAM memory, and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.

The program 810 may be specifically configured to enable the processing unit 802 to perform the electrical testing method in any of the embodiments described above.

For specific implementation of each step in the program 810, reference may be made to corresponding steps and corresponding descriptions in units in any of the foregoing embodiments of the electrical testing method, which are not described herein again. It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described devices and modules may refer to the corresponding process descriptions in the foregoing method embodiments, and are not described herein again.

With the electronic device according to the embodiment of the application, each input signal pad and each device under test connected to the input signal pad through a metal wire in the same device under test array form a tree structure, so that the lengths of the metal wires between each device under test connected to the input signal pad in the same device under test array and the input signal pad are equal. Each tested device in the same tested device array and the input signal pad connected with each other form a tree structure, and the length of the metal wire between each tested device and the input signal pad is the same, so that the resistances of the metal wires between the tested devices at different positions and the input signal pad are the same, and different voltage drops cannot be generated due to introduction of different resistance values when the input signal pads respectively send electrical test signals to the tested devices, thereby reducing the interference on test results and improving the accuracy of electrical test on the tested devices.

Computer storage medium

The present application also provides a computer-readable storage medium storing instructions for causing a machine to perform an electrical testing method as described herein. Specifically, a system or an apparatus equipped with a storage medium on which software program codes that realize the functions of any of the embodiments described above are stored may be provided, and a computer (or a CPU or MPU) of the system or the apparatus is caused to read out and execute the program codes stored in the storage medium.

In this case, the program code itself read from the storage medium can realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present application.

Examples of the storage medium for supplying the program code include a flexible disk, hard disk, magneto-optical disk, optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW), magnetic tape, nonvolatile memory card, and ROM. Alternatively, the program code may be downloaded from a server computer via a communications network.

Computer program product

Embodiments of the present application further provide a computer program product, which includes computer instructions for instructing a computing device to perform operations corresponding to any of the above method embodiments.

It should be noted that, according to the implementation requirement, each component/step described in the embodiment of the present application may be divided into more components/steps, and two or more components/steps or partial operations of the components/steps may also be combined into a new component/step to achieve the purpose of the embodiment of the present application.

The above-described methods according to embodiments of the present application may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CD ROM, a RAM, a floppy disk, a hard disk, or a magneto-optical disk, or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the methods described herein may be stored in such software processes on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware such as an ASIC or FPGA. It will be appreciated that a computer, processor, microprocessor controller, or programmable hardware includes memory components (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by a computer, processor, or hardware, implements the methods described herein. Further, when a general-purpose computer accesses code for implementing the methods illustrated herein, execution of the code transforms the general-purpose computer into a special-purpose computer for performing the methods illustrated herein.

Claims

1. An electrical property testing circuit comprising: at least one input signal pad and at least one array of devices under test formed on a semiconductor substrate, each said array of devices under test comprising at least two devices under test;

each of the devices under test is connected to at least one of the input signal pads through metal lines formed on the semiconductor substrate;

each input signal pad and the tested devices connected to the input signal pad through metal wires in the same tested device array form a tree structure, and the lengths of the metal wires between the tested devices connected to the input signal pad in the same tested device array and the input signal pad are equal.

2. The electrical test circuit of claim 1, wherein the metal lines between the input signal pad and each of the devices under test connected to the input signal pad in the same array of devices under test comprise 2N-1 metal line segments, N being the number of devices under test in the array of devices under test;

the first end of the 1 st metal line segment is connected with the input signal pad;

the second end of each ith metal line segment is respectively connected with the first ends of two (i + 1) th metal line segments, i is a positive integer less than h, and h =1+ log ₂ N；

The second end of each h-th metal line segment is connected with the tested device.

3. The electrical testing circuit of claim 2, wherein the i +1 th metal line segments are equal in length.

4. The electrical testing circuit of claim 2, wherein the array of devices under test comprises 2 ^m Line x 2 ⁿ Column of said devices under test, 2 ^(m+n) N, m and N are positive integers greater than or equal to 2;

the 2 nd metal line segment to the nth metal line segment and the n +2 th metal line segment to the m + n +1 th metal line segment comprise a first sub-metal line segment and a second sub-metal line segment, the second end of the first sub-metal line segment is connected with the first end of the second sub-metal line segment in the same metal line segment, and the first sub-metal line segment is vertical to the second sub-metal line segment;

the n +1 th metal line segment comprises a first sub-metal line segment, a second sub-metal line segment and a third sub-metal line segment, the second end of the first sub-metal line segment in the same n +1 th metal line segment is connected with the first end of the second sub-metal line segment, the second end of the second sub-metal line segment is connected with the first end of the third sub-metal line segment, the second end of the third sub-metal line segment is connected with the first end of the first sub-metal line segment in the n +2 th metal line segment, and the first sub-metal line segment and the third sub-metal line segment are both vertical to the second sub-metal line segment;

the first end of the first sub-metal line segment in the 2 nd metal line segment is connected with the second end of the 1 st metal line segment;

the second end of the second sub-metal line segment in the jth metal line segment is connected with the first end of the first sub-metal line segment in the jth +1 metal line segment, j is a positive integer which is larger than 1 and smaller than m + n +1, and j is not equal to n +1;

and the second end of the second sub-metal line segment in the m + n +1 th metal line segment is connected with the tested device.

5. The electrical testing circuit of claim 4,

the lengths of the first sub-metal line segments in the jth metal line segment are equal, and the lengths of the second sub-metal line segments in the jth metal line segment are equal;

the lengths of the first sub-metal line segments in the m + n +1 th metal line segments are equal, and the lengths of the second sub-metal line segments in the m + n +1 th metal line segments are equal;

the lengths of the first sub-metal line segments in the (n + 1) th metal line segments are equal, the lengths of the second sub-metal line segments in the (n + 1) th metal line segments are equal, and the lengths of the third sub-metal line segments in the (n + 1) th metal line segments are equal.

6. The electrical testing circuit of claim 1, wherein the number of the device under test arrays is plural, each of the input signal pads and each of the device under test arrays are arranged in a row, and at least one of the input signal pads is arranged between adjacent ones of the device under test arrays.

7. The electrical testing circuit of claim 1, further comprising: an address selection module;

the addressing module is arranged on a metal wire connecting the input signal bonding pad and the tested device;

and the addressing module is used for controlling the metal wire between the target tested device and the target input signal bonding pad to be conducted according to the received control instruction.

8. The electrical test circuit of any of claims 1-7, wherein the device under test comprises a single electrical component or a plurality of electrical components connected.

9. An electrical test chip comprising an electrical test circuit according to any one of claims 1 to 8.

10. An electrical property testing system comprising:

the electrical test chip of claim 9;

and the controller is used for controlling the electric property testing chip to work.

11. An electrical property testing method, comprising:

sending an electrical test signal to a device under test through at least one input signal pad, wherein at least one input signal pad and at least one device under test array are formed on a semiconductor substrate, each device under test array comprises at least two devices under test, each device under test is connected with at least one input signal pad through a metal wire formed on the semiconductor substrate, each input signal pad and each device under test connected to the input signal pad through the metal wire in the same device under test array form a tree structure, and the lengths of the metal wires between each device under test connected to the input signal pad in the same device under test array and the input signal pad are equal;

acquiring an electrical feedback signal formed by the device under test responding to the electrical test signal;

and determining an electrical test result of the tested device according to the electrical test signal and the electrical feedback signal.

12. The method of claim 11, further comprising: and sending a control instruction to an address selection module to enable the address selection module to control the conduction of a metal wire between a target tested device to be tested and the input signal bonding pad according to the control instruction, wherein the address selection module is arranged on the metal wire connecting the input signal bonding pad and the tested device.

13. An electronic device, comprising: the system comprises a processing unit, a memory, a communication interface and a communication bus, wherein the processing unit, the memory and the communication interface complete mutual communication through the communication bus;

the memory is used for storing at least one executable instruction, and the executable instruction causes the processing unit to execute the operation corresponding to the electrical testing method according to claim 11 or 12.

14. A computer storage medium having stored thereon a computer program which, when executed by a processor, implements the electrical testing method of claim 11 or 12.