CN115579416A - Preparation method of semiconductor device and semiconductor device - Google Patents

Preparation method of semiconductor device and semiconductor device Download PDF

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Publication number
CN115579416A
CN115579416A CN202211191562.XA CN202211191562A CN115579416A CN 115579416 A CN115579416 A CN 115579416A CN 202211191562 A CN202211191562 A CN 202211191562A CN 115579416 A CN115579416 A CN 115579416A
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China
Prior art keywords
semiconductor device
layer
metal layer
sacrificial layer
groove
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Pending
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CN202211191562.XA
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Chinese (zh)
Inventor
王俊力
谢红梅
周健
吴瑶
王曦
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Priority to CN202211191562.XA priority Critical patent/CN115579416A/en
Publication of CN115579416A publication Critical patent/CN115579416A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The method comprises the following steps: providing a semiconductor device initial body; forming a metal layer covering the top surface of the semiconductor device primary body and covering the inner side wall and the bottom surface of the groove but not filling the groove; forming a sacrificial layer, wherein the sacrificial layer covers the metal layer, and the thickness of the sacrificial layer at the groove is larger than that of the sacrificial layer at the top surface of the primary body of the semiconductor device; the etching selection ratio of the material of the metal layer to the material of the sacrificial layer is greater than or equal to 100; partially removing the sacrificial layer, and remaining at least part of the sacrificial layer in the groove; partially removing the metal layer, and only remaining the residual metal layer on partial inner side wall and bottom surface of the groove; and removing the residual sacrificial layer. The preparation method of the semiconductor device and the semiconductor device provided by the invention enable the performance of the semiconductor device to be more stable.

Description

Preparation method of semiconductor device and semiconductor device
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor device and the semiconductor device.
Background
Infrared imaging technology is increasingly widely used in the fields of industrial sensing, image monitoring, the automotive industry, fire fighting, search and rescue, even military navigation and night vision, etc. The infrared focal plane detector is an imaging sensor which can simultaneously realize the acquisition of infrared information and the information processing, and is a core component of the infrared imaging technology. Infrared focal plane detectors typically include a photosensor chip and silicon readout circuitry.
Wherein, in the processing process of the photosensitive element chip, a procedure that an aluminum (Al) material layer is etched by a wet method and is stopped at a titanium (Ti) material layer is involved. Typically, this process is prepared using conventional Photolithography (PH) and Etching (ET) using WET Etching (WET ET) to ensure that the titanium material layer is not damaged. However, the photoresist is easy to peel off (peeling) in the wet etching process, so that false corrosion is caused. Further, the shape of the aluminum material layer is unstable, and the performance of the photosensitive element chip is affected.
Disclosure of Invention
In view of the above, embodiments of the present application provide a method for manufacturing a semiconductor device and a semiconductor device to solve at least one problem in the background art.
In order to achieve the purpose, the technical scheme of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, where the method includes:
providing a semiconductor device primary body, wherein the semiconductor device primary body comprises a groove extending from the top surface to the inner part;
forming a metal layer covering the top surface of the semiconductor device primary body and covering the inner side walls and the bottom surface of the groove but not filling the groove;
forming a sacrificial layer, wherein the sacrificial layer covers the metal layer, and the thickness of the sacrificial layer at the groove is larger than that of the top surface of the semiconductor device primary body; the etching selection ratio of the material of the metal layer to the material of the sacrificial layer is greater than or equal to 100;
partially removing the sacrificial layer, and remaining at least part of the sacrificial layer in the groove;
partially removing the metal layer, and only remaining the residual metal layer on partial inner side wall and bottom surface of the groove;
and removing the residual sacrificial layer.
Optionally, the forming a sacrificial layer includes:
forming a sacrificial material layer covering the metal layer, wherein the sacrificial material layer fills the part of the groove which is not filled by the metal layer;
and performing a planarization process on the sacrificial material layer to form the sacrificial layer, wherein the thickness of the sacrificial layer at the groove is larger than that at the top surface of the semiconductor device primary body.
Optionally, the step of partially removing the sacrificial layer, and/or the step of removing the remaining sacrificial layer are implemented by using a dry etching process.
Optionally, a reactive ion etching process is used to partially remove the sacrificial layer, and at least part of the remaining sacrificial layer located in the trench remains.
Optionally, the metal layer is formed by a sputtering coating process.
Optionally, the metal layer is partially removed by a wet etching process.
Optionally, the removing the remaining sacrificial layer includes:
and performing chemical etching by using hydrogen fluoride as etching gas to remove the residual sacrificial layer.
Optionally, before forming the metal layer, the method further comprises:
and forming a conductive layer which covers the top surface of the primary body of the semiconductor device, covers the inner side wall and the bottom surface of the groove and does not fill the groove.
Optionally, the forming a metal layer includes:
the metal layer covers a part of the conductive layer in the groove and does not fill the groove.
In a second aspect, embodiments of the present application provide a semiconductor device, which is prepared by any one of the above-mentioned methods for manufacturing a semiconductor device.
The semiconductor device and the preparation method thereof provided by the embodiment of the application comprise the steps of forming a metal layer; forming a sacrificial layer, wherein the sacrificial layer covers the metal layer, and the thickness of the sacrificial layer at the groove is larger than that of the top surface of the semiconductor device primary body; the etching selection ratio of the material of the metal layer to the material of the sacrificial layer is greater than or equal to 100; partially removing the sacrificial layer, and only remaining part of the sacrificial layer in the groove; partially removing the metal layer, and only remaining the residual metal layer on partial inner side wall and bottom surface of the groove; and removing the residual sacrificial layer. In order to enable the metal layer to have good and stable appearance after being etched, a sacrificial layer is formed before the metal layer is etched; and setting the etching selection ratio of the material of the metal layer to the material of the sacrificial layer to be greater than or equal to 100. Therefore, when the sacrificial layer is etched, the metal layer cannot be damaged by the etchant for etching the sacrificial layer, and when the metal layer is etched, the remaining sacrificial layer cannot be damaged by the etchant for etching the metal layer, so that the sacrificial layer has a stable boundary shape and can prevent the etchant from entering the side wall of the metal layer adjacent to the remaining sacrificial layer, and the etched remaining metal layer and the side wall of the sacrificial layer have good and stable appearances. Therefore, the preparation method of the semiconductor device and the semiconductor device provided by the embodiment of the application can enable the etched metal layer to have good and stable appearance, and enable the performance of the semiconductor device to be more stable.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 2, fig. 4, fig. 6, and fig. 8 are schematic cross-sectional views illustrating processes in a method for manufacturing a semiconductor device according to an embodiment of the present application;
FIG. 3 is an enlarged view of a portion of FIG. 2 at A;
FIG. 5 is a partial enlarged view of the portion B in FIG. 4;
FIG. 7 is an enlarged view of a portion of FIG. 6 at C;
FIG. 9 is an enlarged view of a portion of FIG. 8 at D;
fig. 10 is a schematic cross-sectional view of a corresponding structure of a method for manufacturing a semiconductor device provided by an embodiment of the present application during execution;
fig. 11 is a partially enlarged view of fig. 10 at E.
Description of the reference numerals:
20. a semiconductor device substrate; 21. a trench; 30. a metal layer; 40. a sacrificial layer; 22. a conductive layer; 23. a wiring layer; 24. a first dielectric layer; 25. an isolation layer; 26. a second dielectric layer.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "8230;" \8230 "", "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "8230," "over," "with," "8230," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relational terms such as "in 8230," "below," "in 8230," "below," "8230," "above," "above," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230; \8230; below" and "at 8230; \8230; below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.
To solve the technical problem in the prior art, an embodiment of the present application provides a method for manufacturing a semiconductor device, fig. 1 is a schematic flow diagram of the method for manufacturing the semiconductor device provided by the embodiment of the present application, and fig. 2 to 9 are schematic cross-sectional view and schematic partial enlarged view of each process in the method for manufacturing the semiconductor device provided by the embodiment of the present application, and with reference to fig. 1 to 9, the method includes:
step 101: providing a semiconductor device initial body, wherein the semiconductor device initial body comprises a groove 21 extending from a top surface to the inside;
step 102: forming a metal layer 30, wherein the metal layer 30 covers the top surface of the semiconductor device primary body and covers the inner side wall and the bottom surface of the groove 21 but does not fill the groove 21;
step 103: forming a sacrificial layer 40, wherein the sacrificial layer 40 covers the metal layer 30, and the thickness of the sacrificial layer 40 at the position of the groove 21 is larger than that at the position of the top surface of the semiconductor device primary body; the etching selection ratio of the material of the metal layer 30 to the material of the sacrificial layer 40 is greater than or equal to 100;
step 104: partially removing the sacrificial layer 40, and remaining the remaining sacrificial layer 40 at least partially in the trench 21;
step 105: partially removing the metal layer 30, and only remaining metal layers 30 located on part of the inner side wall and the bottom surface of the trench 21 are remained;
step 106: the remaining sacrificial layer 40 is removed.
The preparation method of the semiconductor device provided by the embodiment of the application can be used for preparing a photosensitive element chip in an infrared focal plane detector, and particularly, the preparation method of the embodiment of the application is mainly used for preparing an air bridge in a focal plane array in the photosensitive element chip. The following description will mainly take the air bridge as an example. It can be understood that the method for manufacturing a semiconductor device of the embodiment of the present application can also be used for manufacturing other semiconductor devices.
In step 101, the semiconductor device initial body may be a semi-finished product in a semiconductor device manufacturing process. The semiconductor device body comprises a trench 21 extending from the top surface towards the inside, i.e. the trench 21 is formed by extending the top surface of the semiconductor device body downwards.
In some embodiments, the semiconductor device precursor may include a semiconductor device substrate 20, a wiring layer 23, a first dielectric layer 24, an isolation layer 25, a second dielectric layer 26, and a trench 21. Wherein:
a trench 21 extending from the top surface of the semiconductor device substrate 20 to the inside;
a first dielectric layer 24 formed on the semiconductor device substrate 20 to cover a top surface of the semiconductor device substrate 20;
and a wiring layer 23 formed on the semiconductor device substrate 20. At least a part of the wiring layer 23 is exposed via the trench 21;
an isolation layer 25 formed on the first dielectric layer 24 and divided into a plurality of parts not communicated with each other by the trench 21;
a second dielectric layer 26, wherein the second dielectric layer 26 covers the top surface of the isolation layer 25 and the inner wall of the trench 21 and does not fill the trench 21; the second dielectric layer 26 covers the inner wall of the trench 21.
In some embodiments, the material of the wiring layer 23 may include aluminum. The material of the isolation layer 25 and the second dielectric layer 26 may each comprise silicon dioxide (SiO) 2 )。
In this embodiment, the semiconductor device may be the above-mentioned light-sensitive element chip, and the semiconductor device primary body may be a light-sensitive element chip primary body. As shown in fig. 2, the air bridge of the photosensor chip shows two grooves 21, and the two grooves 21 are used to form piers at both ends of the air bridge. For simplicity, the present embodiment only describes a method for manufacturing one of the air bridges, and it can be understood that the method for manufacturing a semiconductor device provided in the embodiments of the present application can be used to manufacture all the air bridges in the focal plane array in the photosensor chip. The preparation of all air bridges may include the simultaneous preparation of all air bridges, or may include the separate preparation of all air bridges. Illustratively, the air bridge is prepared by preparing a partial structure of the air bridge.
In the step 102, as shown in fig. 2, the metal layer 30 does not fill the trench 21, and it can be considered that a metal film layer with a predetermined thickness is coated on the inner wall surface of the trench 21 instead of filling the trench 21. Illustratively, the metal layer 30 functions as a bridge pier supporting an air bridge. The semiconductor device further comprises a conductive layer 22 electrically connected with the bridge deck photosensitive element, the conductive layer 22 is partially located in the bridge pier region, and the metal layer 30 supports the bridge piers and also plays a role in supporting the conductive layer 22. Therefore, the metal layer 30 has a good and stable morphology, which enables the supporting function to be more stable and reliable, and further enables the performance of the semiconductor device to be more stable.
In some embodiments, in step 102, the forming the metal layer 30 includes:
the metal layer 30 is formed on the semiconductor device primary body by a sputter coating (sputter) process.
Illustratively, for a metal material with certain hardness, the sputtering coating process is adopted, and the characteristics of uniform film thickness and high film forming efficiency are achieved. Therefore, the metal layer 30 having a relatively uniform film thickness can be obtained by the sputtering process. In some embodiments, the material of the metal layer 30 may include aluminum, but may be other metal materials with certain strength.
In step 103, as shown in fig. 3, after the sacrificial layer 40 is formed, the trench 21 is filled. The thickness of the sacrificial layer at the trench comprises the sum of the thicknesses of the sacrificial layer within and over the trench. The etching selection ratio of the material of the metal layer to the material of the sacrificial layer is greater than or equal to 100, so that the sacrificial layer 40 can be used as a mask layer for etching the metal layer 30 when the metal layer 30 is etched in step 105. Compared with other related technologies, the technical scheme of etching the metal layer 30 by using photoresist as a mask is provided. The preparation method of the semiconductor device can overcome the problem that the photoresist is easy to peel off in wet etching, so that the sidewalls of the metal layer 30 and the sacrificial layer 40 which are remained after etching have good and stable appearances, the times of the photoetching process can be reduced, and the influence of the execution of the photoetching process on the production cost can be reduced.
In some embodiments, in step 103, the forming the sacrificial layer 40 includes:
forming a sacrificial material layer covering the metal layer, the sacrificial material layer filling the portion of the trench 21 not filled by the metal layer 30;
and performing a planarization process on the sacrificial material layer to form the sacrificial layer 40, wherein the thickness of the sacrificial layer 40 at the position of the groove 21 is larger than that at the position of the top surface of the semiconductor device primary body.
Illustratively, the material forming the sacrificial layer 40 may be an insulating dielectric material. The insulating medium material meets the following requirements: the insulating medium material does not generate chemical or similar reaction with the metal layer 30 and does not damage the metal layer 30; the etching selection ratio of the insulating medium material to the metal layer 30 is more than 100. Illustratively, forming the sacrificial material layer overlying the metal layer may employ a deposition process. In some embodiments, the material of the sacrificial layer 40 may include silicon dioxide, but may also be other materials, such as Polyimide (PI, polyimide), and the like.
Illustratively, the purpose of making the thickness of the sacrificial layer 40 at the trench 21 greater than the thickness at the top surface of the semiconductor device primary body is to: to achieve that the portion of the sacrificial layer 40 covering the metal layer 30 located in the trench 21 is partially left when the sacrificial layer 40 is etched. The reason is that: since it is necessary to deposit an insulating dielectric material on all surfaces of the metal layer 30, and the insulating dielectric material is required to fill the portion of the trench 21 not filled by the metal layer 30. The thicknesses of the insulating dielectric material deposited on the top surface of the metal layer 30 and the insulating dielectric material in the trench 21 are similar according to the characteristics of the deposition process. Thus, the thickness of the sacrificial layer 40 at the position of the groove 21 is larger than that at the position of the top surface of the semiconductor device primary body, so that the part of the sacrificial layer 40 covering the metal layer 30 can be partially remained when the sacrificial layer 40 is etched. Specifically, making the thickness of the sacrificial layer 40 at the trench 21 larger than the thickness at the top surface of the semiconductor device primary body may be achieved by a planarization process. Illustratively, the top surface of the sacrificial material layer may also be made more planar by a planarization process, facilitating the etching process.
As shown in fig. 4, in the step 104, the sacrificial layer 40 is partially removed, and the remaining sacrificial layer 40 at least partially located in the trench 21 is remained for the purpose of: forming a mask layer to cover at least a portion of the metal layer 30 on the sidewall of the trench 21 and the metal layer 30 on the bottom surface of the trench 21. For example, since the metal layer 30 on at least a portion of the sidewall of the trench 21 and the metal layer 30 on the bottom surface of the trench 21 are covered by the mask layer, the metal layer 30 on at least a portion of the sidewall of the trench 21 can be etched downward only from the top end of the metal layer 30, and the depth of the downward etching can be set according to the related requirements of the semiconductor device, and the depth can be set by controlling the etching time.
In some embodiments, the partially removing the sacrificial layer 40 and leaving the remaining sacrificial layer 40 at least partially within the trench 21 in step 104 includes:
and removing the sacrificial layer by adopting a dry etching process until the part of the sacrificial layer 40, which is positioned on the top surface of the primary body of the semiconductor device, is completely removed, and remaining sacrificial layer 40, which is at least partially positioned in the groove 21, is remained.
Illustratively, the dry etching has higher precision and can make the etched surface smoother than the wet etching, and therefore, the dry etching can make the surface of the remaining sacrificial layer 40 smoother after the dry etching.
In some embodiments, the removing the sacrificial layer by using a dry etching process includes:
reactive Ion Etching (RIE) is performed until the sacrificial layer 40 on the top surface of the semiconductor device primary body is completely removed and the remaining sacrificial layer 40 within the trench 21 is partially left such that the top surface of the remaining sacrificial layer 40 is lower than the top surface of the semiconductor device primary body.
Illustratively, reactive ion etching combines both physical and chemical roles. By selecting the appropriate gas composition, the desired etch selectivity and rate can be achieved. Therefore, the reactive ion etching is adopted, so that certain etching precision is achieved, the heights of the top surfaces of the residual sacrificial layers are more consistent, and certain etching efficiency is achieved.
In some embodiments, after the above dry etching, only part of the remaining sacrificial layer in the trench remains, even if the top surface of the remaining sacrificial layer 40 is lower than the top surface of the semiconductor device, i.e. does not protrude from the trench 21, which is beneficial for providing a reference in height for etching the metal layer 30 on the sidewall of the trench 21 in step 105. Of course, in other embodiments, the top surface of the remaining sacrificial layer 40 after dry etching may be higher than the top surface of the semiconductor device.
In the step 105, as shown in fig. 5, the portion of the metal layer 30 on the top surface of the semiconductor device primary body is completely removed, which can be implemented by using the top surface of the semiconductor device primary body as an etching stop layer. The part of the metal layer 30 covering the inner sidewall of the trench 21 is partially remained, and the etching time can be controlled by using the height of the remaining sacrificial layer as the upper reference height of the metal layer 30 as described above. For example, in other related arts, the solution of etching the metal layer 30 using photoresist as a mask has the following disadvantages: the etching time is short, the metal layer 30 is likely to protrude from the trench 21, the etching time is long, the photoresist is stripped off more, and the metal layer 30 may be etched inward from the sidewall of the metal layer 30, so that the sidewall of the metal layer 30 has no good and stable morphology. In either case, it is apparent that the bridge pier structure of the air bridge is unstable. The preparation method of the semiconductor device does not have the problem of photoresist peeling, and the side wall of the residual metal layer 30 after etching has good and stable appearance, so that the pier structure of the air bridge is more stable, and the performance stability of the semiconductor device is improved.
In some embodiments, the partially removing the metal layer 30 in step 105, and only remaining the remaining metal layer 30 on the partial inner sidewall and bottom surface of the trench 21 includes:
and etching the metal layer 30 by a wet etching process until the part of the metal layer 30 on the top surface of the semiconductor device primary body is completely removed, only remaining metal layers on partial inner side walls and the bottom surface of the groove are remained, and the top surface of the remaining metal layer 30 is lower than the top surface of the remaining sacrificial layer 40.
The wet etching has good etching selectivity, namely only one material can be etched, other materials adjacent to the material can be used as an etching stop layer or a mask layer for etching the material, and the etching efficiency is high. In this embodiment, the metal layer 30 is etched by a wet etching process, the etching selectivity of the material of the metal layer to the material of the sacrificial layer is relatively high, the remaining sacrificial layer 40 can be well used as a mask layer for etching the metal layer 30, the etching selectivity of the material of the metal layer to the material of at least the top layer of the semiconductor device primary body is high, and the top layer of the semiconductor device primary body can be used as an etching stop layer for etching the metal layer 30. Therefore, the side wall of the residual metal layer 30 after wet etching can have good and stable morphology, and the stability of the performance of the semiconductor device is effectively ensured. In some embodiments, the material of the top layer of the semiconductor device primary body may be silicon dioxide, i.e. the material of the top layer of the semiconductor device primary body is the same as the material of the sacrificial layer 40, so that the etching selectivity of the material of the metal layer 30 to the material of the top layer of the semiconductor device primary body is the same and higher, and the material can be used as an etching stop layer for etching the metal layer 30. In some embodiments, the top layer of the semiconductor device precursor is formed with a conductive layer 22 (described in detail below) prior to forming the metal layer 30, such that the material of the conductive layer 22 can be selected such that the etch selectivity of the material of the metal layer 30 to the material of the conductive layer 22 is greater than or equal to 100. For example, the material of the conductive layer 22 may be titanium, while the material of the metal layer 30 may be aluminum, as described above, and the etching selectivity of aluminum to titanium is greater than 1000. Therefore, the etching selectivity of the material of the metal layer 30 to the material of the conductive layer 22 is higher, and the conductive layer 22 can be used as an etching stop layer for etching the metal layer 30.
In the step 106, the remaining sacrificial layer 40 is not a structural layer finally required by the semiconductor device, but a process layer in the process of etching the metal layer 30, so that the sacrificial layer is removed, and the removed semiconductor device is as shown in fig. 6.
In some embodiments, the removing 106 the remaining sacrificial layer 40 includes:
the remaining sacrificial layer 40 is removed by dry etching.
Illustratively, the dry etching has higher precision and can make the etched surface smoother than the wet etching, so that the surface of the metal layer 30 remaining in the trench 21 can be protected from damage by the dry etching.
In some embodiments, the removing the remaining sacrificial layer comprises:
and performing chemical etching by using hydrogen fluoride as etching gas to remove the residual sacrificial layer.
The hydrogen fluoride is used as etching gas to perform chemical etching, and the method has the advantages of high etching efficiency and low cost. It can be understood that other dry etching methods can be used under the condition of low requirement on etching efficiency.
In some embodiments, before forming the metal layer 30, the method for manufacturing a semiconductor device further includes: forming a conductive layer 22 on the semiconductor device primary body, wherein the conductive layer 22 covers the top surface of the semiconductor device primary body and covers the inner side wall and the bottom surface of the groove 21 but does not fill the groove 21;
the forming of the metal layer 30 includes:
the metal layer 30 is formed on the conductive layer 22, and the metal layer 30 covers a part of the conductive layer 22 and does not fill the trench 21.
Illustratively, the conductive layer 22 is the conductive layer 22 electrically connected to the bridge deck photosensitive element as described above, and the conductive layer 22 is prepared prior to the metal layer 30 during the normal air bridge preparation process. That is, the conductive layer 22 is formed in the trench 21 to cover the inner sidewall and the bottom surface of the trench 21 but not to fill the trench 21, and then the metal layer 30 is formed in the trench 21 to cover the conductive layer 22 and not to fill the trench 21. The conductive layer 22 is electrically connected to the photosensitive element of the bridge deck to receive a signal of the photosensitive element. The metal layer 30 serves to support the conductive layer 22 and the entire pier, and serves to stabilize the air bridge.
In some embodiments, the material of the conductive layer 22 may include titanium, but may also be other conductive materials that are conductive and mechanically good.
The embodiment of the application also provides a semiconductor device, and the semiconductor device is prepared by the preparation method of the semiconductor device.
In some embodiments, as shown in fig. 6, the semiconductor device includes:
a semiconductor device primary body including a trench 21 extending from a top surface to an inside;
a conductive layer 22, wherein the conductive layer 22 covers the top surface of the semiconductor device primary body and covers the inner side wall and the bottom surface of the groove 21 but does not fill the groove 21;
the metal layer 30 is formed in the groove 21, and the metal layer 30 covers a part of the conductive layer in the groove 21 and does not fill the groove 21; the top surface of the metal layer 30 is lower than the top surface of the semiconductor device primary body in the longitudinal direction.
In some embodiments, the semiconductor device primary body comprises:
a semiconductor device substrate 20;
and a wiring layer 23 formed on the semiconductor device substrate 20. At least a part of the wiring layer 23 is exposed via the trench 21; the exposed portion of the wiring layer 23 is conductively connected to the conductive layer 22 located in the trench 21.
Illustratively, the wiring layer 23 may be provided with a plurality of corresponding trenches 21. The plurality of wiring layers 23 corresponding to different trenches may be conductively connected two by the conductive layer 22. The wiring layer 23 may be located at a lower end of a bridge abutment of the air bridge, corresponding to the structure of the air bridge. One end of the conductive layer 22 is connected to the wiring layer 23 at the lower end of one pier, and the other end is connected to the wiring layer 23 at the lower end of the other pier via the bridge surface of the air bridge.
A first dielectric layer 24 formed on the semiconductor device substrate 20 to cover a top surface of the semiconductor device substrate 20;
an isolation layer 25 formed on the first dielectric layer 24 and divided into a plurality of parts not communicated with each other by the trench 21;
a second dielectric layer 26, wherein the second dielectric layer 26 covers the top surface of the isolation layer 25 and the inner wall of the trench 21 and does not fill the trench 21; the second dielectric layer 26 is located between the conductive layer 22 and the inner wall of the trench 21.
The embodiment of the semiconductor device provided by the application and the embodiment of the preparation method of the semiconductor device belong to the same concept; the technical features described in the embodiments may be arbitrarily combined without conflict. It should be further noted that, in the semiconductor device provided in the embodiments of the present application, various technical feature combinations of the semiconductor device can already solve the technical problems to be solved by the present application; therefore, the semiconductor device provided by the embodiment of the present application may not be limited by the manufacturing method of the semiconductor device provided by the embodiment of the present application, and any semiconductor device that can be manufactured by the manufacturing method of the semiconductor device structure provided by the embodiment of the present application is within the protection scope of the present application.
It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations encompassed by the claims. Various modifications and changes may also be made on the above embodiments without departing from the scope of the present disclosure. Likewise, various features of the above embodiments may be arbitrarily combined to form additional embodiments of the present invention that may not be explicitly described. Therefore, the above examples only represent some embodiments of the present invention, and do not limit the scope of the present invention.

Claims (10)

1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor device primary body, wherein the semiconductor device primary body comprises a groove extending from the top surface to the inner part;
forming a metal layer covering the top surface of the semiconductor device primary body and covering the inner side walls and the bottom surface of the groove but not filling the groove;
forming a sacrificial layer, wherein the sacrificial layer covers the metal layer, and the thickness of the sacrificial layer at the groove is larger than that of the top surface of the semiconductor device primary body; the etching selection ratio of the material of the metal layer to the material of the sacrificial layer is greater than or equal to 100;
partially removing the sacrificial layer, and remaining at least part of the sacrificial layer in the groove;
partially removing the metal layer, and only remaining the residual metal layer on partial inner side wall and bottom surface of the groove;
and removing the residual sacrificial layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the sacrifice layer includes:
forming a sacrificial material layer covering the metal layer, wherein the sacrificial material layer fills the part of the groove which is not filled by the metal layer;
and performing a planarization process on the sacrificial material layer to form the sacrificial layer, wherein the thickness of the sacrificial layer at the groove is larger than that at the top surface of the semiconductor device primary body.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of partially removing the sacrificial layer and/or the step of removing the remaining sacrificial layer is performed by a dry etching process.
4. The method of claim 1, wherein the sacrificial layer is partially removed by a reactive ion etching process, leaving at least a portion of the remaining sacrificial layer in the trench.
5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the metal layer is formed by a sputtering coating process.
6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the metal layer is partially removed by a wet etching process.
7. The method for manufacturing a semiconductor device according to claim 3, wherein the removing the remaining sacrificial layer comprises:
and performing chemical etching by using hydrogen fluoride as etching gas to remove the residual sacrificial layer.
8. The method for manufacturing a semiconductor device according to claim 1, wherein before the forming of the metal layer, the method further comprises:
and forming a conductive layer which covers the top surface of the primary body of the semiconductor device, covers the inner side wall and the bottom surface of the groove and does not fill the groove.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the forming a metal layer includes:
the metal layer covers a part of the conductive layer in the groove and does not fill the groove.
10. A semiconductor device produced by the method for producing a semiconductor device according to any one of claims 1 to 9.
CN202211191562.XA 2022-09-28 2022-09-28 Preparation method of semiconductor device and semiconductor device Pending CN115579416A (en)

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