CN103311173A - Method for preparing double-depth shallow trench isolation groove - Google Patents
Method for preparing double-depth shallow trench isolation groove Download PDFInfo
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- CN103311173A CN103311173A CN2013101956253A CN201310195625A CN103311173A CN 103311173 A CN103311173 A CN 103311173A CN 2013101956253 A CN2013101956253 A CN 2013101956253A CN 201310195625 A CN201310195625 A CN 201310195625A CN 103311173 A CN103311173 A CN 103311173A
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Abstract
The invention provides a method for preparing a double-depth shallow trench isolation groove. The double-depth shallow trench isolation groove is prepared through two completely independent preparation technologies such as a logic region depth shallow trench isolation groove technology and a pixel region shallow shallow trench isolation groove technology, so that the double slope appearance of the depth shallow trench isolation groove is avoided; through the excellent filling ability characteristic of an ODL (organic dielectric layer), the filling and planarization of the depth shallow trench isolation groove can be finished; and furthermore, through the shallow depth characteristic of the shallow shallow trench isolation groove, a second photoresist layer and an organic isolation layer are used as mask layers etched by pixel region shallow shallow trench isolation (STI), so that the problem of forming stepped height difference in two STI etchings of the hard mask layers can be avoided.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of preparation method of dual-depth shallow trench isolation channels.
Background technology
Shallow trench isolation (STI) technique is one of critical process of cmos device formation, along with constantly dwindling of device size, photoresist thickness is restricted, and not too large the reducing of the etching depth of STI, make photoresist can not satisfy thickness requirement as STI etch mask layer, so behind the 130nm technology node, extensively adopt silicon nitride hard mask technique to carry out the STI etching in the prior art.Along with further dwindling of dimension of picture, after the 45nm technology node, single ArF photoresist all can not meet the demands on thickness and figure Transfer Quality as mask layer, so non-setting carbon+silicon nitride mask etching or three layers of compound photoresist mask etching are widely used in the STI etching technics, its technological principle is generally non-setting carbon or the organic insulator (ODL:organic dielectric layer) that as mask layer pictorial pattern is delivered to photoresist lower floor, then utilize non-setting carbon or organic insulator as mask layer, silicon nitride to lower floor carries out etching, carry out the figure transmission, subsequently non-setting carbon or organic insulator are carried out the ashing removal, finish at last the STI etching of substrate silicon with silicon nitride as mask layer.
Simultaneously, based on advanced technologies platform (＜65nm) CIS(CMOS Image Sensor, cmos image sensor) product is the focus that current chip is made the field, owing to having simultaneously photosensitive area (Pixel) and logic area (Logic) on every side on the CIS chip, make its manufacturing process and traditional logic or memory chip that a lot of differences be arranged, on the STI critical process, because the STI depth requirements of photosensitive area and logic area is different, so CIS product of the prior art generally adopts Dual STI(dual-depth shallow trench isolation channels) technique forms the sti structure of two kinds of degree of depth, and the key step of this technique comprises:
Please refer to Figure 1A, the substrate 100 that comprises photosensitive area I and logic area II is provided, on substrate 100, form successively the photoresist 103 of silicon nitride 101, amorphous carbon layer or organic insulator 102a, bottom anti-reflection layer (BARC) 102b and patterning;
Please refer to Figure 1B, with photoresist, amorphous carbon layer or organic insulator, bottom anti-reflection layer (BARC) and the silicon nitride of patterning as mask, substrate is carried out the light engraving erosion, form shallow trench isolation channels 104a, 104b at photosensitive area I and logic area II, remove remaining photoresist and bottom anti-reflection layer (BARC);
Please refer to Fig. 1 C, on photosensitive area I, again cover photoresist 103a;
Please refer to Fig. 1 D, at logic area II, as hard mask, carry out the deep etching of the shallow trench isolation channels of logic area II with remaining silicon nitride, to form the dual-depth sti structure.
There is following shortcoming in above-mentioned process:
1) the twice etching all utilizes silicon nitride as the hard mask of etching, make that there is step-like difference in height (shown in the dotted line circle 1 among Fig. 1 D) in the remaining silicon nitride of logic area II behind the deep etching, so that the difference in height of the silicon oxide layer of the sti structure of photosensitive area I and logic area II and active area (AA) is inconsistent behind the subsequent CMP, thereby cause some electrical problem and potential risks, so that component failure;
2) when the deep etching of the shallow trench isolation channels that carries out logic area II, because the mask different in kind of twice etching, the situation of polymer deposition is different during etching, easily produce pattern (the double slope of diclinic degree at the shallow trench isolation channels sidewall of logic area II, shown in the dotted line circle 2 among Fig. 1 D)), thus electrically exerting an influence to logic area II.
Thereby need a kind of preparation method of new dual-depth shallow trench isolation channels, to avoid defects.
Summary of the invention
The object of the present invention is to provide a kind of preparation method of dual-depth shallow trench isolation channels, when forming dual-depth shallow trench isolation channels structure, can avoid the diclinic degree pattern of shallow trench isolation channels sidewall of the prior art and the problem of the step-like difference in height of hard mask layer.
For addressing the above problem, the present invention proposes a kind of preparation method of dual-depth shallow trench isolation channels, may further comprise the steps:
The substrate that comprises photosensitive area and logic area is provided, forms successively hard mask layer, amorphous carbon layer, the first photoresist layer on described substrate, described the first photoresist layer is formed with dark STI pattern at described logic area;
Take described the first photoresist layer, amorphous carbon layer and hard mask layer as mask, carry out the dark STI etching of logic area, form depth channel isolation groove at described logic area;
Form organic insulator at the device surface that forms depth channel isolation groove, described organic insulator fills up described depth channel isolation groove and covers described device surface;
Form the second photoresist layer at described organic insulator, described the second photoresist layer is formed with shallow STI pattern at described photosensitive area;
Take described the second photoresist layer and organic insulator as mask, carry out the shallow STI etching of photosensitive area, form simple channel isolation groove at described photosensitive area;
Remove the organic insulator of filling in the described depth channel isolation groove, again expose described depth channel isolation groove.
Further, described substrate comprises substrate and suprabasil dielectric layer.
Further, described hard mask layer is silicon nitride layer, silicon oxynitride layer, silica-silicon nitride stack layer or silica-silicon-nitride and silicon oxide stack layer.
Further, the step that forms the first photoresist layer comprises:
Be coated with photoresist layer at described amorphous carbon layer;
Form the position of depth channel isolation groove in described logic area definition, and the described photoresist layer of exposure imaging;
Described position in definition forms opening, to form dark STI pattern at described logic area.
Further, the step that forms the second photoresist layer comprises:
Be coated with photoresist layer at the device surface of filling organic insulator;
Form the position of simple channel isolation groove in described photosensitive area definition, and the described photoresist layer of exposure imaging;
Described position in definition forms opening, to form shallow STI pattern at described photosensitive area.
Further, the preparation method of described dual-depth shallow trench isolation channels also comprises:
Before forming the first photoresist layer, described amorphous carbon layer also forms the insulation anti-reflecting layer;
Before forming the second photoresist layer, described organic insulator also forms spin-on-glass layer.
Further, the dark STI etching of described logic area and the shallow STI etching of photosensitive area include hard mask layer etching, substrate S TI etching and STI bottom fillet etching.
Further, described insulation anti-reflecting layer comprises the medium anti-reflecting layer of bottom anti-reflection layer and upper surface thereof.
Further, adopt cineration technics to remove respectively the first photoresist layer, the second photoresist layer and organic insulator.
Further, remove the organic insulator of filling in the described depth channel isolation groove after, wet-cleaned device surface.
Compared with prior art, the preparation method of dual-depth shallow trench isolation channels provided by the invention, by logic area depth channel isolation groove technique and these twice of the simple channel isolation groove of photosensitive area technique fully independently preparation technology finish the preparation of dual-depth shallow trench isolation channels, thereby avoided the diclinic degree pattern of depth channel isolation groove; Utilize simultaneously the good characteristics of ODL fillibility, finish filling and planarization to depth channel isolation groove; Further utilize the more shallow characteristics of the degree of depth of simple channel isolation groove, directly with the second photoresist layer and the organic insulator mask layer as the shallow STI etching of photosensitive area, thereby avoided hard mask layer in twice STI etching, to form the problem of step-like difference in height.
Description of drawings
Figure 1A to 1D is the device profile structural representation in preparation method's flow process of traditional dual-depth shallow trench isolation channels;
Fig. 2 is preparation method's flow chart of the dual-depth shallow trench isolation channels of the specific embodiment of the invention;
Fig. 3 A to 3E is the device profile structural representation in preparation method's flow process of dual-depth shallow trench isolation channels shown in Figure 2.
Embodiment
Core concept of the present invention is the preparation method who discloses a kind of dual-depth shallow trench isolation channels, by changing process sequence and lithographic method, form dual-depth shallow trench isolation channels structure, namely by logic area depth channel isolation groove technique and these twice of the simple channel isolation groove of photosensitive area technique fully independently preparation technology finish the preparation of dual-depth shallow trench isolation channels, avoid simultaneously diclinic degree (double slope) pattern of shallow trench isolation channels sidewall and hard mask layer in the step-like difference in height of the groove etched middle formation of twice shallow trench isolation, reduce technology difficulty, enlarge process window.
For purpose of the present invention, feature are become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is further described, yet the present invention can realize with different forms, should not think just to be confined to described embodiment.
Please refer to Fig. 2, the present invention proposes a kind of preparation method of dual-depth shallow trench isolation channels, may further comprise the steps:
S1 provides the substrate that comprises photosensitive area and logic area, forms successively hard mask layer, amorphous carbon layer, the first photoresist layer on described substrate, and described the first photoresist layer is formed with dark STI pattern at described logic area;
S2 take described the first photoresist layer, amorphous carbon layer and hard mask layer as mask, carries out the dark STI etching of logic area, forms depth channel isolation groove at described logic area;
S3 forms organic insulator at the device surface that forms depth channel isolation groove, and described organic insulator fills up described depth channel isolation groove and covers described device surface;
S4 forms the second photoresist layer at described organic insulator, and described the second photoresist layer is formed with shallow STI pattern at described photosensitive area;
S5 take described the second photoresist layer and organic insulator as mask, carries out the shallow STI etching of photosensitive area, forms simple channel isolation groove at described photosensitive area;
S6 removes the organic insulator of filling in the described depth channel isolation groove, again exposes described depth channel isolation groove.
Describe the preparation method of dual-depth shallow trench isolation channels of the present invention in detail below in conjunction with specific embodiments and the drawings 3A to 3E.
Please refer to Fig. 3 A, in step S1, the substrate that provides comprises substrate 300 and suprabasil dielectric layer 301, and described dielectric layer 301 can be silica.This substrate is divided into photosensitive area I and logic area II; On described dielectric layer 301, form successively the first photoresist layer 305 of hard mask layer 302, amorphous carbon (APF) layer 303, insulation anti-reflecting layer 304 and patterning, described the first photoresist layer 305 is formed with dark STI pattern (opening among Fig. 3 A) at described logic area II, and namely the first photoresist layer 305 covers all the other insulation anti-reflecting layer 304 surfaces except opening part.In the present embodiment, hard mask layer 302 can be to be silicon nitride layer, silicon oxynitride layer, silica-silicon nitride stack layer or silica-silicon-nitride and silicon oxide stack layer, and thickness is
The thickness of amorphous carbon layer 303 is
Insulation anti-reflecting layer 304 comprises the medium anti-reflecting layer (DARC) of bottom anti-reflection layer (BARC) and upper surface thereof, and wherein the thickness of bottom anti-reflection layer is
The thickness of medium anti-reflecting layer is
The first photoresist layer is
The ArFi layer.Wherein hard mask layer 302 can form by chemical vapour deposition technique, and insulation anti-reflecting layer 304 can form by spin coating or chemical vapour deposition technique, and the concrete steps that the first photoresist layer 305 forms comprise:
Be coated with photoresist layer at described insulation anti-reflecting layer 304;
Form the position of depth channel isolation groove in described logic area II definition, and the described photoresist layer of exposure imaging;
Described position in definition forms opening, to form dark STI pattern at described logic area II.
Please refer to Fig. 3 A and 3B, in step S2, with the first photoresist layer 305, insulation anti-reflecting layer 304, amorphous carbon layer 303 and hard mask layer 302 are mask, the key step of carrying out the dark STI etching of logic area II comprises: the etching of insulation anti-reflecting layer 304, amorphous carbon layer 303 etchings, hard mask layer 302 etchings, remaining amorphous carbon layer 303, insulation anti-reflecting layer 304 and the first photoresist layer 305 are removed, the STI etching of substrate 300 logic area II, STI bottom fillet etching etc., form at last the dark STI(depth of logic area channel isolation groove) 306 structures, the degree of depth of dark STI306 probably is
Form that the loss thickness of silicon nitride hard mask 302 is about after the dark STI306 structure
In the present embodiment, after finishing, hard mask layer 302 etchings can directly adopt cineration technics to remove remaining the first photoresist layer 305, insulation anti-reflecting layer 304 and amorphous carbon layer 303, hard mask layer 302 is as the mask layer of photosensitive area I and logic area II, finish the STI etching of follow-up substrate logic region II, STI bottom fillet etching etc., the pattern of the first photoresist layer 305 is continued to transfer on the substrate 300, thereby the substantial principle of step S2 be first with the first photoresist layer 305 as mask layer anti-reflecting layer 304 etchings that insulate, make the pictorial pattern of the first photoresist layer 305 be delivered to insulation anti-reflecting layer 304, then take the first photoresist layer 305 and insulation anti-reflecting layer 304 as mask layer, to amorphous carbon layer 303 etchings, make pictorial pattern be delivered to 303 layers of amorphous carbon layers; Then take the first photoresist layer 305, insulation anti-reflecting layer 304 and amorphous carbon layer 303 as mask, to hard mask layer 302 etchings, make pictorial pattern be delivered to hard mask layer 302, then remove the first photoresist layer 305, insulation anti-reflecting layer 304 and amorphous carbon layer 303, carry out the etching of substrate 300 as mask layer with hard mask layer 302, the design transfer of the first photoresist layer 305 forms dark STI306 structure in substrate 305 the most at last.
Please continue with reference to figure 3A and 3B, in other embodiments of the invention, the removal technique of remaining the first photoresist layer 305, insulation anti-reflecting layer 304 and amorphous carbon layer 303 also can be finished after described logic area II forms dark STI306, and namely the employing cineration technics is removed the first photoresist layer 305, insulation anti-reflecting layer 304 and amorphous carbon layer 303 after STI bottom fillet etching is finished.
Please refer to Fig. 3 C, in step S3, because the filling capacity of organic insulation medium is higher, thereby the coating organic insulator of the device after can finishing step S2 (ODL) 307 forms dark STI to filling up, then device is carried out top flattening, obtain the well behaved device flat surfaces of trench fill.The thickness of the organic insulator 307 of photosensitive area I is
The 3C with reference to figure be please continue, in step S4, spin-on-glass layer (SOG) 308 and the second photoresist layer 309 on organic insulator 307 surfaces, are coated with successively.Wherein, spin-on-glass layer 308 thickness are
The second photoresist layer 309 is
The ArFi layer, the second photoresist layer 309, spin-on-glass layer 308 and organic insulator 307 are equivalent to three layers of compound photoresist layer, have preferably thickness and figure Transfer Quality.The forming process of the second photoresist layer 309 forming processes and the first photoresist layer is similar, specifically comprises:
Be coated with photoresist layer in described spin-on-glass layer 308;
Form the simple channel isolation groove of shallow STI(in described photosensitive area I definition) the position, and the described photoresist layer of exposure imaging;
Described position in definition forms opening, to form shallow STI pattern at described photosensitive area I.
Please refer to Fig. 3 D, in step S5, utilize the shallow STI degree of depth more shallow, can be the process characteristic of mask layer with photoresist, directly with organic insulator 307, spin-on-glass layer 308 and the second photoresist layer 309 are mask, carry out the shallow STI etching of photosensitive area, the etching key step has spin-on-glass layer 308 etchings, organic insulator 307 etchings, hard mask layer 302 etchings, the second photoresist layer 309 and spin-on-glass layer 308 are removed, the STI etching of substrate photosensitive area I, STI bottom fillet etchings etc. form the simple trench isolations of shallow STI() 310 structures, the degree of depth of shallow STI310 probably is
Organic insulator 307 keeps in the shallow STI etching process of photosensitive area all the time, thereby does not cause the quadratic loss of hard mask layer 302, thereby can be in the step-like difference in height of logic area II and photosensitive area I formation hard mask layer 302.In the present embodiment, after finishing, hard mask layer 302 etchings can directly adopt cineration technics to remove remaining the second photoresist layer 309 and spin-on-glass layer 308, hard mask layer 302 is as the mask layer of photosensitive area I and logic area II, finish the STI etching of follow-up substrate 300 photosensitive area I, STI bottom fillet etching etc., the pattern of the second photoresist layer 309 is continued to transfer on the substrate 300, thereby the substantial principle of step S5 is to carry out spin-on-glass layer 308 etchings with the second photoresist layer 310 as mask layer first, make the pictorial pattern of the second photoresist layer 309 be delivered to spin-on-glass layer 308, then take the second photoresist layer 309 and spin-on-glass layer 308 as mask layer, to organic insulator 307 etchings, make pictorial pattern be delivered to organic insulator 307; Then take the second photoresist layer 309, spin-on-glass layer 308 and organic insulator 307 as mask, to hard mask layer 302 etchings, make pictorial pattern be delivered to hard mask layer 302, then remove remaining the second photoresist layer 309 and spin-on-glass layer 308, carry out the etching of substrate 300 as mask layer with organic insulator 307 and hard mask layer 302, the design transfer of the second photoresist layer 309 forms shallow STI310 structure in substrate 305 the most at last.
In other embodiments of the invention, the removal technique of remaining the second photoresist layer, spin-on-glass layer also can be finished in step S6, and namely the employing cineration technics is removed the second photoresist layer, spin-on-glass layer after STI bottom fillet etching is finished.
Please refer to Fig. 3 E, in step S6, the device behind the step S5 is carried out the organic insulator ashing remove, again to expose described depth channel isolation groove, then chemical cleaning is removed etch residue and other etch product, finally obtains the dual-depth sti structure.
Need to prove, the preparation method of dual-depth shallow trench isolation channels provided by the invention is not limited to the above-mentioned order that forms shallow STI behind the dark STI that forms first, also can be transformed to and form first the order that forms dark STI behind the shallow STI, the technical process after the exchange specifically comprises:
The substrate that comprises photosensitive area and logic area is provided, forms successively hard mask layer, organic insulator, spin-on-glass layer, the first photoresist layer on described substrate, described the first photoresist layer is formed with shallow STI pattern at described photosensitive area;
Take described the first photoresist layer, spin-on-glass layer, organic insulator as mask, carry out the shallow STI etching of photosensitive area, form simple channel isolation groove at described photosensitive area;
Form organic insulator at the device surface that forms simple channel isolation groove, described organic insulator fills up described simple channel isolation groove and covers described device surface;
Form amorphous carbon layer, insulation anti-reflecting layer, the second photoresist layer at described organic insulator, described the second photoresist layer is formed with dark STI pattern at described logic area;
Take described the second photoresist layer, insulation anti-reflecting layer, amorphous carbon layer and silicon nitride layer as mask, carry out the dark STI etching of logic area, form depth channel isolation groove at described logic area;
Remove the organic insulator of filling in the described simple channel isolation groove, again expose described simple channel isolation groove.
In sum, the preparation method of dual-depth shallow trench isolation channels provided by the invention, by logic area depth channel isolation groove technique and these twice of the simple channel isolation groove of photosensitive area technique fully independently preparation technology finish the preparation of dual-depth shallow trench isolation channels, thereby avoided the diclinic degree pattern of depth channel isolation groove; Utilize simultaneously the good characteristics of ODL fillibility, finish filling and planarization to depth channel isolation groove; Further utilize the more shallow characteristics of the degree of depth of simple channel isolation groove, directly with the second photoresist layer and the organic insulator mask layer as the shallow STI etching of photosensitive area, thereby avoided hard mask layer in twice STI etching, to form the problem of step-like difference in height.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the preparation method of a dual-depth shallow trench isolation channels is characterized in that, comprising:
The substrate that comprises photosensitive area and logic area is provided, forms successively hard mask layer, amorphous carbon layer, the first photoresist layer on described substrate, described the first photoresist layer is formed with dark STI pattern at described logic area;
Take described the first photoresist layer, amorphous carbon layer and hard mask layer as mask, carry out the dark STI etching of logic area, form depth channel isolation groove at described logic area;
Form organic insulator at the device surface that forms depth channel isolation groove, described organic insulator fills up described depth channel isolation groove and covers described device surface;
Form the second photoresist layer at described organic insulator, described the second photoresist layer is formed with shallow STI pattern at described photosensitive area;
Take described the second photoresist layer and organic insulator as mask, carry out the shallow STI etching of photosensitive area, form simple channel isolation groove at described photosensitive area;
Remove the organic insulator of filling in the described depth channel isolation groove, again expose described depth channel isolation groove.
2. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 1 is characterized in that, described substrate comprises substrate and suprabasil dielectric layer.
3. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 1 is characterized in that, described hard mask layer is silicon nitride layer, silicon oxynitride layer, silica-silicon nitride stack layer or silica-silicon-nitride and silicon oxide stack layer.
4. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 1 is characterized in that, the step that forms the first photoresist layer comprises:
Be coated with photoresist layer at described amorphous carbon layer;
Form the position of depth channel isolation groove in described logic area definition, and the described photoresist layer of exposure imaging;
Described position in definition forms opening, to form dark STI pattern at described logic area.
5. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 1 is characterized in that, the step that forms the second photoresist layer comprises:
Be coated with photoresist layer at the device surface of filling organic insulator;
Form the position of simple channel isolation groove in described photosensitive area definition, and the described photoresist layer of exposure imaging;
Described position in definition forms opening, to form shallow STI pattern at described photosensitive area.
6. such as the preparation method of each described dual-depth shallow trench isolation channels in the claim 1 to 5, it is characterized in that, also comprise:
Before forming the first photoresist layer, described amorphous carbon layer also forms the insulation anti-reflecting layer;
Before forming the second photoresist layer, described organic insulator also forms spin-on-glass layer.
7. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 6 is characterized in that, the dark STI etching of described logic area and the shallow STI etching of photosensitive area include hard mask layer etching, substrate S TI etching and STI bottom fillet etching.
8. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 6 is characterized in that, described insulation anti-reflecting layer comprises the medium anti-reflecting layer of bottom anti-reflection layer and upper surface thereof.
9. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 1 is characterized in that, adopts cineration technics to remove respectively the first photoresist layer, the second photoresist layer and organic insulator.
10. the preparation method of dual-depth shallow trench isolation channels as claimed in claim 1 is characterized in that, remove the organic insulator of filling in the described depth channel isolation groove after, wet-cleaned device surface.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390441A (en) * | 2015-11-26 | 2016-03-09 | 上海集成电路研发中心有限公司 | Method for improving morphology of through holes in low-dielectric-constant dielectric layer |
| CN107993922A (en) * | 2017-11-30 | 2018-05-04 | 上海华力微电子有限公司 | Avoiding control gate from forming middle etching and do over again causes the method for amorphous carbon film peeling |
| CN110148580A (en) * | 2019-05-15 | 2019-08-20 | 上海集成电路研发中心有限公司 | A kind of dual depth shallow trench isolation groove and preparation method thereof |
| CN115775766A (en) * | 2023-02-02 | 2023-03-10 | 合肥晶合集成电路股份有限公司 | Method for forming shallow trench isolation structure and method for forming semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060011631A (en) * | 2004-07-30 | 2006-02-03 | 주식회사 하이닉스반도체 | Method for isolation in semiconductor device by using amorphous carbon layer |
| CN101645421A (en) * | 2008-08-04 | 2010-02-10 | 中芯国际集成电路制造(上海)有限公司 | CMOS image sensor and forming method thereof and method for forming semiconductor device |
| CN101783313A (en) * | 2009-01-19 | 2010-07-21 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove, manufacturing method thereof and shallow groove isolation structure |
| CN102005404A (en) * | 2009-08-28 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | Double-depth shallow groove isolation manufacturing method |
-
2013
- 2013-05-23 CN CN2013101956253A patent/CN103311173A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060011631A (en) * | 2004-07-30 | 2006-02-03 | 주식회사 하이닉스반도체 | Method for isolation in semiconductor device by using amorphous carbon layer |
| CN101645421A (en) * | 2008-08-04 | 2010-02-10 | 中芯国际集成电路制造(上海)有限公司 | CMOS image sensor and forming method thereof and method for forming semiconductor device |
| CN101783313A (en) * | 2009-01-19 | 2010-07-21 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove, manufacturing method thereof and shallow groove isolation structure |
| CN102005404A (en) * | 2009-08-28 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | Double-depth shallow groove isolation manufacturing method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390441A (en) * | 2015-11-26 | 2016-03-09 | 上海集成电路研发中心有限公司 | Method for improving morphology of through holes in low-dielectric-constant dielectric layer |
| CN107993922A (en) * | 2017-11-30 | 2018-05-04 | 上海华力微电子有限公司 | Avoiding control gate from forming middle etching and do over again causes the method for amorphous carbon film peeling |
| CN107993922B (en) * | 2017-11-30 | 2020-12-01 | 上海华力微电子有限公司 | Method for preventing amorphous carbon film from peeling off caused by etching rework in control gate formation |
| CN110148580A (en) * | 2019-05-15 | 2019-08-20 | 上海集成电路研发中心有限公司 | A kind of dual depth shallow trench isolation groove and preparation method thereof |
| CN115775766A (en) * | 2023-02-02 | 2023-03-10 | 合肥晶合集成电路股份有限公司 | Method for forming shallow trench isolation structure and method for forming semiconductor device |
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