CN115576000A - Charge readout circuit and method, and multi-channel charge readout device and method - Google Patents

Abstract

The present disclosure provides a charge readout circuit, a method, a multi-channel charge readout device and a method, wherein the charge readout circuit comprises: a current integration circuit for inputting an input voltage in which the charge amount of the charge varies; the first charge reading branch circuit is used for reversely charging the current integrating circuit when the input voltage is greater than a first reference voltage so as to balance the charge quantity in the current integrating circuit and generate a first pulse signal; the second charge reading branch circuit is used for reversely charging the current integrating circuit when the input voltage is greater than a second reference voltage so as to balance the charge quantity in the current integrating circuit and generate a second pulse signal; the second reference voltage is greater than the first reference voltage, and the reverse charging voltage of the second charge reading branch is greater than the reverse charging voltage of the first charge reading branch. The charge readout circuit can realize the readout of high-precision, wide-range and multi-channel weak charges, and improves the conversion range of dynamic charges under the condition of switches with the same performance.

Description

Charge readout circuit and method, and multi-channel charge readout device and method

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a charge readout circuit and method, and a multi-channel charge readout device and method.

Background

The beam position and profile are key factors affecting the particle therapy device. In order to irradiate the tumor with accurate dose and ensure the safety and reliability of the medical device, the beam position and the profile need to be monitored in real time, and important control data are provided for doctors and physical personnel. In a treatment system, a multi-channel weak charge signal is output through a strip ionization chamber of a treatment terminal, and real-time monitoring of beam position and profile can be realized through a multi-channel charge reading device. The output charge signal range of the strip ionization chamber for beam monitoring and measurement is large, the number of channels is large, the span of the output charge range can reach six orders of magnitude (pA-muA), and the number of channels can reach 100-400. For multichannel weak charge signals, a series of front-end processing, conversion and amplification are required to read the signals. When processing such weak signals, attention needs to be paid to noise and interference, and particularly to the problem of processing speed. Therefore, the development of a multichannel wide-range weak electric charge readout device is a problem to be solved urgently.

The prior art generally adopts a current-voltage real-time conversion method to read the input charge quantity. The method has the advantage that real-time information of the beam can be obtained, but the method has the disadvantages of large data volume, high requirements on subsequent data real-time transmission and processing and high manufacturing cost. Secondly, the interference of the environmental noise to the circuit is large by adopting the method, and the accuracy of beam monitoring is influenced. Thirdly, in order to ensure the conversion accuracy of the input charge, the prior art generally adopts a method of alternately operating the two integrators, which easily causes that the two integrators cannot be well connected when being switched with each other. Finally, the prior art generally adopts a multiplexing circuit to realize the serial output of multi-channel signals, and the scheme increases the signal conversion and reading time and reduces the signal processing efficiency while reducing the complexity of a data acquisition and processing system.

Disclosure of Invention

In view of the above problems, the present invention provides a charge readout circuit and method and a multi-channel charge readout device and method to solve the above problems.

One aspect of the present disclosure provides a charge readout circuit, including: a current integration circuit for receiving an input charge and outputting an input voltage varying with a charge amount of the input charge; the input end of the first charge reading branch circuit is connected with the output end of the current integrating circuit, the first output end of the first charge reading branch circuit is connected with the input end of the current integrating circuit, the second output end of the first charge reading branch circuit is connected with an external reading circuit, the first output end is used for charging the current integrating circuit in an inverted phase when the input voltage is greater than a first reference voltage so as to balance the charge amount in the current integrating circuit, and the second output end is used for outputting a first pulse signal generated when the input voltage is greater than the first reference voltage; the input end of the second charge reading branch circuit is connected with the output end of the current integrating circuit, the third output end of the second charge reading branch circuit is connected with the input end of the current integrating circuit, the fourth output end of the second charge reading branch circuit is connected with an external reading circuit, the third output end is used for charging the current integrating circuit in an inverted phase when the input voltage is greater than a second reference voltage so as to balance the charge amount in the current integrating circuit, and the fourth output end is used for outputting a second pulse signal generated when the input voltage is greater than the second reference voltage; the second reference voltage is greater than the first reference voltage, and the reverse charging voltage generated by the second charge reading branch is greater than the reverse charging voltage generated by the first charge reading branch.

Optionally, the current integration circuit comprises: an operational amplifier and a variable integrating capacitor; the inverting input end of the operational amplifier is connected with the input end of the charge, and the positive input end of the operational amplifier is grounded; one end of the variable integrating capacitor is connected with the inverting input end of the operational amplifier, and the other end of the variable integrating capacitor is connected with the output end of the operational amplifier.

Optionally, the first charge reading branch comprises: the first comparator, the first timer, the first switch and the first constant current source; the positive input ends of the first comparators are connected with the output end of the current integrating circuit, and the negative input ends of the first comparators are connected with the first reference voltage and used for outputting a first trigger signal to the first timer when the input voltage is greater than the first reference voltage; the output end of the first timer is connected with a first switch for controlling the on-off of the first constant current source and is used for generating a first pulse signal for closing the first switch based on the first trigger signal; the first constant current source is used for reversely charging the current integration circuit when the first switch is closed; the second charge reading branch includes: the second comparator, the second timer, the second switch and the second constant current source; the positive input ends of the second comparators are connected with the output end of the current integrating circuit, and the negative input ends of the second comparators are connected with the second reference voltage and used for outputting a second trigger signal to the second timer when the input voltage is greater than the second reference voltage; the output end of the second timer is connected with a second switch for controlling the on-off of the second constant current source and is used for generating a second pulse signal for closing the second switch based on the second trigger signal; the second constant current source is used for reversely charging the current integration circuit when the second switch is closed.

Optionally, the first timer and the second timer include a high level state, a low level state, and an initial state, where the high level state is a working state in which a high level is output to generate the first pulse signal, the fixed time duration is Ht, the low level state is a working state in which a low level is output after the high level state is ended, the fixed time duration is Lt, ht ≧ Lt > 0, and the initial state is a static state after the low level state is ended.

A second aspect of the present disclosure provides a multi-channel charge readout device comprising a plurality of charge readout circuits according to any one of the first aspects and a data acquisition card; each charge readout circuit is respectively connected with one charge channel and used for reading input charges transmitted by the charge channels; the data acquisition card is connected with the output end of each charge readout circuit and is used for acquiring pulse signals generated by the charge readout circuits reading the input charges.

Optionally, the apparatus further comprises: and the digital integrated circuit is connected with the first timer and the second timer in the charge readout circuit and is used for setting the pulse width of the first timer and the pulse width of the second timer for generating pulse signals.

Optionally, the apparatus further comprises: a first photoelectric conversion module and a second photoelectric conversion module; the input end of the first photoelectric conversion module is connected with the output end of each charge readout circuit, and the output end of the first photoelectric conversion module is connected with an optical fiber and used for converting pulse signals generated by reading input charges by the charge readout circuits into optical signals and transmitting the optical signals to the second photoelectric conversion module through the optical fiber; the input end of the second photoelectric conversion module is connected with the optical fiber, and the output end of the second photoelectric conversion module is connected with the digital integrated circuit and used for converting the optical signal into an electric signal and outputting the electric signal to the digital integrated circuit.

A third aspect of the present disclosure provides a charge readout method including: receiving the electric charge output by the charge channel, and generating an input voltage corresponding to the electric charge; comparing an input voltage with a first reference voltage and a second reference voltage, generating an inverted charging voltage to charge the current integration circuit in an inverted manner when the input voltage is greater than the first reference voltage or the second reference voltage to balance the amount of charge in the current integration circuit, and outputting a first pulse signal when the input voltage is greater than the first reference voltage and outputting a second pulse signal when the input voltage is greater than the second reference voltage; wherein the second reference voltage is greater than the first reference voltage, and the inverse charging voltage generated when the input voltage is greater than the second reference voltage is greater than the inverse charging voltage generated when the input voltage is greater than the first reference voltage.

A fourth aspect of the present disclosure provides a multi-channel charge readout method, including: receiving charges output by a plurality of charge channels, and respectively generating input voltages corresponding to the charges output by the charge channels; comparing the input voltage of each charge channel with a first reference voltage and a second reference voltage respectively, generating an inverted charging voltage to charge the current integrating circuit in an inverted manner when the input voltage is greater than the first reference voltage or the second reference voltage so as to balance the charge amount in the current integrating circuit, outputting a first pulse signal when the input voltage is greater than the first reference voltage, and outputting a second pulse signal when the input voltage is greater than the second reference voltage; converting the first pulse signal and the second pulse signal generated by each charge channel into optical signals, and transmitting the optical signals through optical fibers; converting the optical signal into an electrical signal and collecting the electrical signal, wherein the electrical signal represents the quantity of electric charge output by a corresponding charge channel; wherein the second reference voltage is greater than the first reference voltage, and the inverse charging voltage generated when the input voltage is greater than the second reference voltage is greater than the inverse charging voltage generated when the input voltage is greater than the first reference voltage.

The above-mentioned at least one technical scheme who adopts in this disclosed embodiment can reach following beneficial effect:

1. the method adopts a charge balance principle, automatically switches the constant current source balanced with the input charge quantity according to the input charge quantity, better solves the contradiction between the measuring range and the resolution ratio, and realizes the reading of weak charges with high precision, large measuring range and multiple channels. Under the condition of the same performance of switch, the conversion range of dynamic charge is greatly improved.

2. The charge frequency conversion technology is adopted to convert the input charge signal into the frequency signal, so that the subsequent data acquisition amount is greatly reduced, and the requirements on later-stage data transmission and processing are reduced.

3. The single channel works by adopting a single integrator, input signals are not switched, the problem of charge information loss in the dynamic charge reading process can be avoided in the full-range, and the conversion precision is higher.

4. In the process of transmitting the output frequency signal, a method of photoelectric conversion is adopted twice, the pulse signal is converted into the optical signal and then transmitted, the interference of environmental noise on the signal transmission is avoided to the maximum extent, and the accuracy of beam monitoring is ensured.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1 schematically illustrates a schematic diagram of a charge readout circuit provided by an embodiment of the present disclosure;

fig. 2 schematically illustrates an operation state flow diagram of a timer provided by an embodiment of the present disclosure;

fig. 3 schematically illustrates a basic operation waveform diagram of a charge readout circuit provided by an embodiment of the present disclosure;

FIG. 4 schematically illustrates a current integration circuit provided by an embodiment of the present disclosure;

fig. 5 schematically illustrates a comparison circuit provided by an embodiment of the present disclosure;

fig. 6 schematically illustrates a constant current source circuit provided by an embodiment of the present disclosure;

fig. 7 schematically illustrates a schematic diagram of a charge readout device provided by an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.

The charge readout circuit provided by the embodiment of the disclosure comprises a current integration circuit, a first charge reading branch circuit and a second charge reading branch circuit.

The current integration circuit is used for receiving input charges and outputting input voltages which are changed along with the charge quantity of the input charges.

The input end of the first charge reading branch circuit is connected with the output end of the current integrating circuit, the first output end of the first charge reading branch circuit is connected with the input end of the current integrating circuit, the second output end of the first charge reading branch circuit is connected with the external reading circuit, the first output end of the first charge reading branch circuit is used for charging the current integrating circuit in an inverted mode when the input voltage is larger than the first reference voltage so as to balance the charge amount in the current integrating circuit, and the second output end of the first charge reading branch circuit is used for outputting a first pulse signal generated when the input voltage is larger than the first reference voltage.

The input end of the second charge reading branch circuit is connected with the output end of the current integrating circuit, the third output end of the second charge reading branch circuit is connected with the input end of the current integrating circuit, the fourth output end of the second charge reading branch circuit is connected with the external reading circuit, the third output end is used for charging the current integrating circuit in a reversed phase mode when the input voltage is larger than the second reference voltage so as to balance the charge amount in the current integrating circuit, and the fourth output end is used for outputting a second pulse signal generated when the input voltage is larger than the second reference voltage.

The second reference voltage is greater than the first reference voltage, and the reverse charging voltage generated by the second charge reading branch circuit is greater than the reverse charging voltage generated by the first charge reading branch circuit.

Based on the charge readout circuit provided by the embodiment of the disclosure, the charge balance principle is adopted, and the constant current source balanced with the input charge amount is automatically switched according to the magnitude of the input charge amount, so that the contradiction between the measuring range and the resolution ratio is better solved. Wherein, when the charge amount is large, the total charge amount Q is inputted _in And the number of pulses V _P11 And V _P12 The following relationship exists between: qin = K ₁ *V _P11 +K ₂ *V _P12 Wherein K1 and K2 are precision factors, K2 is more than or equal to K1, and the values of K1 and K2 determine the resolution of the whole circuit.

Fig. 1 schematically illustrates a schematic diagram of a charge readout circuit provided by an embodiment of the present disclosure.

As shown in fig. 1, in a charge readout circuit provided in an embodiment of the present disclosure, a current integration circuit includes an operational amplifier U1 and a variable integration capacitor C1; the inverting input end of the operational amplifier U1 is connected with the input end of the charge, and the positive input end of the operational amplifier U1 is grounded; one end of the variable integrating capacitor C1 is connected with the inverting input end of the operational amplifier U1, and the other end of the variable integrating capacitor C1 is connected with the output end of the operational amplifier U1. The output end of the operational amplifier U1 is also connected with the positive input ends of the comparators A1 and A2.

The first charge reading branch includes: a first comparator A1, a first timer T1, a first switch KB1, and a first constant current source I1; the positive input ends of the first comparators A1 are connected with the output end of the current integrating circuit, the negative input ends of the first comparators A1 are connected with a first reference voltage Vref1, and the first comparators A1 are used for outputting a first trigger signal U to the first timer T1 when the input voltage V1 is greater than the first reference voltage Vref1 _c11 (ii) a The output end of the first timer T1 is connected with a first switch KB1 for controlling the on-off of the first constant current source I1 and is used for triggering a signal U based on a first trigger signal _c11 Generates a first pulse signal V for closing the first switch KB1 _P11 (ii) a The first constant current source I1 is used to charge the current integration circuit in anti-phase when the first switch is closed KB 1.

The second charge reading branch includes: a second comparator a12, a second timer T2, a second switch KB2, and a second constant current source I2; the positive input ends of the second comparators A12 are connected with the output end of the current integrating circuit, the negative input ends are connected with a second reference voltage Vref2, and the second comparators A12 are used for outputting a second trigger signal U to the second timer T2 when the input voltage V1 is greater than the second reference voltage Vref2 _c12 (ii) a The output end of the second timer T2 is connected with a second switch KB2 for controlling the on-off of the second constant current source I2 and is used for controlling the on-off of the second constant current source I2 based on a second trigger signal U _c12 Generates a second pulse signal V for closing the second switch KB2 _P12 (ii) a The second constant current source I2 is used to charge the current integration circuit in reverse phase when the second switch KB2 is closed.

Fig. 2 schematically illustrates an operation state flow diagram of a timer provided by an embodiment of the present disclosure.

As shown in fig. 2, the first timer T1 and the second timer T2 provided by the embodiment of the present disclosure include a high level state, a low level state, and an initial state, where the high level state is a working state outputting a high level to generate a first pulse signal, the fixed time duration is Ht, after the low level state is the high level state, the working state outputting a low level, the fixed time duration is Lt, ht ≧ Lt > 0, and the initial state is a static state after the low level state is ended.

Taking the timer T1 as an example, the initial state is Timinit, and the timer outputs a signal V _P11 At the rising edge of the system clock, detecting an output signal Uc11 of the comparator, if Uc11=1, the state of the timer is switched from an initial state Timinit to a high level state Timon, otherwise the timer is always in the initial state, the timer starts and outputs high level in the high level state Timon, and the state is switched from the high level state Timon to a low level state Timoff when the timing time reaches a set value Ht of the high level. In low level state, the timer outputs a signal V _P11 Is 0, and is set in a state where the timing reaches a time setting value Lt of a low levelThe low state Timoff is converted to the initial state Timinit. The low level state Timoff can ensure that the output interval of the pulse is ensured when the input electric charge is accumulated more, and the timer is not always in the high level state.

The output signal of the timer is used for controlling the switch of the constant current source on one hand, and is directly input into the photoelectric conversion module as the output signal of the multi-channel charge reading device on the other hand. The high-level output set time Ht and the low-level output set time Lt of the timer can be controlled and set by the FPGA or the CPLD, generally, ht is more than or equal to Lt and is more than 0, and the maximum pulse output frequency is Fmax = 1/(Ht + Lt).

Fig. 3 schematically illustrates a basic operation waveform diagram of a charge readout circuit provided by an embodiment of the present disclosure.

As shown in fig. 3, when the input charge Qin is negative and small, the voltage V1 of the output of the operational amplifier is positive, and the output voltage V1 continuously increases as the amount of input charge increases, when the output voltage V1 of the operational amplifier increases to the threshold voltage Vref1 of the comparator A1, the output of the comparator A1 transitions from a low level to a high level. After receiving the high level signal, the input end of the timer T1 starts to operate and enters a high level state, and the output end VP11 of the timer T1 becomes a high level, so that the analog switch KB1 is closed, and the constant current source I1 and one end of the integrating capacitor C1 are connected to reversely charge the integrating capacitor. With the continuous charging, the output end V1 of the operational amplifier gradually decreases, after a fixed high level holding time Ht, the output end VP11 of the timer T1 changes to a low level, and the output end of the timer T1 outputs a pulse V _P11 And the constant current source I1 is disconnected from the input end of the integrating capacitor. The output voltage V1 of the operational amplifier is again increased stepwise as the charge is continuously input, and the above-described process is repeated when the output voltage V1 is increased to the threshold voltage Vref1 of the comparator A1. In this case only timer T1 has a pulse signal output. As the input charge Qin continues to increase, the output terminal V1 of the operational amplifier increases rapidly, and even if the analog switch KB1 performs the switching operation at the fastest frequency, the constant current source I1 cannot charge and discharge the entire charge on the integrating capacitor in reverse phase. This results in an operational amplifier outputThe output voltage V1 rises all the time, exceeding the threshold voltage Vref1 of the comparator A1. When the output voltage V1 increases to the threshold voltage Vref2 of the comparator A2, the output of the comparator A2 transitions from the low level to the high level. The input end of the timer T2 starts working after receiving the high level signal and enters a high level state, the output end VP12 of the timer T2 becomes high level, so that the analog switch KB2 is closed, and the constant current source I2 and one end of the integrating capacitor C1 are connected to reversely charge the integrating capacitor. With the continuous charging, the output terminal V1 of the operational amplifier gradually decreases, after a fixed high level holding time Ht, the output terminal VP12 of the timer T2 becomes a low level, the output terminal of the timer T2 outputs a pulse, and the constant current source I2 is disconnected from the input terminal of the integrating capacitor. The output voltage V1 of the operational amplifier is again increased stepwise with the continuous input of the electric charge, and the above-described process is repeated when the output voltage V1 is increased to the threshold voltage Vref2 of the comparator A2. In this case, the timers A1 and A2 each have a pulse signal output.

Therefore, when the input charge amount is small, the comparator A2, the analog switch KB2 and the timer T2 are not triggered to start operating, the timer T2 does not output a pulse signal, and only the timer A1 outputs the pulse signal V _P11 And (6) outputting. Input charge amounts Qin and V _P11 And the whole circuit works in a small range and has higher resolution. The comparator A2, the analog switch KB2, and the timer T2 are triggered to start operating only when the input charge amount is large enough and the analog switch KB1 operates at the maximum frequency and cannot balance out the charge amount of the integrating capacitor C1. The whole circuit is automatically switched to a large range, in which case the total output pulse number should be V _P11 And V _P12 And (4) the sum. Inputting total charge Qin and pulse number V _P11 And V _P12 The following relationship exists between: qin = K1V _P11 +K2*V _P12 K1 and K2 are precision factors, K2 is larger than or equal to K1, the values of K1 and K2 determine the resolution of the whole circuit, and K1 and K2 can be reasonably selected according to the range and the maximum output frequency of the whole circuit.

In this embodiment, the control parameters, such as the precision factors K1 and K2, the high and low level setting values Ht and Lt, the threshold voltages Vref1 and Vref2, and the value of the integrating capacitor C2, can be set according to the actual application requirements of the device, so that the device has more flexibility and universality in use.

Fig. 4, 5 and 6 sequentially and schematically illustrate a current integration circuit schematic diagram, a comparison circuit diagram and a constant current source circuit diagram provided by the embodiment of the disclosure.

As shown in fig. 4, an operational amplifier AD8065ARTZ and an integrating capacitor with an accuracy of ± 0.1pF at 1pF may be used; as shown in fig. 5, a comparator chip TLV3201 and a reference voltage source ADR130BUJZ may be adopted to ensure stability of the threshold voltage; as shown in fig. 6, a precision voltage source ADR130BUJZ and a precision CMOS operational amplifier AD8605ARTZ may be used to ensure the stability of the constant current source.

According to the charge reading circuit provided by the embodiment of the disclosure, a charge balance principle is adopted, and the constant current source balanced with the input charge quantity is automatically switched according to the input charge quantity, so that the contradiction between the measuring range and the resolution ratio is well solved, and the high-precision, large-range and multi-channel weak charge reading is realized. Under the condition of switches with the same performance, the conversion range of dynamic charges is greatly improved; the charge frequency conversion technology is adopted to convert the input charge signal into the frequency signal, so that the subsequent data acquisition amount is greatly reduced, and the requirements on later data transmission and processing are reduced; the single channel works by adopting a single integrator, input signals are not switched, the problem of charge information loss in the dynamic charge reading process can be avoided in the full-range, and the conversion precision is higher.

The present disclosure also provides a charge readout method including operations S110 to S120.

S110, receiving the electric charge output by the electric charge channel, and generating an input voltage corresponding to the electric charge.

S120, comparing the input voltage V1 with a first reference voltage Vref1 and a second reference voltage Vref2, and generating an inverted charging voltage V when the input voltage V1 is greater than the first reference voltage Vref1 or the second reference voltage Vref2 _p11 Charging the current integration circuit in reverse phase to balance the amount of charge in the current integration circuit, and when the input voltage V1 is greater than the first reference voltage Vref1Outputting a first pulse signal V _p11 When the input voltage is greater than the second reference voltage Vref2, the second pulse signal V is output _p12 。

The second reference voltage Vref2 is greater than the first reference voltage Vref1, and the reverse charging voltage generated when the input voltage V1 is greater than the second reference voltage Vref2 is greater than the reverse charging voltage generated when the input voltage V1 is greater than the first reference voltage Vref1.

According to the method, the range of charge reading is expanded from Vref1 to Vref2, and when the charge level is in different states, pulse signals with different pulse frequencies are generated, so that the contradiction between the range and the resolution is better solved. Under the condition of the same performance of switch, the conversion range of dynamic charge is greatly improved.

It should be noted that, this method has the same technical features as the charge readout circuit shown in fig. 1, and therefore, the same technical effects can be achieved, and are not described herein again.

Fig. 7 schematically illustrates a schematic diagram of a charge readout device provided by an embodiment of the present disclosure.

As shown in fig. 7, a charge readout device provided by the embodiment of the present disclosure includes a multi-channel charge readout circuit and a data acquisition card. Each charge readout circuit is connected with one charge channel respectively and used for reading input charges transmitted by the charge channels. The data acquisition card is connected with the output end of each charge readout circuit and is used for acquiring pulse signals generated by the charge readout circuits reading input charges. And the digital integrated circuit is connected with the first timer and the second timer in the charge readout circuit and is used for setting the pulse width of the pulse signals generated by the first timer and the second timer.

In this embodiment, each channel includes an integration circuit, two constant current sources, two comparators, and two timers. The multichannel charge readout device consists of N single channels like this, wherein the timers of the channels are implemented by an FPGA or a CPLD. The operation of the charge readout circuit of this embodiment is the same as that of the charge readout circuit shown in fig. 1, and is not described herein again.

In this embodiment, the apparatus may include a first photoelectric conversion module a and a second photoelectric conversion module B; the input end of the first photoelectric conversion module 1 is connected with the output end of each charge readout circuit, and the output end of the first photoelectric conversion module is connected with an optical fiber and used for converting a pulse signal generated by reading input charges by the charge readout circuits into an optical signal and transmitting the optical signal to the second photoelectric conversion module B through the optical fiber; the input end of the second photoelectric conversion module B is connected with the optical fiber, and the output end of the second photoelectric conversion module B is connected with the digital integrated circuit and used for converting the optical signal into an electric signal and outputting the electric signal to the digital integrated circuit. In the process of transmitting the output frequency signal, a method of photoelectric conversion twice is adopted to convert the pulse signal into the optical signal and then transmit the optical signal, so that the electromagnetic interference of environmental noise on the signal transmission is avoided to the maximum extent, and the accuracy of beam monitoring is ensured.

In this embodiment, the digital integrated circuit is connected to the first timer and the second timer in each charge readout circuit, and is configured to set the pulse widths of the pulse signals generated by the first timer and the second timer.

The present disclosure also provides a multi-channel charge readout method, including S210 to S240.

S210, receiving the charges outputted from the plurality of charge channels, and respectively generating input voltages corresponding to the charges outputted from the charge channels.

S220, comparing the input voltage of each charge channel with a first reference voltage and a second reference voltage respectively, generating an inverted charging voltage to invert and charge the current integrating circuit when the input voltage is greater than the first reference voltage or the second reference voltage so as to balance the charge amount in the current integrating circuit, outputting a first pulse signal when the input voltage is greater than the first reference voltage, and outputting a second pulse signal when the input voltage is greater than the second reference voltage.

And S230, converting the first pulse signal and the second pulse signal generated by each charge channel into optical signals and transmitting the optical signals through optical fibers.

And S240, converting the optical signal into an electric signal and collecting the electric signal, wherein the electric signal represents the electric charge quantity output by the corresponding charge channel.

The second reference voltage is greater than the first reference voltage, and the reverse charging voltage generated when the input voltage is greater than the second reference voltage is greater than the reverse charging voltage generated when the input voltage is greater than the first reference voltage.

The method can realize multichannel charge reading, adopts a charge balance principle, automatically switches a constant current source balanced with the input charge quantity according to the input charge quantity, better solves the contradiction between the measuring range and the resolution ratio, and realizes the reading of weak charges with high precision, large measuring range and multiple channels; the charge frequency conversion technology is adopted to convert the input charge signal into the frequency signal, so that the subsequent data acquisition amount is greatly reduced, and the requirements on later data transmission and processing are reduced; the single channel works by adopting a single integrator, the input signals are not switched, the problem of charge information loss in the dynamic charge reading process can not occur in the full-range, and the conversion precision is higher; in the transmission process of the output frequency signal, a method of two-time photoelectric conversion is adopted to convert the pulse signal into the optical signal and then transmit the optical signal, so that the interference of environmental noise on the signal transmission is avoided to the maximum extent, and the accuracy of beam monitoring is ensured.

It will be appreciated by a person skilled in the art that various combinations or/and combinations of features recited in the various embodiments of the disclosure and/or in the claims may be made, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teaching of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.

While the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined not only by the appended claims, but also by equivalents thereof.

Claims (9)

1. A charge readout circuit, comprising:

a current integration circuit for receiving an input charge and outputting an input voltage varying with a charge amount of the input charge;

the input end of the first charge reading branch circuit is connected with the output end of the current integrating circuit, the first output end of the first charge reading branch circuit is connected with the input end of the current integrating circuit, the second output end of the first charge reading branch circuit is connected with an external reading circuit, the first output end is used for charging the current integrating circuit in an inverted phase when the input voltage is greater than a first reference voltage so as to balance the charge amount in the current integrating circuit, and the second output end is used for outputting a first pulse signal generated when the input voltage is greater than the first reference voltage;

the input end of the second charge reading branch circuit is connected with the output end of the current integrating circuit, the third output end of the second charge reading branch circuit is connected with the input end of the current integrating circuit, the fourth output end of the second charge reading branch circuit is connected with an external reading circuit, the third output end is used for charging the current integrating circuit in an inverted phase when the input voltage is greater than a second reference voltage so as to balance the charge amount in the current integrating circuit, and the fourth output end is used for outputting a second pulse signal generated when the input voltage is greater than the second reference voltage;

the second reference voltage is greater than the first reference voltage, and the reverse charging voltage generated by the second charge reading branch is greater than the reverse charging voltage generated by the first charge reading branch.

2. The charge readout circuit of claim 1, wherein the current integration circuit comprises:

an operational amplifier and a variable integrating capacitor;

the inverting input end of the operational amplifier is connected with the input end of the charge, and the positive input end of the operational amplifier is grounded;

one end of the variable integrating capacitor is connected with the inverting input end of the operational amplifier, and the other end of the variable integrating capacitor is connected with the output end of the operational amplifier.

3. The charge readout circuit of claim 1,

the first charge reading branch includes:

the first comparator, the first timer, the first switch and the first constant current source;

the positive input ends of the first comparators are connected with the output end of the current integrating circuit, the negative input ends of the first comparators are connected with the first reference voltage, and the first comparators are used for outputting a first trigger signal to the first timer when the input voltage is greater than the first reference voltage;

the output end of the first timer is connected with a first switch for controlling the on-off of the first constant current source and is used for generating a first pulse signal for closing the first switch based on the first trigger signal;

the first constant current source is used for reversely charging the current integration circuit when the first switch is closed;

the second charge reading branch includes:

the second comparator, the second timer, the second switch and the second constant current source;

the positive input ends of the second comparators are connected with the output end of the current integrating circuit, and the negative input ends of the second comparators are connected with the second reference voltage and used for outputting a second trigger signal to the second timer when the input voltage is greater than the second reference voltage;

the output end of the second timer is connected with a second switch for controlling the on-off of the second constant current source and is used for generating a second pulse signal for closing the second switch based on the second trigger signal;

the second constant current source is used for reversely charging the current integration circuit when the second switch is closed.

4. The charge readout circuit of claim 3, wherein the first timer and the second timer comprise a high state, a low state and an initial state, wherein the high state is an operating state outputting a high level to generate the first pulse signal, the fixed time duration is Ht, the low state is an operating state outputting a low level after the high state is ended, the fixed time duration is Lt, ht ≧ Lt > 0, and the initial state is a static state after the low state is ended.

5. A multi-channel charge readout device comprising a plurality of charge readout circuits according to any one of claims 1 to 4 and a data acquisition card;

each charge readout circuit is respectively connected with one charge channel and used for reading input charges transmitted by the charge channels;

the data acquisition card is connected with the output end of each charge readout circuit and is used for acquiring pulse signals generated by the charge readout circuits reading the input charges.

6. The apparatus of claim 5, further comprising:

and the digital integrated circuit is connected with the first timer and the second timer in the charge readout circuit and is used for setting the pulse width of the first timer and the second timer for generating pulse signals.

7. The apparatus of claim 5, further comprising:

a first photoelectric conversion module and a second photoelectric conversion module;

the input end of the first photoelectric conversion module is connected with the output end of each charge readout circuit, and the output end of the first photoelectric conversion module is connected with an optical fiber and used for converting pulse signals generated by reading input charges by the charge readout circuits into optical signals and transmitting the optical signals to the second photoelectric conversion module through the optical fiber;

the input end of the second photoelectric conversion module is connected with the optical fiber, and the output end of the second photoelectric conversion module is connected with the digital integrated circuit and is used for converting the optical signal into an electric signal and outputting the electric signal to the digital integrated circuit.

8. A charge readout method, comprising:

receiving the electric charge output by the charge channel, and generating an input voltage corresponding to the electric charge;

comparing an input voltage with a first reference voltage and a second reference voltage, generating an inverted charging voltage to charge the current integration circuit in an inverted manner when the input voltage is greater than the first reference voltage or the second reference voltage to balance the amount of charge in the current integration circuit, and outputting a first pulse signal when the input voltage is greater than the first reference voltage and outputting a second pulse signal when the input voltage is greater than the second reference voltage;

wherein the second reference voltage is greater than the first reference voltage, and an inverted charging voltage generated when the input voltage is greater than the second reference voltage is greater than an inverted charging voltage generated when the input voltage is greater than the first reference voltage.

9. A multi-channel charge readout method, comprising:

receiving the electric charges output by a plurality of electric charge channels, and respectively generating input voltages corresponding to the electric charges output by the electric charge channels;

comparing the input voltage of each charge channel with a first reference voltage and a second reference voltage respectively, generating an inverted charging voltage to charge the current integrating circuit in an inverted manner when the input voltage is greater than the first reference voltage or the second reference voltage so as to balance the charge amount in the current integrating circuit, outputting a first pulse signal when the input voltage is greater than the first reference voltage, and outputting a second pulse signal when the input voltage is greater than the second reference voltage;

converting the first pulse signal and the second pulse signal generated by each charge channel into optical signals, and transmitting the optical signals through optical fibers;

converting the optical signal into an electrical signal and collecting the electrical signal, wherein the electrical signal represents the amount of electric charge output by a corresponding charge channel;

wherein the second reference voltage is greater than the first reference voltage, and an inverted charging voltage generated when the input voltage is greater than the second reference voltage is greater than an inverted charging voltage generated when the input voltage is greater than the first reference voltage.

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