CN115568115A - Method for processing offset circuit board - Google Patents
Method for processing offset circuit board Download PDFInfo
- Publication number
- CN115568115A CN115568115A CN202211182811.9A CN202211182811A CN115568115A CN 115568115 A CN115568115 A CN 115568115A CN 202211182811 A CN202211182811 A CN 202211182811A CN 115568115 A CN115568115 A CN 115568115A
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- circuit board
- marking
- offset
- layer
- deviation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/166—Alignment or registration; Control of registration
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention discloses an offset circuit board processing method, relates to the technical field of circuit board production, and aims to solve the problem that the existing method can only judge whether a layer is offset or not but cannot specifically obtain the layer offset when detecting the layer offset. The circuit board layer deviation judging method comprises the steps of manufacturing a marking ring, pressing, detecting layer deviation and classifying, and can specifically obtain the layer deviation data of the circuit board, so that the circuit board can be conveniently subjected to subsequent processing according to the data; the circuit board full-page structure comprises a plurality of uniformly arranged single board areas and cutting areas arranged at the periphery of the single board areas, and the marking rings are positioned in the cutting areas, so that the structure has the beneficial effects of improving the detection efficiency and avoiding damaging the single boards of the circuit board; the method for processing the offset circuit board comprises full offset circuit board processing and half offset circuit board processing, and the method carries out classification processing on the circuit board according to the full-page layer offset data of the circuit board, so that the waste of the circuit board is reduced, and the cost is saved.
Description
Technical Field
The invention relates to the technical field of circuit board production, in particular to a method for processing an offset circuit board.
Background
The PCB is one of the very important elements for electrical connection of electronic components in electronic equipment, for the PCB with a multilayer structure manufactured by a laminating process, detecting the alignment consistency (whether interlayer offset is generated) of two adjacent layers of plates is a key element index for judging the quality of a finished product of the PCB, and if the offset between the layers reaches a certain degree, the drilling deviation hole is caused to generate short circuit, so that the circuit board is scrapped.
The invention with the publication number CN105072830B discloses a layer deviation detection method. The invention sets two rings (compensation copper rings and copper rings) in each layer deviation detection area of a circuit copper layer to form a pre-stacking structure and two groups of different rings on a multilayer board, wherein the copper ring without tension coefficient compensation is used for detecting whether each board layer in the pre-stacking structure deviates after fusing/riveting, and the compensation copper ring with tension coefficient compensation is used for detecting whether each board layer in the multilayer board deviates after laminating, thereby being suitable for detecting the layer deviation condition of the pre-stacking structure of core boards with different tension coefficients, providing quality guarantee for subsequent production, providing basis for solving layer deviation abnormity, and further improving production efficiency and quality.
However, when the device detects layer deviation, only whether the layer deviation exists can be judged, but the layer deviation cannot be specifically obtained, so that it is difficult to judge which circuit boards have the layer deviation in a qualified range and which circuit boards have the layer deviation in an unqualified range, and scrapping treatment is needed.
Disclosure of Invention
In view of the disadvantages of the prior art, a first object of the present invention is to provide a method for determining layer offset of a circuit board, which can specifically obtain layer offset data of the circuit board, and facilitate subsequent processing of the circuit board according to the data.
The first object of the invention is achieved by the following technical solutions:
a circuit board layer deviation judging method comprises the following steps:
s1: manufacturing a marking ring: etching a marking ring at the same position on the surface of each main substrate, wherein the diameters of the marking rings are the same;
s2: and (3) laminating: aligning the main substrates, and laminating the plurality of layers to form an inner layer plate;
s3: layer deviation detection: placing the inner-layer plate into an x-ray detector to detect layer deviation, and if the marking rings on the main substrates of all the layers are completely overlapped, no layer deviation exists; if the marking circular rings on the main substrates of all the layers are staggered, the layers are deviated;
the x-ray detector scans the positions of three marking rings which are farthest away in the marking rings on each layer of main substrate, and makes alignment rings which surround the three marking rings which are farthest away and are tangent to the marking rings respectively;
the system obtains the diameter of the alignment ring, and calculates the difference value of the diameters of the alignment ring and the marking ring, wherein the difference value is the real-time layer offset;
the system sets up the standard layer deflection in advance, compare real-time layer deflection with standard and measure the layer deflection, if the real-time layer deflection is less than or equal to the standard layer deflection, there is no deflection; if the real-time layer offset is greater than the standard layer offset, the deviation exists;
s4: and (4) classification: and (4) separately outputting the circuit boards without deviation and with deviation.
By adopting the technical scheme, the x-ray detector can detect the position of the contour line of each marking ring, but cannot reflect the position of the center of each marking ring, so that the marking rings are set to be the same in diameter and are positioned at the same position on each layer of main substrates, if the main substrates of all layers are completely aligned, the contour lines of the marking rings are completely aligned, if the main substrates are misaligned, the outer contours of the marking rings are misaligned, and when the main substrates of all layers are misaligned, the farthest marking rings can reflect the misalignment degree to the greatest extent, the alignment rings made by the tangent circles of the three marking rings farthest are scanned to obtain the diameter of the alignment rings, and the difference between the diameter of the alignment rings and the diameter of the marking rings represents the discrete degree of the marking rings on each layer of main substrates, so that the misalignment degree between the main substrates of each layer is expressed. The method specifically quantizes the layer deviation degree of the circuit board, and is convenient for personnel to accurately judge and classify, so that corresponding subsequent processing is convenient for different layer deviation quantities.
The present invention in a preferred example may be further configured to: the standard layer offset value is smaller than the diameter of the marking ring.
By adopting the technical scheme, the marking rings of all layers on the qualified circuit board are in a concentric or crossed state, and when the marking rings are in a complete separated state, the fault deviation can be directly judged to be unqualified, so that the detection efficiency is further improved, and the detection result can be conveniently verified.
The present invention in a preferred example may be further configured to: a plurality of marking rings are arranged on one circuit board and are respectively close to the edges of different sides of the circuit board.
Through adopting above-mentioned technical scheme, when the circuit board takes place the skew, the position that the circuit board offset is the biggest must be close to circuit board edge, set up a plurality of mark rings, and make it all be located circuit board edge, the layer partial degree of circuit board can furthest be reflected, and the skew trend of circuit board is obtained through the offset change of the mark ring of different positions, be convenient for make corresponding adjustment to lamination equipment, and simultaneously, can accurately classify the circuit board according to the offset of difference, be convenient for follow-up processing to the circuit board.
The invention in a preferred example may be further configured to: and S3, marking the circuit board with deviation, and marking real-time layer deviation values at the marked circular rings at different positions.
By adopting the technical scheme, the real-time layer deviation value at the mark position is used for personnel to analyze and classify the circuit board with deviation, and the control of the layer deviation of the circuit board is facilitated.
The second objective of the present invention is to provide a circuit board full page structure, which has the beneficial effects of improving the detection efficiency and avoiding damaging the single board of the circuit board.
The second objective of the invention is achieved by the following technical solutions:
a circuit board full page structure, comprising a plurality of single board areas which are uniformly arranged and cutting areas which are arranged at the periphery of the single board areas, wherein the full page of the circuit board is a rectangular board, and the marking ring of any one of claims 1 to 4 is positioned in the cutting areas.
By adopting the technical scheme, in the alignment, press fit and other processing steps among all layers of the circuit board, the edge of the whole circuit board is easy to have dislocation, abrasion and the like to the maximum extent, so that the circuit board at the position is difficult to directly utilize, the position is set as a cutting area and is used as the margin of the whole circuit board, and the circuit board is finally removed after the whole circuit board is completely processed, thereby ensuring the quality of the processed circuit board; the outline of the marking ring is formed by etching, the thickness of a copper layer on the surface of the main substrate can be influenced, the marking ring is arranged in the cutting area, and the marking ring and the cutting area are removed together after the marking ring is processed, so that the quality of the circuit board single board which is finally separated is further ensured.
The invention in a preferred example may be further configured to: the marking circular rings are arranged at four positions, and the four positions of the marking circular rings are respectively positioned at four corners of the circuit board.
By adopting the technical scheme, the area of the cutting area at the four corners of the whole circuit board is the largest, the single board area can be avoided to the greatest extent to etch and process the marking ring, damage to the single board area is avoided, meanwhile, when dislocation occurs between the main substrates of all layers, the dislocation degree of the four corners of the whole circuit board is the largest, the offset is also the largest, and the detected layer deviation data is more accurate.
The third objective of the present invention is to provide an offset circuit board processing method, which can perform classification processing on circuit boards according to the layer offset data of the entire circuit board, thereby reducing waste of the circuit boards and saving cost.
The third object of the present invention is achieved by the following technical solutions:
a method for processing an offset circuit board comprises processing a full offset circuit board and a half offset circuit board,
the full-bias circuit board is a circuit board with each marking circular ring biased, and the full-bias circuit board is processed to be scrapped in a full version mode;
the semibiased circuit board is a circuit board with at least one unbiased mark ring in each marking ring, and the semibiased circuit board processing method comprises the following steps:
and (3) wiring: drawing a straight line from the marking ring with the minimum real-time layer offset to the marking ring with the maximum real-time layer offset;
making a vertical line: making a perpendicular line for connecting;
detection and excision: taking the circuit board single board through which the perpendicular line passes for electrical detection, if the circuit is well connected, all circuit board single boards on the side of the marking circular ring through which the perpendicular line passes and on which the perpendicular line is close to the real-time layer with the minimum deviation are qualified, and the rest circuit board single boards are scrapped;
if the circuit is short-circuited, taking 1/4 point of the connecting line close to one side of the marking ring with the minimum real-time layer deviation, making a perpendicular line of the connecting line through the point, taking the circuit board single board through which the perpendicular line passes for electrical detection, if the circuit is well connected, enabling all circuit board single boards through which the perpendicular line passes and one side of the real-time marking ring with the minimum real-time layer deviation of which the perpendicular line is close to the layer deviation to be qualified, and scrapping the rest circuit board single boards;
and repeating the steps until no complete circuit board single board exists between the vertical line and the marking ring with the minimum real-time layer deviation, and scrapping the whole circuit board in full page.
Through adopting above-mentioned technical scheme, the dislocation condition of circuit board generally includes translation off normal and rotation off normal, and the real-time layer offset that each mark ring department detected after the translation off normal is unanimous, when partial off normal, partial no off normal time appear in the different mark rings on the circuit board full-page, explains the off normal of circuit board not only because the translation in the main substrate plane between each layer main substrate causes, still has the dislocation rotation. The qualified part in the whole half-offset circuit board is cut and utilized, so that the scrapped quantity of the circuit board is greatly reduced, the scrapping of the whole circuit board is avoided, the waste of raw materials and procedures is reduced, and the cost is saved.
The present invention in a preferred example may be further configured to: and selecting the circuit board single board on the side with larger real-time layer deviation from the two sides of the connecting line for electrical detection.
By adopting the technical scheme, the offset of the circuit board single plate on the side with larger real-time layer offset is larger than the offset of the circuit board single plate on the other side of the connecting line, if the circuit board single plate on the side is not short-circuited, the perpendicular line and the circuit board single plate on the side of the marking ring with the smallest real-time layer offset are not short-circuited, and the unqualified product is further prevented from flowing in.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the discrete degree of the marking ring on each layer of main substrate is represented by the difference value between the diameter of the alignment ring and the diameter of the marking ring, so that the layer deviation degree of the circuit board is specifically quantized, and personnel can conveniently and accurately judge and classify the circuit board, and accordingly, corresponding subsequent processing can be conveniently performed on different layer deviation quantities;
2. the marking circular ring is arranged in the cutting area, and is removed together with the cutting area after the processing is finished, so that the quality of the circuit board single board after the circuit board single board is finally separated is further ensured;
3. the qualified part in the whole edition of the semi-biased circuit board is distinguished and cut for use, so that the scrapped quantity of the circuit board is greatly reduced, scrapping of the whole circuit board is avoided, waste of raw materials and procedures is reduced, and cost is saved.
Drawings
Fig. 1 is a schematic structural diagram of a circuit board layout according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a layer offset detection process according to an embodiment of the present invention
Fig. 3 is a flowchart of a circuit board layer bias determination method according to an embodiment of the invention.
Fig. 4 is a flowchart of a circuit board half-bias processing method according to a second embodiment of the present invention.
In the figure: 1. a single board area; 2. cutting the area; 3. marking a circular ring; 4. aligning the circular ring.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Example one
Referring to fig. 1, a method for determining a layer bias of a circuit board disclosed by the present invention includes the following steps:
s1: manufacturing a marking ring 3: the marking rings 3 are etched at the same positions on the surfaces of the respective main substrates, and the diameters of the marking rings 3 are the same. Each layer of main substrate comprises two layers of copper-clad plates bonded with each other, the blanking area of each copper-clad plate is calculated according to the size of the multi-circuit board single plate after being spliced, the splicing area of the multi-circuit board single plates is a single plate area 1, cutting areas 2 with equal widths are arranged on the periphery of the single plate area 1, the widths of the cutting areas 2 are 5mm, the overall shape of each copper-clad plate is rectangular, four marking rings 3 are etched on the surface of one side of the main substrate respectively, the marking rings are located in the cutting areas 2 at the four corners of the main substrate, the depth of each marking ring 3 is smaller than the thickness of a copper foil on the surface of the main substrate, and the diameter of each marking ring 3 in the embodiment is 3.5mm.
S2: and (3) pressing a main substrate: the main substrate is aligned and laminated in multiple layers to form the inner layer board.
S3: layer deviation detection: and (5) placing the inner layer plate into an x-ray detector to detect layer deviation. The detection position, the diameter data of the marking circular rings 3 and the standard layer deviation value are set in an x-ray detector in advance, the standard layer deviation value is generally smaller than the diameter of the marking circular rings 3, when the marking circular rings 3 are in a complete separation state, fault deviation can be judged to be unqualified directly, the detection efficiency is further improved, and the detection result can be verified conveniently, the standard layer deviation value in the embodiment is 0.85 mu m, the x-ray detector detects the deviation degree of the marking circular rings 3 at each position and analyzes the deviation degree, and the analysis and data processing processes are as follows:
if the marking circular rings 3 on the main substrates of all layers are completely overlapped, deviation does not exist;
if the marking rings 3 on the main substrate of each layer are staggered, the analysis is continued: the x-ray detector scans the positions of three marking rings 3 which are farthest away in the marking rings 3 on each layer of main substrate, and makes alignment rings 4, wherein the alignment rings 4 surround all the marking rings 3 and are respectively tangent with the three marking rings 3 which are farthest away; the system obtains the diameter of the alignment ring 4, and calculates the difference value between the diameters of the alignment ring 4 and the marking ring 3, and the difference value is the real-time layer offset;
comparing the real-time layer deviation with the standard layer deviation, and if the real-time layer deviation is less than or equal to the standard layer deviation, then no deviation exists; if the real-time layer deviation is greater than the standard layer deviation, the circuit board with deviation exists, the circuit board without deviation is a qualified circuit board, and the circuit board with deviation needs to be further classified, so that the circuit board with deviation is marked in the step, and real-time layer deviation values at the positions of the marking circular rings 3 at different positions are marked;
s4: and (4) classification: and (4) separately outputting the circuit boards without deviation and with deviation.
The implementation principle of the embodiment is as follows: because the x-ray detector can detect the position of the contour line of each marking ring 3, but cannot reflect the position of the center of each marking ring 3, each marking ring 3 is set to have the same diameter and is positioned at the same position on each layer of main substrates, if the main substrates of each layer are completely aligned, the contour lines of each marking ring 3 are completely aligned, if the main substrates are misaligned, the outer contour of the marking ring 3 is misaligned, and when the main substrates are misaligned, the marking ring 3 farthest away can reflect the misalignment degree to the greatest extent, and the alignment ring 4 is made by the tangent circle of the marking ring 3 farthest away; the diameter of the alignment ring 4 is obtained by scanning the outer contour of the alignment ring 4, and the difference value between the diameter of the alignment ring 4 and the diameter of the marking ring 3 represents the discrete degree of the marking rings 3 on each layer of main substrates, so that the dislocation degree between the main substrates of each layer is expressed.
The method specifically quantizes the layer deviation degree of the circuit board, and is convenient for personnel to accurately judge and classify, so that corresponding subsequent processing is convenient for different layer deviation quantities.
Example two
The embodiment of the invention discloses a method for processing an offset circuit board, which comprises full offset circuit board processing and half offset circuit board processing, wherein the full offset circuit board is a circuit board with all marking rings 3 offset, and the full offset circuit board is scrapped for full version;
the semibiased circuit board is a circuit board with at least one unbiased mark ring 3, and the semibiased circuit board processing method comprises the following steps:
(1) And (3) wiring: drawing a straight line from the marking ring 3 with the minimum real-time layer offset to the marking ring 3 with the maximum real-time layer offset;
(2) Making a vertical line: making a perpendicular line of the connection;
(3) Detection and excision: taking the circuit board single board which is passed by the perpendicular line and on the side with larger real-time layer deviation amount in the two sides of the connecting line for electrical detection, if the circuit is well connected, all the circuit board single boards which are passed by the perpendicular line and on the side of the perpendicular line close to the marking ring 3 with the smallest real-time layer deviation amount are qualified, and the rest circuit board single boards are scrapped;
if the circuit is short-circuited, taking 1/4 point of one side of the marking ring 3 with the minimum real-time layer deviation of the connecting line, making a perpendicular line of the connecting line passing through the point, taking the circuit board single board on one side of the two sides of the connecting line through which the real-time layer deviation is larger to perform electrical detection, if the circuit is well connected, passing all the circuit board single boards on one sides of the marking ring 3 with the minimum real-time layer deviation of the perpendicular line and the perpendicular line close to the layer deviation, and scrapping the rest circuit board single boards;
and repeating the steps until no complete circuit board single board exists between the vertical line and the marking ring 3 with the minimum real-time layer deviation, and then the whole circuit board is scrapped in a whole version mode.
The implementation principle of the embodiment is as follows: the dislocation condition of the circuit board generally comprises translational dislocation and rotational dislocation, the real-time layer deviation detected at each marking ring 3 after the translational dislocation is consistent, and when partial deviation and partial non-deviation of different marking rings 3 on the whole circuit board occur, the deviation of the circuit board is indicated to be caused by the translation between each layer of main substrates in the plane of the main substrates and also to have dislocation and rotation; the offset of the circuit board single plate on the side with larger real-time layer offset is larger than that of the circuit board single plate on the other side of the connecting line, if the circuit board single plate on the side is not short-circuited, the perpendicular line and the circuit board single plate on the side of the marking ring 3 with the perpendicular line close to the minimum real-time layer offset cannot be short-circuited, and unqualified products are further prevented from flowing in. The qualified part in the whole half-offset circuit board is cut and utilized, so that the scrapped quantity of the circuit board is greatly reduced, the scrapping of the whole circuit board is avoided, the waste of raw materials and procedures is reduced, and the cost is saved.
The embodiments of the present invention are preferred embodiments of the present invention, and the scope of the present invention is not limited by these embodiments, so: all equivalent changes made according to the structure, shape and principle of the invention are covered by the protection scope of the invention.
Claims (2)
1. A method for processing an offset circuit board is characterized in that a marking ring (3) is manufactured: the mark rings (3) are etched at the same position on the surface of each main substrate, the diameters of the mark rings (3) are the same, and the method is characterized in that: comprises full-bias circuit board processing and half-bias circuit board processing,
the full-bias circuit board is a circuit board with each marking circular ring (3) biased, and the full-bias circuit board is processed to be scrapped in a full version;
the semideviated circuit board is a circuit board with at least one unbiased position in each marking ring (3), and the semideviated circuit board processing method comprises the following steps:
(1) And (3) wiring: drawing a straight line from the marking ring (3) with the minimum real-time layer offset to the marking ring (3) with the maximum real-time layer offset;
(2) Making a vertical line: making a perpendicular line of the connection;
(3) Detection and excision: taking the circuit board single board through which the perpendicular line passes for electrical detection, if the circuit is well connected, all circuit board single boards through which the perpendicular line passes and on one side of the marking circular ring (3) with the perpendicular line close to the minimum real-time layer deviation amount are qualified, and the rest circuit board single boards are scrapped;
if the circuit is short-circuited, taking 1/4 point of one side of the connecting line close to the marking ring (3) with the minimum real-time layer deviation, making a perpendicular line of the connecting line passing through the point, taking the circuit board single board passing through the perpendicular line for electrical detection, if the circuit is well connected, passing through the perpendicular line and enabling the perpendicular line to be close to one side of the marking ring (3) with the minimum real-time layer deviation, wherein all circuit board single boards are qualified, and the rest circuit board single boards are scrapped;
and repeating the steps until no complete circuit board single board exists between the vertical line and the marking circular ring (3) with the minimum real-time layer deviation, and scrapping the whole circuit board in full page.
2. The method as claimed in claim 1, wherein the method further comprises: and selecting the circuit board single board on the side with larger real-time layer deviation from the two sides of the connecting line for electrical detection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211182811.9A CN115568115A (en) | 2020-01-18 | 2020-01-18 | Method for processing offset circuit board |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010056264.4A CN111182746B (en) | 2020-01-18 | 2020-01-18 | Circuit board layer deviation judging method |
| CN202211182811.9A CN115568115A (en) | 2020-01-18 | 2020-01-18 | Method for processing offset circuit board |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010056264.4A Division CN111182746B (en) | 2020-01-18 | 2020-01-18 | Circuit board layer deviation judging method |
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| CN115568115A true CN115568115A (en) | 2023-01-03 |
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| CN202211182811.9A Pending CN115568115A (en) | 2020-01-18 | 2020-01-18 | Method for processing offset circuit board |
| CN202010056264.4A Active CN111182746B (en) | 2020-01-18 | 2020-01-18 | Circuit board layer deviation judging method |
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| CN202010056264.4A Active CN111182746B (en) | 2020-01-18 | 2020-01-18 | Circuit board layer deviation judging method |
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| CN114889151A (en) * | 2022-04-08 | 2022-08-12 | 赣州市同兴达电子科技有限公司 | Method suitable for trimming, photographing and aligning corners of sandwich OCA (optical clear adhesive) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005072227A (en) * | 2003-08-25 | 2005-03-17 | Matsushita Electric Ind Co Ltd | Multilayer circuit board and method for inspecting positional deviation between layers thereof |
| TW200808147A (en) * | 2006-07-24 | 2008-02-01 | Siliconware Precision Industries Co Ltd | Method for inspecting the process of cutting semiconductor package and printed circuit board for the semiconductor package |
| JP5359757B2 (en) * | 2009-10-08 | 2013-12-04 | パナソニック株式会社 | Multi-layer printed wiring board position recognition mark |
| CN102032885B (en) * | 2010-08-31 | 2013-05-15 | 北大方正集团有限公司 | Printed circuit board, method and device for detecting layer-to-layer registration of circuit graphs at two surfaces thereof |
| CN109561605B (en) * | 2018-12-14 | 2020-04-21 | 深圳市景旺电子股份有限公司 | Method for capturing expansion and shrinkage data of multi-layer board in pressing and manufacturing method of multi-layer board |
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| CN111182746B (en) | 2022-11-22 |
| CN111182746A (en) | 2020-05-19 |
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